KR20070015984A - Embedded System Capable Of Hardware Self Test And Self Test Method In That Embedded System - Google Patents

Abstract

The present invention provides an embedded system capable of hardware self-diagnosis and a self-diagnostic method in the system using the Joint Test Action Group (JTAG) port implemented in an embedded system. It is about.

The present invention assigns an input / output terminal implemented in a processor of an embedded system to its own JTAG port to access registers and peripherals inside the processor, thereby enabling self-diagnosis of hardware defects in the embedded system. In addition, the hardware self-diagnosis results can be output to the user or reported to the outside through wired / wireless communication so that they can cope with the development process of the embedded system or after service (AS) situation more quickly.

Embedded System, JTAG Port, Bad Hardware, Self Diagnostic, Processor, Peripheral

Description

Embedded System Capable Of Hardware Self Test And Self Test Method In That Embedded System}

1 is a block diagram for detecting a hardware failure of a conventional embedded system.

2 is a block diagram illustrating a built-in system capable of hardware self-diagnosis according to the present invention.

3 is a flowchart illustrating a hardware self-diagnosis operation in an embedded system according to the present invention.

Explanation of symbols on the main parts of the drawings

21: user interface 22: display

23: communication processing unit 24: memory unit

25-1: master processor 25-2, 25-3: subprocessor

26-1 ~ 26-3: Peripheral device

The present invention relates to hardware diagnosis of an embedded system (Embedded System), in particular, hardware self-diagnosis capable of diagnosing the hardware itself by using a Joint Test Action Group (JTAG) port implemented in the embedded system is possible It relates to an embedded system and a hardware self-diagnosis method in the system.

In general, in the case of electronic products, there are various methods for diagnosing a hardware defect. For example, after connecting a separate test equipment (eg, an oscilloscope, a multimeter, etc.) to an electronic product, a technician directly There is a method of diagnosing a hardware defect by checking a signal of an electronic product.

In addition, the recent embedded system consumes a small amount of power, and is mainly equipped with an ARM (Advanced RISC Machines) core, and also includes a JTAG port (Joint Test Action Group Port) for debugging. Such an embedded system has a JTAG port on a JTAG port existing in the master processor 11 or a JTAG port of a JTAG module separately configured outside the master processor 11 as shown in FIG. It configures the interface to connect the external PC 15, which is the main body controlling the port, connects the test equipment 16 to the peripheral device 12, and in this state, JTAG transmits a test signal transmitted from the external PC 15. After passing through the port to the processor 11 and peripherals 12, the test equipment 16 is used to determine the signal transmitted to the peripheral device 12. By directly checking whether the test signal transmitted from the PC 15 is the same, a method of determining whether or not a product is defective is used.

In this regard, when electronic products having an embedded system structure are sold to a consumer and malfunctioned due to a user's mistake or a long-term use, the defect is caused by hardware rather than software. Since the first subject to discover is not a technician but a general consumer, the general consumer has to visit a manufacturer or a service center or report a product defect by using a communication means (such as a telephone or the Internet).

In addition, conventionally, in diagnosing a defective product for the embedded system 10, since the JTAG port implemented for debugging in the embedded system 10 cannot proceed simultaneously with input and output, that is, the external PC 15 Outputs a signal to the JTAG port of the embedded system 10 and at the same time cannot receive a signal through the JTAG port, a technician can determine whether the product is defective without using a separate test equipment 16. There was no downside.

In particular, in recent years, with the development of technology, unlike a conventional one, a single electronic product is equipped with a plurality of processors to implement additional functions in addition to the master processor (for example, a mobile terminal with a master processor for call processing function for the call processing function) It is equipped with camera processor, Bluetooth processor, and MP3 processor at the same time.) Also, each processor is becoming smaller, modular, and ball grid array (BGA) type. There is a problem that it is becoming more complicated and difficult to diagnose whether the equipment is a master processor failure, an additional processor failure, or a non-processor peripheral device. Pins to check PCB (Printed Ci) rcuit Board) There is a problem that it is hidden in the board and it is impossible to diagnose the defect directly by using the test equipment.

The present invention is to solve the problems described above, the object is to assign an input / output terminal implemented in the processor of the embedded system to its own JTAG port to access the registers and peripherals inside the processor, This enables self-diagnosis of hardware defects in the embedded system itself.

Another object of the present invention is to enable the embedded system to output its hardware self-diagnosis result to the user or to report to the outside through wired / wireless communication.

Another object of the present invention is to enable a system to output and report hardware self-diagnosis results in an embedded system, so that the system can cope with a development process or an AS (After Service) situation more quickly.

A feature of the present invention for solving the above object is, in an embedded system having at least one processor and a peripheral device embedded therein an Advanced RISC Machines (ARM) core including a JTAG or JTAG, A user interface unit for receiving and delivering a test command for requesting diagnosis; A display unit which outputs the hardware self-diagnosis result to a user; A memory unit for storing software and information necessary for driving the embedded system and software and test reference information for performing the hardware self-diagnosis function; The software and the test reference information stored in the memory unit to control the overall operation by using the software and information necessary for driving the system, the hardware self-diagnosis software and test reference information stored in the memory unit when a test command requesting a hardware self-diagnosis is inputted Hardware self-diagnosis through the input / output terminal for test signal, test data input / output terminal and input / output terminal for test result input while controlling JTAG's TAP controller test operation mode through input / output terminal for test operation mode control The present invention provides an embedded system capable of performing hardware self-diagnosis including a master processor performing a function and outputting a hardware self-diagnosis result through the display unit.

Here, the test reference information may include a JTAG identification code of each processor used when performing a hardware self-diagnostic function, specific state information for setting each processor internal module to a self-diagnostic state, and specific setting for setting a peripheral device to a self-diagnostic state. It is characterized in that the status information.

The above-described embedded system capable of hardware self-diagnosis, in performing the hardware self-diagnosis, receives a test command requesting hardware self-diagnosis and transmits it to a master processor, or transmits the hardware self-diagnosis result to an external device via wire / wireless communication. It further comprises a communication processing unit for reporting to.

In addition, the master processor reads a JTAG identification code inside the processor in a state in which the TAP controller of the JTAG is set to the internal test mode, diagnoses whether the JTAG is defective, and sets the processor internal modules to a specific state when the JTAG is normal. After that, the register value of the internal modules of the processor is read to diagnose whether the internal modules are defective. If the internal modules of the processor are normal, the peripheral device connected to its input / output terminal is set to a specific state, and then the JTAG Setting the TAP controller to external test mode to read pin status information of the peripheral device while the test data input terminal and the test data output terminal are connected to the boundary scan register to diagnose whether the peripheral device is defective or not. Performing a series of hardware self-diagnostic functions It characterized.

In addition, when the at least one subprocessor and a peripheral device exist in the embedded system, the master processor controls the TAP controller test operation mode of the JTAG of each processor through the input / output terminal for controlling the test operation mode, and input / output for the test signal. Terminals and test data input / output terminals and input / output terminals for inputting test results to perform a series of hardware self-diagnosis functions for diagnosing hardware defects for each processor and peripheral devices present in the embedded system. The hardware self-diagnosis result is output through the display unit.

In this case, the subprocessor includes a TAP controller of a JTAG in which a test operation mode is controlled by a master processor, and a test mode selection and a test clock terminal thereof are connected to an input / output terminal for controlling a test operation mode of the master processor. The test operation mode of the TAP controller is controlled, and the test data output terminal of the previous processor and its own test data input terminal are connected according to the processor connection order to provide a predetermined sub test path, and the own test data output terminal is mastered. It is connected to the input / output terminal of the processor and transmits a series of test result signals to the master processor.

In addition, the master processor directly sets a test data input terminal and a test data output terminal serving as a sub test path by setting the TAP controller of the JTAG of the other processors (including the master processor) except the sub-processor to be self-diagnostic to the bypass mode. Connected to the corresponding subprocessor and its subprocessors through its input / output terminals for its own test signals, the test data input / output terminals directly connected above and the test data input terminals of the subprocessors to be self-diagnosed. The hardware self-diagnosis function for the peripheral device is performed.

In another aspect of the present invention, there is provided a hardware diagnostic method in an embedded system having an advanced RISC Machines (ARM) core including a JTAG or at least one processor and a peripheral device having a JTAG therein. Diagnosing a JTAG failure by reading a JTAG identification code in a state where the TAP controller of the JTAG is set to the internal test mode by executing hardware self-diagnosis software in the master master processor; If the JTAG is normal, setting a processor internal module to a specific state for self-diagnosis, and then reading a register value of the processor internal modules to diagnose whether the processor internal module is defective; When the internal module of the master processor is normal, the peripheral device connected to the input / output terminal is set to a specific state for self-diagnosis, and the pin state information of the peripheral device is read after setting the TAP controller of the JTAG to an external test mode. Diagnosing whether a corresponding peripheral device is defective; The present invention provides a hardware self-diagnosis method in an embedded system including a process of outputting a hardware diagnosis result to a user through a display unit, or reporting to the outside through wired / wireless communication.

The diagnosing of the JTAG failure may include: setting a TAP controller of the JTAG to an internal test mode by controlling a test mode selection terminal and a test clock terminal through an input / output terminal for controlling a test operation mode in a master processor; Reading a JTAG identification code inside the processor through an input / output terminal for a test signal and a test data input terminal of the master processor, and outputting the JTAG identification code as a test result to a test data output terminal; Receiving a JTAG identification code read as the test result through an input / output terminal for inputting a test result of the master processor, and then checking whether the same as the JTAG identification code stored in the memory unit; And outputting a hardware diagnostic result of JTAG normal when the JTAG identification code read above and the JTAG identification code of the memory unit are the same.

The diagnosing whether the internal processor module is defective may include: setting the internal modules to a specific state for self-diagnosis to diagnose whether the internal module of the master processor is defective; Reading register values of the internal modules of the processor through an input / output terminal and a test data input terminal for a test signal of the master processor and outputting the register values to the test data output terminals as a test result; Register value of self-diagnosis status information about internal modules stored in the memory unit after receiving the register value of the internal modules read as the test result through the input / output terminal for inputting the test result of the master processor Checking whether it is equal to; And outputting a hardware diagnosis result of an internal module failure if the register values of the internal modules of the processor and the register values of the internal modules of the memory unit are the same, and a hardware diagnosis result of an internal module failure if not identical. Characterized in that.

In addition, the process of diagnosing whether the peripheral device is defective may include: setting a corresponding peripheral device to a specific state for self-diagnosis to diagnose whether the peripheral device connected to the master processor is defective; By controlling the test mode selection terminal and the test clock terminal through the test operation mode control input / output terminal of the master processor, the TTAG controller of the JTAG is set to the external test mode so that the test data input terminal and the test data output terminal are bounded scan registers. Connecting to; Reading pin state information of the peripheral device through a test signal input / output terminal and a test data input terminal of the master processor and outputting the pin state information to the test data output terminal as a test result; After receiving the pin state information of the peripheral device read as the test result through the input / output terminal for inputting the test result of the master processor, and confirming the same as the self-diagnostic state information of the peripheral device stored in the memory unit. Steps; And outputting a hardware diagnostic result of a normal peripheral device if the pin state information of the peripheral device read above is the same as the peripheral device self-diagnostic status information of the memory unit, and outputting a hardware diagnostic result of a peripheral device failure if not identical. It is characterized by.

In the above-described embedded system, the hardware self-diagnosis method includes a master processor when a hardware self-diagnosis request is made to other sub-processors and peripheral devices present in the embedded system, and between the master processor and the sub-processor to be self-diagnosed. The method may further include performing hardware self-diagnosis on the subprocessor and the peripheral device in a state in which the sub test path is implemented by setting the TAP controller of the JTAG of each located processor to the bypass mode.

In addition, the hardware self-diagnosis of the subprocessor and the peripheral device may be performed by the master processor through an input / output terminal for controlling a test operation mode, and a test mode of each subprocessor located on the subtest path. Controlling the selection terminal and the test clock terminal to set the TAP controller of the JTAG to the bypass mode to directly connect the test data input terminal and the test data output terminal of each processor to implement a sub test path; In the state in which the TAP controller of the JTAG of the subprocessor is set to the internal test mode by controlling the test mode selection terminal and the test clock terminal of the subprocessor to be self-diagnosed through the input / output terminal for controlling the test operation mode in the master processor. Diagnosing whether the JTAG of the subprocessor and the internal module are defective; The master processor sets the peripheral device connected to the subprocessor to a specific state for self-diagnosis, sets the JTAG TAP controller of the subprocessor to the external test mode, and reads pin state information of the peripheral device connected to the subprocessor. Diagnosing whether a corresponding peripheral device is defective; And outputting a hardware diagnosis result of the subprocessor and the peripheral device in the above step to the user through the display unit in the master processor or to the outside through wired / wireless communication.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, in diagnosing a hardware defect for an electronic product having an embedded system structure, the input / output terminal of the processor is assigned to a JTAG port to access a register and a peripheral device inside the processor to self-diagnose the defect. In addition, if multiple processors are installed, the self-diagnosis function is performed by accessing the JTAG TAP (Test Access Port) controller and the boundary scan register of another processor through the input / output terminals of the master processor. This provided embedded system has a configuration as shown in FIG.

That is, the embedded system capable of hardware self-diagnosis according to the present invention has a user interface 21, a display 22, a communication processor 23, a memory 24, and the like, as illustrated in FIG. 2. And at least one processor 25-1 to 25-3 and peripheral devices 26-1 to 26-3.

In FIG. 2, the processor 25-1 to 25-3 and the peripheral devices 26-1 to 26-3 are each provided with three. However, in the present invention, the processors 25-1 to 25-3 are illustrated. 3) may include only the master processor 25-1, or may include one master processor 25-1 and a plurality of subprocessors 25-2 and 25-3, and each processor 25-1. Peripheral devices 26-1-26-3 connected to ˜ 25-3 may also exist if equipped with a processor, or otherwise do not.

Here, although the user interface 21, the display 22, and the communication processor 23 are also included in the peripheral device for the hardware self-diagnosis, the hardware self-diagnosis of the present invention performs a different function from the general peripheral device. That is, the user interface 21 is implemented as a keypad or a touch screen, and receives a test command for requesting hardware self-diagnosis and delivers the test command to the master processor 25-1, and the display unit 22 is an LCD. It is implemented as a screen or a speaker, and serves to output the hardware self-diagnosis result to the user, the communication processor 23 receives the test command for requesting the hardware self-diagnosis and delivers it to the master processor 25-1, It reports the hardware self-diagnosis result to the outside through wired / wireless communication.

The memory unit 24 includes software and various kinds of information necessary for driving an electronic product that is an embedded system, software necessary for performing a hardware self-diagnosis function, and various kinds of test reference information (that is, each processor 25-1 to 25-3). JTAG identification code, specific status information for setting each processor internal module to the self-diagnostic state, and specific status information for setting the peripheral devices 26-1 to 26-3 to the self-diagnostic state. Do it.

In addition, the master processor 25-1 and each of the subprocessors 25-2 and 25-3 mean an ARM (Advanced RISC Machines) core or JTAG including JTAG in an architecture. Here, the JTAG includes a JTAG connected through a pipeline inside the ARM core, and a JTAG existing as a module outside the ARM core.

The master processor 25-1 controls the overall operation of the electronic product using software and various information necessary for driving the electronic product stored in the memory unit 24, and also controls the user interface unit 21 and the communication processing unit 23. When the hardware self-diagnosis command is inputted through the I / O terminal I / O2 to I / O3 by using the hardware self-diagnosis software stored in the memory unit 24 and various test reference information. Test data input / output terminals (TDI, TDO) and other input / output terminals (I / O4 ~ I /) with control of the TAP controller test operation mode of the JTAG of each processor (25-1 to 25-3) including O6) performs a series of hardware self-diagnosis functions to diagnose hardware defects on the processors 25-1 to 25-3 and peripheral devices 26-1 to 26-3. Display the diagnostic result (22) Output to the user or report to the outside through the communication processing unit (23). Here, the input / output terminals I / O1 to I / O6 of the master processor 25-1 are terminals configured as boundary scan cells that can set two states, such as input and output, in the master processor 25-1. (Eg, GPIO terminal, address and data bus, etc.).

Each of the subprocessors 25-2 and 25-3 is a processor added to provide additional functions implemented in electronic products, and is tested by the master processor 25-1 in a test operation mode (external test mode, bypass mode). It includes a TAP controller of the JTAG is controlled, the test mode selection and test clock terminals (TMS, TCK) and the input / output terminals (I / O2, I / O3) of the master processor 25-1 is connected to the TAP controller The test operation mode of the controller is controlled, and a path in which the test data output terminal TDO and its test data input terminal TDI of the previous processor are connected and the predetermined test signal is transmitted according to the processor connection order, that is, the sub test path The test data output terminal (TDO) is connected to the input / output terminals (I / O4 to I / O6) of the master processor 25-1 to transmit a series of test result signals to the master processor 25-1. Deliver it.

Peripherals 26-1 to 26-3 are connected to respective processors 25-1 to 25-3 and through the input / output terminals (I / O) of the processors 25-1 to 25-3. Controlled.

The JTAG signal line connection structure of the master processor 25-1 and the subprocessors 25-2 and 25-3 will be described in more detail. The master processor 25-1 includes a TAP controller and each subprocessor of the internal JTAG. Each processor 25-1 to 25-3 at its input / output terminals I / O2 and I / O3 to control the test operation mode for the TAP controller of the JTAG of (25-2, 25-3). The test mode select terminal (TMS) and the test clock terminal (TCK) are respectively connected, and their input / output terminals (I / O1) and the test data input terminals (TDI) are connected. Then, the master processor itself for hardware self-diagnosis of each subprocessor 25-2, 25-3 and the peripheral devices 26-2, 26-3 connected to the subprocessors 25-2, 25-3. Connects the test data output terminal TDO of the test data input terminal TDI of the adjacent subprocessor 25-2 and the adjacent subprocessor 25-2 directly connected to the master processor 25-1. For the remaining subprocessors 25-3, a series of sub test paths are implemented by connecting the test data output terminal TDO of the adjacent sub processor and its test data input terminal TDI.

In addition, each of the subprocessors 25-2 and 25-3 including the master processor 25-1 may transmit a signal to the master processor 25-1 to transmit a signal to the master processor 25-1 as a test result for hardware self-diagnosis. The test data output terminal TDO is connected to the input / output terminals I / O4 to I / O6 of the master processor 25-1.

The hardware self-diagnosis operation in the embedded system capable of such hardware self-diagnosis will be described in detail with reference to FIG. 3.

First, the driving of the embedded system is generally controlled by the master processor 25-1, and the master processor 25-1 drives the entire electronic product by using driving software and various information stored in the memory unit 24. To control.

The hardware self-diagnosis of the embedded system may be performed by a user or a technician by directly operating a keypad or a touch screen, or remotely through wired / wireless communication. In this case, the user interface 21 may use a keypad or touch. It detects the screen operation, receives a test command requesting hardware self-diagnosis through the keypad or touch screen, and transfers the test command to the master processor 25-1. The communication processing unit 23 performs the hardware self-through the wire / wireless communication. The test command requesting the diagnosis is received and transferred to the master processor 25-1.

When the hardware self-diagnostic test command is input through the user interface unit 21 or the communication processing unit 23 (step S31), the master processor 25-1 stores the hardware self-diagnosis software stored in the memory unit 24. And hardware self-diagnosis for each of the processors 25-1-25-3 and the peripheral devices 26-1-26-3 using various test reference information.

That is, the master processor 25-1 executes the hardware self-diagnosis software, and first of all, the test mode selection terminal TMS and the test clock terminal (I / O2, I / O3) through the test operation mode control input / output terminals I / O2 and I / O3. TCK) to set the JTAG's TAP controller to the internal test mode (INTEST) (step S32) .In this state, the input / output terminal (I / O1) for the test signal and the test signal for diagnosing the JTAG failure of the processor itself. After reading the JTAG identification code inside the processor through the test data input terminal (TDI), it is output to the test data output terminal (TDO) as a test result (step S33).

In addition, the test result signal output to the test data output terminal TDO of the master processor 25-1, that is, the JTAG identification code read above, is connected to the test data output terminal TDO of the master processor 25-1. The master processor 25-1 inputs to the test result input / output terminal I / O4, and the master processor 25-1 checks whether the JTAG identification code read as the test result is the same as the JTAG identification code stored in the memory unit 24. It confirms (step S34).

At this time, if the JTAG identification code read as a test result is not the same as the JTAG identification code stored in the memory unit 24, this means that the JTAG is abnormal, and thus the master processor 25-1 diagnoses the hardware self as a JTAG failure. The result is output to the user via the display unit 22 or reported to the outside via the communication processing unit 23 (step S35). For reference, the first reason for JTAG failure in hardware self-diagnosis is that if the JTAG of the master processor 25-1 is defective, other processors 25-2 to 25-3 and each peripheral device ( This is because hardware self-diagnosis for 26-1 ~ 26-3) is impossible.

However, if the JTAG identification code read as the test result is the same as the JTAG identification code stored in the memory unit 24, this means that the JTAG is normal, and then the defects of the internal modules of the master processor 25-1 are bad. The master processor 25-1 performs a test using self-diagnostic status information of an internal module of the master processor 25-1 stored in the memory unit 24 as test reference information. Through the signal input / output terminal I / O1 and the test data input terminal TDI, internal modules thereof are set to a specific state for self-diagnosis (step S36).

In this way, after setting the internal modules of the master processor 25-1 to a specific state, the master processor 25-1 performs input / output terminals I / O1 for test signals to diagnose whether or not the internal modules are defective. And the register values of the internal modules of the processor through the test data input terminal (TDI) and output them to the test data output terminal (TDO) as a test result (step S37) and output to the test data output terminal (TDO). The test result signal, that is, the register value of the internal modules read above, is input to the input / output terminal I / O4 for inputting the test result of the master processor 25-1 connected to the test data output terminal TDO, and the master The processor 25-1 registers the register value of the internal modules read as the test result, and becomes a self-diagnostic state information for the internal modules stored in the memory unit 24. Is the same make sure (step S38).

At this time, if the register value of the internal processor modules read as a test result is not the same as the register value of the internal modules stored in the memory unit 24, this means that the internal processor module is abnormal, and thus the master processor 25-. 1) outputs the hardware self-diagnosis result of the processor internal module failure to the user through the display unit 22 or reports to the outside through the communication processing unit 23 (step S39).

However, if the register value of the processor internal modules read as the test result is the same as the register value for the internal modules stored in the memory unit 24, this means that the processor internal modules are normal. As a result, the peripheral device 26-1 connected to the master processor 25-1 is diagnosed as defective. For this purpose, the master processor 25-1 is a peripheral device stored as test reference information in the memory unit 24. Peripherals connected to a given input / output terminal (I / O) via input / output terminals (I / O1) and test data input terminals (TDI) for test signals using self-diagnostic status information for device 26-1. The device 26-1 is set to a specific state for self diagnosis (step S40).

After setting the peripheral device 26-1 connected with the master processor 25-1 to a specific state in this manner, the master processor 25-1 diagnoses whether the peripheral device 26-1 connected with the master processor is defective. In order to control the test mode selection terminal (TMS) and the test clock terminal (TCK) of the processor through the input / output terminals (I / O2 and I / O3) for test operation mode control, JTAG's TAP controller is controlled by the external test mode (EXTEST). ), The test data input terminal TDI and the test data output terminal TDO are connected to the boundary scan register (step S41).

Thereafter, the master processor 25-1 is connected to the input / output terminal I / O to which the peripheral device 26-1 is connected through the input / output terminal I / O1 for the test signal and the test data input terminal TDI. After reading the current state information (i.e., pin state information of the peripheral device 26-1, High or Low), it is output to the test data output terminal TDO as a peripheral device test result (step S42). The peripheral device test result signal output to the output terminal TDO, that is, the pin state information of the peripheral device 26-1 previously read is a test of the master processor 25-1 connected to the test data output terminal TDO. Input to the input / output terminal I / O4 for result input, the master processor 25-1 stores the pin state information of the peripheral device 26-1 read as the test result in the memory unit 24. It is confirmed whether or not the same as the self-diagnosis status information of the peripheral device 26-1 present (step S43).

At this time, when the pin state information of the peripheral device 26-1 read as a test result is not the same as the self-diagnostic state information of the peripheral device 26-1 stored in the memory unit 24, this is the peripheral device 26. -1) means that the abnormality, the master processor 25-1 outputs the hardware self-diagnosis result of the defective peripheral device connected to the processor itself to the user through the display unit 22, or the communication processor 23 The report is made to the outside via the step S44.

However, when the pin state information of the peripheral device 26-1 read as a test result is the same as the self-diagnostic state information of the peripheral device 26-1 stored in the memory unit 24, the peripheral device connected to the processor itself is used. Since the symbol 26-1 is normal, the master processor 25-1 outputs a corresponding hardware self-diagnosis result to the user through the display unit 22, or reports to the outside through the communication processor 23. After that, a series of hardware self-diagnosis is completed for the master processor 25-1 and the peripheral device 26-1 connected to the master processor 25-1 (step S45).

In addition, in the present invention, the master processor 25-1 is a hardware self-diagnosis function as follows, and peripheral devices connected to each of the subprocessors 25-2 and 25-3 and their subprocessors 25-2 and 25-3. A series of hardware self-diagnostics are performed for (26-2, 26-3), first with respect to the adjacent subprocessor 25-2 connected to the test data output terminal (TDO) of the master processor 25-1. The hardware self-diagnosis is performed. For this purpose, the master processor 25-1 first checks the processor's own test mode selection terminal (TMS) and the test through the input / output terminals I / O2 and I / O3 for controlling the test operation mode. Control the clock terminal (TCK) to set the JTAG's TAP controller to bypass mode (BYPASS) so that the test data input terminal (TDI) and the test data output terminal (TDO) are connected in series directly without connecting to the boundary scan register. do. That is, in order to bypass the JTAG of the master processor 25-1 and perform hardware self-diagnosis on the subprocessor 25-2, the TAP controller of the JTAG of the master processor 25-1 is set to the bypass mode to test data. The sub test path connected to the input terminal TDI and the test data output terminal TDO is implemented.

In this state, the master processor 25-1 performs hardware self-diagnosis on the subprocessor 25-2, and the hardware self-diagnosis operation is performed by performing a series of operations on the master processor 25-1 described with reference to FIG. 3. This is done in a similar manner to the hardware self-diagnosis operation.

That is, the master processor 25-1 may first test the test mode selection terminal TMS of the subprocessor 25-2, which is a hardware self-diagnosis target, through the input / output terminals I / O2 and I / O3 for test operation mode control. ) And the test clock terminal TCK to set the TAP controller of the JTAG of the subprocessor 25-2 to the internal test mode INTEST. In this state, the JTAG of the subprocessor 25-2 is bad. The JTAG identification code of the subprocessor 25-2 is read to diagnose whether the master processor owns the input / output terminal I / O1 for the test signal and the test data input / output terminal (TDI / TDO). And the JTAG identification code of the subprocessor 25-2 through the test data input terminal TDI of the subprocessor 25-2, and the JTAG identification code of the subprocessor 25-2 thus read. Test the subprocessor 25-2 as a test result. It is output to the data output terminal (TDO).

The test result signal output to the test data output terminal TDO of the subprocessor 25-2, that is, the JTAG identification code of the sub processor 25-2 read previously, is used to test the subprocessor 25-2. The input / output terminal I / O5 for inputting the test result of the master processor 25-1 connected to the data output terminal TDO is input to the input / output terminal I / O5, and the master processor 25-1 reads the subprocessor ( It is checked whether the JTAG identification code of 25-2) is the same as the JTAG identification code of the subprocessor 25-2 stored in the memory unit 24.

At this time, when the JTAG identification code of the subprocessor 25-2 read as a test result is not the same as the JTAG identification code of the subprocessor 25-2 stored in the memory unit 24, the subprocessor 25- Since the JTAG of 2) is abnormal, the master processor 25-1 outputs a hardware self-diagnosis result of the JTAG failure of the subprocessor 25-2 to the user through the display unit 22, or the communication processing unit. (23) will report to the outside.

However, when the JTAG identification code of the subprocessor 25-2 read as the test result is the same as the JTAG identification code of the subprocessor 25-2 stored in the memory unit 24, this is the subprocessor 25-2. This means that the JTAG is normal, and then it is diagnosed whether or not the internal modules of the subprocessor 25-2 are defective. For this purpose, the master processor 25-1 transmits the test reference information to the memory unit 24. The input / output terminal (I / O1) for the test signal of the master processor and the test data input / output terminal (TDI / TDO) using the self-diagnosis status information of the internal module of the stored subprocessor 25-2. And internal modules of the subprocessor 25-2 to a specific state for self-diagnosis through the test data input terminal TDI of the subprocessor 25-2.

In this way, after setting the internal modules of the subprocessor 25-2 to a specific state, the master processor 25-1 inputs / receives a test signal for the master processor itself to diagnose whether the internal modules of the subprocessor 25 are defective or not. After reading the register values of the subprocessor internal modules through the output terminal I / O1, the test data input / output terminal TDI / TDO, and the test data input terminal TDI of the subprocessor 25-2, The test result is output to the test data output terminal TDO of the subprocessor 25-2 as a test result, and the test result signal output to the test data output terminal TDO of the subprocessor 25-2, that is, the previous reading. The register value of one subprocessor internal module is input to an input / output terminal I / O5 for inputting a test result of the master processor 25-1 connected to the test data output terminal TDO of the subprocessor 25-2. In addition, the master processor 25-1 is a processor for internal modules of the subprocessor 25-2 in which the register values of the internal modules of the subprocessor 25-2 read as test results are stored in the memory unit 24. It is checked whether it is the same as the register value which is the diagnostic status information.

At this time, when the register values of the internal modules of the subprocessor 25-2 read as a test result are not the same as the register values of the internal modules of the subprocessor 25-2 stored in the memory unit 24, the sub values of the internal modules of the subprocessors 25-2 are stored. Since the internal module of the processor 25-2 is abnormal, the master processor 25-1 outputs a hardware self-diagnosis result indicating that the internal module of the sub processor 25-2 is defective to the user through the display unit 22. Or, it is reported to the outside through the communication processing unit 23.

However, if the register values of the internal modules of the subprocessor 25-2 read as the test results are the same as the register values of the internal modules of the subprocessor 25-2 stored in the memory unit 24, the subprocessor ( 25-2) means that the internal modules are normal, and as the next hardware self-diagnosis function, it diagnoses whether the peripheral device 26-2 connected to the subprocessor 25-2 is defective. -1) uses the self-diagnosis status information of the peripheral device 26-2 of the subprocessor 25-2 stored as the test reference information in the memory unit 24 to input / output terminals for its own test signal ( I / O1, the test data input / output terminal (TDI / TDO), and the test data input terminal (TDI) of the subprocessor 25-2 through the input / output terminal I of the subprocessor 25-2. Device (26-2) connected to the It is set to a specific state.

After setting the peripheral device 26-2 connected to the subprocessor 25-2 in this state, the master processor 25-1 performs the peripheral device 26-2 connected to the subprocessor 25-2. In order to diagnose the failure, the test mode selection terminal (TMS) and the test clock terminal (TCK) of the subprocessor 25-2 are controlled by the input / output terminals I / O2 and I / O3 for controlling the test operation mode. By setting the JTAG TAP controller to the external test mode EXTEST, the test data input terminal TDI and the test data output terminal TDO of the subprocessor 25-2 are connected to the boundary scan register. At this time, since the TAP controller of the JTAG of the master processor 25-1 maintains the bypass mode (BYPASS), the test data input terminal (TDI) and the test data output terminal (TDO) are connected to the boundary scan register. They are connected in series. That is, the TAP of the JTAG of the master processor 25-1 to bypass the JTAG of the master processor 25-1 and perform hardware self-diagnosis on the peripheral device 26-2 connected to the subprocessor 25-2. The controller is set to the bypass mode (BYPASS), and the TAP controller of the JTAG of the subprocessor 25-2 is set to the external test mode (EXTEST).

In this state, the master processor 25-1 has its own input / output terminal I / O1 for test signals, test data input / output terminals (TDI / TDO), and test data input terminals of the subprocessor 25-2. Current state information of the input / output terminal I / O of the subprocessor 25-2 to which the peripheral device 26-2 is connected via (TDI) (that is, the peripheral device connected to the subprocessor 25-2) After reading the pin state information 26-2) of the pin state, High or Low, it is output to the test data output terminal TDO as a test result of the peripheral device connected to the subprocessor 25-2, and the test data output terminal ( TDO) outputs the peripheral device test result signal, that is, the pin state information of the peripheral device 26-2 connected to the previously read subprocessor 25-2, and the test data output terminal of the subprocessor 25-2. To the input / output terminal (I / O5) for inputting the test result of the master processor 25-1 connected to (TDO) The master processor 25-1 is a subprocessor 25- with the pin state information of the peripheral device 26-2 connected to the subprocessor 25-2 read as the test result stored in the memory unit 24. The self-diagnosis status information of the peripheral device 26-2 connected to 2) is checked.

At this time, the peripheral device 26 connected to the subprocessor 25-2 stored in the memory unit 24 stores pin state information of the peripheral device 26-2 connected to the subprocessor 25-2 read as a test result. If it is not the same as the self-diagnosis status information of -2), it means that the peripheral device 26-2 is abnormal, and thus, the master processor 25-1 is a hardware self-managed device that is connected to the subprocessor 25-2. The diagnosis result may be output to the user through the display unit 22 or may be reported to the outside through the communication processor 23.

However, the peripheral device 26 connected to the subprocessor 25-2 stored in the memory unit 24 has pin state information of the peripheral device 26-2 connected to the subprocessor 25-2 read as a test result. If the same as the self-diagnostic status information of -2), this means that the peripheral device 26-2 connected to the subprocessor 25-2 is normal, and thus the subprocessor 25-2 and its subprocessor 25-. A series of hardware self-diagnosis is completed for the peripheral device 26-2 connected to 2).

In addition, in the present invention, the master processor 25-1 is not the neighboring subprocessor 25-2 connected to its test data output terminal TDO, that is, the neighboring subprocessor 25-3. Hardware self-diagnosis may also be performed on the subprocessor 25-3 connected to the test data output terminal TDO of 2). For this purpose, the master processor 25-1 may perform the above-described subprocessor 25-2. Similar to the hardware self-diagnosis operation, the JAP's TAP controller is set to bypass mode (BYPASS), and it is also adjacent via the test data input / output terminal (TDI / TDO) of the master processor 25-1. Hardware self-diagnosis of the subprocessor 25-3 is performed through the test data input / output terminal TDI / TDO of the subprocessor 25-2, so that the adjacent subprocessor 25-2 located on the subtest path is provided. JTAG TAP control It is also set to the bypass mode (BYPASS).

Then, the hardware self-diagnosis is performed on the subprocessor 25-3 connected to the adjacent subprocessor 25-2 and the peripheral device 26-3 connected to the subprocessor 25-3 in the master processor 25-1. The operation of performing the above operation is performed in the above-described manner except for not only the test data input / output terminal (TDI / TDO) of the master processor itself but also the test data input / output terminal (TDI / TDO) of the adjacent subprocessor 25-2. It is performed in the same manner as a series of hardware self-diagnostic operations on the subprocessor 25-2 and the peripheral device 26-2 connected to the subprocessor 25-2. At this time, the test result output as the hardware self-diagnosis result of the subprocessor 25-3 and the peripheral device 26-3 connected to the subprocessor 25-3 is the test data of the subprocessor 25-3. The test result signal output to the output terminal TDO and thus output is an input / output terminal for inputting a test result of the master processor 25-1 connected to the test data output terminal TDO of the subprocessor 25-3. The master processor 25-1 inputs to the I / O6, and the master processor 25-1 diagnoses whether the hardware is defective by using the test result that is input through the input / output terminal I / O6.

Furthermore, the embodiment according to the present invention is not limited to the above-described embodiments, and various alternatives, modifications, and changes can be made within the scope apparent to those skilled in the art in connection with the present invention. Although the embodiment has been described as sequentially performing hardware self-diagnosis for the master processor and the sub-processor and its peripheral devices, it may be implemented to perform hardware self-diagnosis only for a specific processor or peripheral device if necessary.

As described above, the present invention assigns an input / output terminal implemented in a processor of an embedded system to its JTAG port to access a register and a peripheral device inside the processor, thereby making it possible to determine whether there is a hardware failure in the embedded system. Diagnosis can be performed, and the hardware self-diagnosis result can be output to the user or reported to the outside through wired / wireless communication.

In addition, the present invention enables to output and report the hardware self-diagnosis results in the embedded system, it is possible to more quickly cope with the development process of the embedded system or AS (After Service) situation, and furthermore with the service provider of the embedded system Through linkage, it can be utilized as one of service items or development of embedded system that can debug its own hardware defects.

Claims (13)

An embedded system having an ARM (Advanced RISC Machines) core including a JTAG or at least one processor and a peripheral device including a JTAG. A user interface unit for receiving and delivering a test command for requesting hardware self-diagnosis; A display unit which outputs the hardware self-diagnosis result to a user; A memory unit for storing software and information necessary for driving the embedded system and software and test reference information for performing the hardware self-diagnosis function; The software and the test reference information stored in the memory unit to control the overall operation by using the software and information necessary for driving the system, the hardware self-diagnosis software and test reference information stored in the memory unit when a test command requesting a hardware self-diagnosis is inputted Hardware self-diagnosis through the input / output terminal for test signal, test data input / output terminal and input / output terminal for test result input while controlling JTAG's TAP controller test operation mode through input / output terminal for test operation mode control And a master processor that performs a function and outputs the hardware self-diagnosis result through the display unit. The method of claim 1, The test reference information includes a JTAG identification code of each processor used when performing a hardware self-diagnosis function, specific state information for setting each processor internal module to a self-diagnostic state, and specific state information for setting a peripheral device to a self-diagnostic state. Embedded system capable of hardware self-diagnosis, characterized in that. The method of claim 1, The hardware self-diagnosis further includes a communication processor that receives a test command requesting hardware self-diagnosis and delivers the test command to the master processor, or reports the hardware self-diagnosis result to the outside through wired / wireless communication. Embedded system with hardware self-test. The method of claim 1, The master processor reads the JTAG identification code inside the processor in a state where the TAP controller of the JTAG is set to the internal test mode, diagnoses whether the JTAG is defective, and sets the internal modules of the processor to a specific state when the JTAG is normal. The register value of the internal modules of the processor is read to diagnose whether the internal modules are defective. If the internal modules of the processor are normal, the peripheral device connected to the input / output terminal of the processor is set to a specific state and then the TAP of the JTAG is executed. Set the controller to external test mode and read the pin status information of the peripheral device while connecting the test data input terminal and the test data output terminal to the boundary scan register to diagnose whether the peripheral device is defective or not. Perform hardware self-diagnosis Hardware Self-capable embedded system diagnostics that. The method of claim 1, When the at least one subprocessor and peripheral devices exist in the embedded system, the master processor controls the TAP controller test operation mode of the JTAG of each processor through the input / output terminal for controlling the test operation mode and the input / output terminal for the test signal. The test data input / output terminal and input / output terminal for inputting the test result perform a series of hardware self-diagnosis functions for diagnosing hardware defects for each processor and peripheral devices present in the embedded system. Hardware self-diagnostics, characterized in that for outputting the diagnostic results through the display unit. The method of claim 5, The subprocessor includes a TAP controller of a JTAG in which a test operation mode is controlled by a master processor. The subprocessor includes a TAP controller connected to a test mode selection and a test clock terminal of the master processor and an input / output terminal for controlling a test operation mode of the master processor. The test operation mode of the control unit is controlled, and the test data output terminal of the previous processor and its test data input terminal are connected according to the processor connection order to provide a predetermined sub test path, and the test data output terminal of the master processor An embedded system capable of hardware self-diagnosis, which is connected to the input / output terminals and passes a series of test result signals to the master processor. The method of claim 5, The master processor sets the TAP controller of the JTAG of the other processors (including the master processor) except the sub-processor to be self-diagnostic to the bypass mode to directly connect the test data input terminal and the test data output terminal serving as the sub test path. A subprocessor and a peripheral device connected to the subprocessor through the input / output terminal for its own test signal, the test data input / output terminal directly connected to the above, and the test data input terminal of the subprocessor to be self-diagnosed. An embedded system capable of hardware self-diagnosis, characterized in that to perform a hardware self-diagnosis function. A hardware diagnostic method in an embedded system having an advanced RISC Machines (ARM) core including a JTAG or at least one processor and a peripheral device having a JTAG therein, Diagnosing JTAG failure by reading a JTAG identification code in a state in which the TAP controller of the JTAG is set to an internal test mode by executing hardware self-diagnosis software in the master processor when a hardware self-diagnosis request is made; If the JTAG is normal, setting a processor internal module to a specific state for self-diagnosis, and then reading a register value of the processor internal modules to diagnose whether the processor internal module is defective; When the internal module of the master processor is normal, the peripheral device connected to the input / output terminal is set to a specific state for self-diagnosis, and the pin state information of the peripheral device is read after setting the TAP controller of the JTAG to an external test mode. Diagnosing whether a corresponding peripheral device is defective; And outputting the hardware diagnosis result in the above process to the user through a display unit, or reporting the result to the outside through wired / wireless communication. The method of claim 8, The diagnosing of the JTAG failure may include setting a TAP controller of the JTAG to an internal test mode by controlling a test mode selection terminal and a test clock terminal through a test operation mode control input / output terminal in a master processor; Reading a JTAG identification code inside the processor through an input / output terminal for a test signal and a test data input terminal of the master processor, and outputting the JTAG identification code as a test result to a test data output terminal; Receiving a JTAG identification code read as the test result through an input / output terminal for inputting a test result of the master processor, and then checking whether the same as the JTAG identification code stored in the memory unit; And outputting a hardware diagnosis result of JTAG normal when the JTAG identification code and the JTAG identification code of the memory unit are the same, and outputting a hardware diagnosis result of JTAG failure if not identical. Hardware self-diagnosis method. The method of claim 8, Diagnosing whether the processor internal module is defective may include: setting the internal modules to a specific state for self-diagnosis to diagnose whether the internal module of the master processor is defective; Reading register values of the internal modules of the processor through an input / output terminal and a test data input terminal for a test signal of the master processor and outputting the register values to the test data output terminals as a test result; Register value of self-diagnosis status information about internal modules stored in the memory unit after receiving the register value of the internal modules read as the test result through the input / output terminal for inputting the test result of the master processor Checking whether it is equal to; And outputting a hardware diagnosis result of an internal module failure if the register values of the internal modules of the processor and the register values of the internal modules of the memory unit are the same, and a hardware diagnosis result of an internal module failure if not identical. Hardware self-diagnosis method in an embedded system, characterized in that. The method of claim 8, Diagnosing whether the peripheral device is defective may include setting a corresponding peripheral device to a specific state for self-diagnosis to diagnose whether the peripheral device is defective or not; By controlling the test mode selection terminal and the test clock terminal through the test operation mode control input / output terminal of the master processor, the TTAG controller of the JTAG is set to the external test mode so that the test data input terminal and the test data output terminal are bounded scan registers. Connecting to; Reading pin state information of the peripheral device through a test signal input / output terminal and a test data input terminal of the master processor and outputting the pin state information to the test data output terminal as a test result; After receiving the pin state information of the peripheral device read as the test result through the input / output terminal for inputting the test result of the master processor, and confirming the same as the self-diagnostic state information of the peripheral device stored in the memory unit. Steps; And outputting a hardware diagnostic result of a normal peripheral device if the pin state information of the peripheral device read above is the same as the peripheral device self-diagnostic status information of the memory unit, and outputting a hardware diagnostic result of a peripheral device failure if not identical. Hardware self-test method in an embedded system, characterized in that. The method of claim 8, When there is a hardware self-diagnosis request for the other subprocessors and peripheral devices present in the embedded system, the TAP controller of the JTAG of each processor located between the master processor and the sub-processor targeted for self-diagnosis is bypassed. And performing hardware self-diagnosis on the sub-processor and the peripheral device in a state in which the sub-test path is set to be implemented. The method of claim 12, The hardware self-diagnosis of the subprocessor and the peripheral device may include: a master processor itself, a test mode selection terminal of each subprocessor located on a subtest path, through an input / output terminal for controlling a test operation mode in a master processor; Controlling the test clock terminal to set the TAP controller of the JTAG to the bypass mode to directly connect the test data input terminal and the test data output terminal of each processor to implement a sub test path; In the state in which the TAP controller of the JTAG of the subprocessor is set to the internal test mode by controlling the test mode selection terminal and the test clock terminal of the subprocessor to be self-diagnosed through the input / output terminal for controlling the test operation mode in the master processor. Diagnosing whether the JTAG of the subprocessor and the internal module are defective; The master processor sets the peripheral device connected to the subprocessor to a specific state for self-diagnosis, sets the JTAG TAP controller of the subprocessor to the external test mode, and reads pin state information of the peripheral device connected to the subprocessor. Diagnosing whether a corresponding peripheral device is defective; In the embedded system, characterized in that for outputting the hardware diagnostic results for the sub-processor and the peripheral device in the step to the user via the display unit in the master processor, or to the outside via wired / wireless communication Hardware self-diagnosis method.

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