KR20070015884A - ScmiconducLor Mcmorv Dcvicc - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. For example, an error code correction scheme comprising a 64-bit data bit and a 9-bit check bit for a memory array (ARY) such as a DRAM is introduced. (ECC) is placed adjacent to the sense amplifier (SAA). In addition to a regular memory array made up of such a memory array ARY, a redundant memory array having SAA and an ECC adjacent thereto is provided in the chip to eliminate defects that occur during manufacturing. In addition, the ECC provides a technique for providing a semiconductor memory device having a wider operating margin at the time of miniaturization while suppressing area penalty by performing error correction at the time of an activation command and storing a precharge command, especially a check bit.

Description

Semiconductor Memory {ScmiconducLor Mcmorv Dcvicc}

1 is a plan view showing an example of a chip configuration in a semiconductor memory device according to one embodiment of the present invention, where (a) is a configuration example of an entire chip; (b) shows an example of the configuration of the memory bank in (a).

FIG. 2 is a diagram showing the configuration and operation around the memory array in the semiconductor memory device of FIG. 1, (a) is a schematic diagram showing a configuration example around the memory array including an error correction code circuit; (b) is a sequence diagram explaining an operation example of (a).

FIG. 3 is a circuit diagram showing an example of the configuration of the memory array in the semiconductor memory device of FIG.

FIG. 4 is a plan view showing an example of detailed arrangement of the sense amplifier string, the sub word driver string, and the error correction code circuit in the semiconductor memory device of FIG.

FIG. 5 is a block diagram showing an example of a configuration in which the redundant area is provided in the memory bank of the semiconductor memory device of FIG.

FIG. 6 is a diagram showing details of internal circuits in the structural example of FIG. 5, (a) is a circuit structural example of a multiplexer; FIG. (b) shows an example of the circuit configuration of the fuse block.

FIG. 7 is a plotter diagram showing another example of the configuration in which the redundant area is provided in the memory bank of the semiconductor memory device of FIG. 1.

8 is a schematic diagram showing an example of a detailed connection relationship between the sense amplifier string and the error correction code circuit in the semiconductor memory device of FIG.

FIG. 9 is a circuit diagram showing an example of a detailed configuration of a sense amplifier for the data bits and an ECC subcircuit in the configuration example of FIG. 8.

FIG. 10 is a circuit diagram showing an example of a detailed configuration of a sense amplifier for the check bit and an ECC subcircuit in the example of the configuration of FIG. 8.

FIG. 1 is a circuit diagram showing an example of the configuration of the cross area in the semiconductor memory device of FIG.

FIG. 2 is a diagram for explaining an example of code used in the error correction code circuit in the semiconductor memory device of FIG. 1, (a) is an explanatory diagram of a test matrix; (b) is explanatory drawing of each element in the inspection matrix of (a).

3 is a diagram illustrating an example of a layout of the memory array in the semiconductor memory device of FIG. 1.

4 is a diagram illustrating an example of a cross-sectional configuration between A-A 'in the layout of FIG. 3.

FIG. 5 is a diagram illustrating an example of a layout of a memory array different from that of FIG. 3 in the semiconductor memory device of FIG. 1.

FIG. 6 is a circuit diagram showing an example of the configuration of the subword driver string in the semiconductor memory device of FIG.

FIG. 7 is a block diagram showing another example of the configuration in which the redundant area is provided in the memory bank of the semiconductor memory device of FIG.

FIG. 8 is a circuit diagram showing an example of the configuration of the multiplexer in the configuration example of FIG. 7.

FIG. 9 is a diagram showing an example of the operation in the structural example of FIG. 8, and (a) is a waveform example in the case of not performing redundant replacement; FIG. (b) is an example of waveforms in the case of performing redundant substitution.

20 is a schematic diagram illustrating a modification of the arrangement of the error correction code circuit in the example of the configuration of FIG. 4.

Fig. 21 is a schematic diagram showing an example of the configuration of a semiconductor memory device of the prior art examined as a premise of the present invention.

* Description of reference numerals indicating major parts **

CHIP memory chip

BANK memory bank

DQ3 input / output circuit

DQ I / O Buffer

CNTL control circuit

ARY memory array

MAA Main Amplifier Row

MA main amplifier

XDEC Row Decoder

YDEC thermal decoder

ACC array control circuit

XP cross area

SWDA Subword Driver String

SWD Subword Driver

SAA Sense Amplifier Row

SA sense amplifier

ECC; ECC_A; ECC_B; ECC_C; ECC_D Error Correction Code Circuit

MC memory cell

SN accumulation node

Cs capacitor

BL BLT BLB Bit Line

WL wordline

MWLB Main Word Line

GIO Regular Global I / O Lines

RGIO redundant global I / O line

RN redundant selection signal

RD redundant decode signal

MS matte selection signal

CK clock signal

MUX, MUXB Multiplexer

FB fuse block

XPD Row Address Free Decoder

YPD open dress free decoder

DC decoder

ECE ECC Drive Circuit

For ECS data bits

ECC sub circuit

For CKS check bits

ECC sub circuit

EXOR exclusive OR circuit

C0MP comparison circuit

INV inversion circuit

FX Subword Driver Selection Line

P, PT, PB syndrome preliminary signal

S syndrome

TGC Transfer Gate

IOP read and write port

YS heat selector

CC cross couple amplifier

PCC precharge circuit

SHR sense amplifier isolation signal

LIO, LIOT, LIOB Local IO Lines

MIO, MIOT, MIOB main IO cable

RMIO redundant main IO cable

CSP P side common source line

CSN N-side Common Source Line

BLEQ bit line precharge signal

SHD SHR Signal Driver

REQ LIO Line Precharge Circuit

RGC lead light gate

CSD CS Line Driver

SEQ CS line precharge circuit

EQD BLEQ Signal Driver

FXD FX Line Driver

PXD PX Line Driver

PSA, SSA Sense Circuit

CWC check bit write circuit

BCNT Burst Counter

ACT active area

BC Bitline Contact

SC accumulating node contacts

CI Capacitor Insulation CI

CB contacts

N N-type diffusion layer region

PW Semiconductor Substrate

Si0₂ insulating film

IS0 device isolation gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly, to semiconductor memories such as dynamic random access memories (DRAMs) equipped with error correction code circuits.

According to the inventors' consideration, the followings can be considered as to the DRAM reliability improvement technology.

For example, the patent document shows a memory circuit as shown in FIG. The memory circuit shown in FIG. 21 is configured to determine and correct data from memory cells of an SRAM or a DRAM by an error correction code circuit (ECC circuit). With this configuration, even if an error occurs in the 4-bit data bit, it can be corrected using the 3-bit check bit.

In addition, in Fig. 21, a plurality of ECC circuits are provided for the memory array, and data from the non-adjacent bit lines are connected to each of the ECC circuits so as to perform error correction. For this reason, error correction is possible even when a so-called multi-bit soft error occurs in a plurality of consecutive bit lines. Redundant memory cells are provided to eliminate stuck failures, and data from a regular memory cell and data from a redundant memory cell can be replaced while connecting from an sense amplifier circuit to an ECC circuit. It is supposed to be done.

[Patent Document] Japanese Unexamined Patent Publication No. 2003-77294

However, as a result of the present inventor's examination of the above described technology for improving reliability of DRAM, the following cases became clear.

To miniaturize and high-density memory cells in DRAMs, capacitors and fine transistors that realize large capacities within a limited memory cell area are required. However, miniaturization of memory cell transistors increases device gaps, affects lower voltages, and degrades DRAM operating margins.

Particularly problematic are the mismatch of the threshold of the M0S transistors constituting the sense amplifier and the reduction of the voltage of the accumulation node due to the junction leak current. As the scaling progresses, the fluctuation of the number of impurity in the channel of the fine M0S transistor increases with respect to the threshold mismatch. The junction leakage current also tends to increase because the electric field in the diffusion layer becomes stronger for miniaturization. The device gap effectively reduces the amount of signal when reading data from a memory cell and increases the risk of being read backwards when amplifying the signal with a sense amplifier.

Therefore, in order to improve the operating margin of such DRAM, it is conceivable to use the technique of the patent document as described above, for example. However, in the technique described in the patent document, since three bits are provided for four bits of data, the area of the memory cell is increased by 75% compared to the case where no error correction by the ECC circuit is used. DRAM chips are difficult to be applied to products such as cost-oriented servers, personal computers (PCs), and home appliances. In that regard, the area penalty of memory cells is reduced to 0% by using ECC method to install about 8 bits of check bits for 64 bits of data, so that the chip area and cost are increased. It is desirable to suppress.

In order to operate the (ECC) circuit in such a large number of bits, it is necessary to bring a large number of bits from the sense amplifier circuit to the ECC circuit. If so, the power consumption or wiring delay occurring in this wiring cannot be ignored. Therefore, in order to reduce power consumption or wiring delay, it is preferable to arrange the ECC circuit adjacent to the sense amplifier circuit.

By the way, in the technique of the patent document, it is expected that the ECC circuit will be difficult to arrange adjacent to the sense amplifier circuit. As one of the factors, the technique of the patent document uses an ECC method having three bits of data bits and four bits of data bits, thereby increasing the area of the ECC circuit. Therefore, if such a configuration is applied to DRAM and the ECC circuit and the sense amplifier circuit are arranged adjacently, it is not preferable because the area of the so-called direct peripheral circuit becomes large and the chip area is greatly increased.

As another factor, in the technique of the patent document, as shown in Fig. 21, the ECC circuit is provided for the normal memory cell (normal mernory ceI1), but the ECC circuit is not provided for the redundant memory cell. Then, when replacing the data of the normal memory cell with the data of the redundant memory cell, it is necessary to arrange a multiplexer or the like in the path from the sense amplifier circuit to the ECC circuit to convert the path.

Therefore, it is conceivable to arrange the multiplexer arrangement area between the sense amplifier circuit and the ECC circuit in the layout. In this case, the sense amplifier circuit and the ECC circuit are not arranged adjacently. In the DRAM, since many sense amplifier circuits are distributed in a chip, such a multiplexer greatly increases the area of the direct peripheral circuit including the wiring area. This also makes it difficult to arrange adjacent sense amplifier circuits and ECC circuits. Another problem is that the delay time caused by the multiplexer and its wiring causes a decrease in the operating speed.

This invention is made | formed in view of such a problem. The above and other objects and novel features of the present invention will be apparent from the description and the accompanying drawings.

Representative but briefly outlined among the inventions disclosed in the pursuit as follows.

A semiconductor memory device according to the present invention includes a plurality of memory arrays each including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, and a sense amplifier array disposed corresponding to each memory array. In one configuration, an error correction code circuit is disposed adjacent to this sense amplifier column. The error correction code circuit performs error correction on the data read by each sense amplifier in the sense amplifier string. Such a configuration is suitable for a method of performing error correction when an activation command is input. Further, since the sense amplifier string and the error correction code circuit are disposed adjacent to each other, power consumption due to charging and discharging of the wiring in the past can be reduced. In addition, the penalty of the operation speed accompanying the wiring delay time can be reduced. In addition, since the integration is possible by the adjacent arrangement, the area penalty can be reduced.

By the way, it is conceivable that the error correction is performed in response to the column-based command in addition to the method of error correction in the period of such an activation command (row command activate command: row command). As such a column-based command method, for example, an error correction code circuit can be arranged in a so-called indirect peripheral circuit or the like, so that the area penalty can be reduced as compared with the row-based command method. However, since the low-based command method can normally be several tens of ns periods, the penalty for operating cycles across the chip is very large. Therefore, the operation cycle penalty and the area penalty can be efficiently reduced by arranging the sense amplifier string and the error correction code circuit adjacent to each other using the row-based command method.

In the semiconductor memory device of the present invention, redundant memory arrays are included in the plurality of memory arrays described above. The redundant memory array also has an error correction code circuit adjacent to the sense amplifier string. As a result, the chip yield can be improved and the reliability can be improved from both sides of the fault relief (failurcrcplaccmcnt) using the error correction code circuit and the fault relief by the redundancy relief. In addition, a path conversion circuit between the sense amplifier and the error correction code circuit, which is necessary for sharing a dedicated error correction code circuit with the redundant memory array, becomes unnecessary. This makes it easy to arrange the error correction code circuit adjacent to the sense amplifier string.

When redundant redundancy is performed between redundant memory arrays and regular memory arrays, the redundant memory arrays have dedicated error correction code circuits. Substitution in this memory array unit may be performed in the same manner as in the case of selecting whether the I / O line connected to the regular memory array or the I / 0 line connected to the redundant memory array is selected by the multiplexer. .

In addition, the above-described error correction code circuit can be specifically configured by a plurality of sub-circuits arranged adjacent to each sense amplifier circuit in a one-to-one correspondence, for example. Such a plurality of sub circuits may be classified into, for example, a plurality of first sub circuits and a plurality of second sub circuits. Here, each of the first sub-circuits has a function of responding to each sense amplifier of data bits, generating a check bit based on the read data of the sense amplifier, and correcting the read data of the sense amplifier in case of an error. Each of the second sub-circuits corresponds to each sense amplifier of the check bits and compares and determines the value of the check bit generated by the first sub-circuit with the check bit value previously generated and stored, and the result of the presence or absence of an error obtained therefrom. It is provided with a function of transmitting to the first sub-circuit. With such a circuit configuration, the sense amplifier string and the error correction code circuit can be adjacent to each other in an efficient layout.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing. In addition, in the whole figure for demonstrating embodiment, the same code | symbol is attached | subjected to the same member as a principle, and the repeated description is abbreviate | omitted. In the figure, the PMOS transistor is given a well-known symbol to the gate to distinguish it from the NMOS transistor. In the drawing, the connection of the substrate potential of the MOS transistor is not specified. However, the connection method is not particularly limited as long as the MOS transistor is in a normal operable range.

1 is a plan view showing an example of a chip configuration in a semiconductor memory device according to one embodiment of the present invention, (a) is an example of the entire chip configuration, and (b) is a memory bank in (a). A structural example is shown.

The semiconductor memory device shown in FIG. 1 is a DRAM. The configuration of the entire memory chip CHIP can be broadly divided into, for example, the control circuit CNTL and the input / output circuit DQ3 memory bank BANK. The clock, address, and control signal are inputted from the outside of the memory chip CHIP to the control circuit CNTL, and the operation mode of the memory chip CHIP is determined, the predecoding of the address, and the like are performed. The input / output circuit DQ3 includes an input / output buffer and the like, and write data is input from the outside of the memory chip CHIP to output read data to the outside of the memory chip CHIP.

In the memory bank BANK, for example, memory arrays ARY arranged in a plurality of array states are arranged as shown in Fig. 1 (b); Sub word driver sequence (SWDA); Error correction code circuit ECC; cross area XP is arranged. In addition, the column decoder (YDEC) and the main amplifier column (MAA) are arranged on the outer periphery of the memory bank (BANK) in parallel with the sense amplifier string (SAA), and the row decoder (XDEC) and array in parallel with the sub word driver string (SWDA). An arrav control circuit (ACC) is disposed.

FIG. 2 shows the configuration and operation around the memory array in the semiconductor memory device of FIG. 1, (a) is a schematic diagram showing a configuration example around the memory array including an error correction code circuit, and (b) is (a). Is a sequence diagram illustrating an example of the operation. The semiconductor memory device shown in Fig. 2A is provided with an error correcting code circuit ECC in a corresponding relationship to the sense amplifier column SAA adjacent to the memory array ARY. The ECC is a circuit having a bit error correction capability.

In addition, a sense amplifier (SAA) is generally referred to as a direct peripheral circuit, so that an error correction code circuit (ECC) installed corresponding thereto is also a direct peripheral circuit. The circuits of the address system such as XDEC and YDEC shown in FIG. 1, the circuit of the data system belonging to the external terminal side of the chip rather than the MAA, are generally called indirect peripheral circuits.

The memory array ARY is divided into DATA BIT and CHECK BIT. For example, one ECC block is formed by 64-bit data bits and 9-bit check bits. . Then, the entire array (ECC) block is read into the sense amplifier string SAA by the conference array operation, and error determination and correction are performed by the error correction code circuit ECC. By performing error correction by ECC, it is possible to widen the chip operating margin even when the memory cell is made smaller and the device gap increases. In addition, since only 9 bits are provided for a large number of bits, such as 64 bits, area penalties such as memory cells can be reduced.

Next, an example of the operation of such a semiconductor memory device will be described with reference to Fig. 2B. In Fig. 2B, the operation inside the chip after the activate command, after the read / write command, and after the precharge command is shown. The characteristic here is to operate the error correcting code circuit (ECC) after an activation command and after a precharge command.

As a flow of external commands, first activate the bank with the activate command, exchange data with the bank with the read / write commands, and then deactivate the bank with the precharge command. As a result of this flow, the chip receives an activation command to activate a word line and read a signal to the bit line. Then, the read signal is amplified by a sense amplifier, and the data in the sense amplifier is subjected to error determination and error correction by ECC. Here, when the read / write command is input, the column select line is activated to read out error corrected data from the sense amplifier and write new data into the sense amplifier. When a precharge command is inputted, a check bit is made by ECC, the generated check bit is written to the memory cell for the check bit, and the word line is deactivated to pre-jaggie the bit line.

Thus, in the structure and operation of FIG. 2, ECC is installed in the sense amplifier and error correction is performed when an activation command is input. Since the cycle of the activation operation is about 60 ns, the delay of several ns caused by the error correction code circuit (ECC) can reduce the penalty of the operation cycle. Therefore, there is an advantage that a timing specification (specification) almost equivalent to a DRAM having no error correction code circuit can be realized. On the other hand, when the ECC is placed in an indirect peripheral circuit as in the prior art and the error correction is specifically performed, a penalty of several ns is added to the operation cycle of about 5 ns. There is a problem that is large.

FIG. 3 is a circuit diagram showing an example of the configuration of the memory array in the semiconductor memory device of FIG. As shown in FIG. 3, the memory array ARY is composed of a plurality of memory cells MC. Each memory cell MC is a DRAM memory cell and is composed of three MOS transistors (memory cell transistors) and three capacitors Cs. One source or drain of the memory cell transistor is connected to the bit line BLT or bit line BLB, the other source or drain is connected to the storage node SN and the gate is connected to the word line WL. You are connected.

One terminal of the capacitor Cs is connected to the accumulation node SN and the other terminal is connected to the common plate PL. The bit line BLT and the bit line BLB function as bit line pairs (complementary bit lines) and are connected to the same sense amplifier SA. The sense amplifier string SAA and the error correction code circuit ECC are alternately arranged up and down with respect to the memory array ARY, and are connected in common to the bit line pairs BLT / BLB in the upper and lower memory arrays ARY, and shared with each other. do. In addition, in the sense amplifier string SAA, adjacent sense amplifiers SA are arranged so as to sandwich a space for one bit line pair.

By adopting such an arrangement, the pitch between SAs is alleviated, so that the layout of the SAs is easy and can be made finer. Although details will be described later in FIG. 8 and the like, the pitch between ECC subcircuits can be similarly reduced when the ECC subcircuits are arranged in a one-to-one correspondence to each SA. In addition, since the ECC is disposed adjacent to the SA, the wirings connecting the two are short and the charge-discharge power consumption of the wirings is small. If one of the indirect peripheral circuits (ECC) is placed and the ECC method is used to install check bits for many of these bits, it is necessary to install a large number of long distance wires on the chip and consume power. Grows

FIG. 4 is a plan view showing an example of detailed arrangement of the sense amplifier string, the sub word driver string, and the error correction code circuit in the semiconductor memory device of FIG. As shown in FIG. 4, the sense amplifier SA and the error correction code circuit ECC in the sense amplifier string SAA are alternately arranged up and down with respect to the memory array ARY, and thus, bit line pairs in the upper and lower memory arrays ARY. It is commonly connected to (BLT / BLB).

Similarly, the sub word driver SWD in the sub word driver string SWDA is also alternately placed on the left and right with respect to the memory array ARY and is commonly connected to the word line WL in the left and right memory array ARY. . By arranging in this way, the pitch between the sub word drivers SWD in the sub word driver string SWDA can be increased to twice the pitch between the word lines WL in the memory array ARY. Therefore, miniaturization becomes easy.

In addition, a local I / O line LIO is arranged in the sense amplifier string (SAA), and the LIO is connected to the main I / 0 line (MIO) via a switch (SW) through the cross area (XP). At the time of reading, data in the sense amplifier (SA) corrected using ECC is read out of the chip through the LIO and MIO, and at the time of writing, data is written to the sense amplifier (SA) through the MIO and IO from outside the chip.

FIG. 5 is a block diagram showing an example of a configuration in which the redundant area is provided in the memory bank of the semiconductor memory device of FIG. Usually, dozens of memory mats MAT are included in the memory bank BANK. However, in FIG. 5, two cases of the memory mats MAT0 and MAT1 are shown for simplicity of explanation. The regular memory arrays ARY0 to 7 and redundant memory arrays RARY0 and 1 each have a sense amplifier sequence SAA and an error correction code circuit ECC corresponding to each other. For the sake of simplicity, however, the sense amplifier array SAA as shown in FIG. 4 is not configured to be shared connected to the memory array ARY. 5, ARY0 to 3 and RARY0 belong to the memory mat MAT0, and ARY4 to 7 and RARY1 belong to the memory mat MAT1.

With such a configuration, for example, when there is a manufacturing defect in the memory array ARY in a memory mat MAT that cannot be repaired by ECC, the entire redundant ARY is a redundant memory array in the same MAT. It is possible to rescue by replacing with (RARY). The redundant memory array RARY is installed independently of the regular memory array ARY, and an independent error correction code circuit (ECC) is also provided in the sense amplifier string (SAA) of RARY. The multiplexer between the sense amplifier and the ECC is no longer needed, and the circuit area and wiring area can be reduced.

Here, each error correction code circuit (ECC) in FIG. 5 can be corrected when a defect exists in 64 bits, for example, but error correction cannot be performed when a defect exists in a plurality of bits. In the error correction method according to the present embodiment, the ECC and SAA correspond to one-to-one, and each SA in the SAA has a slightly different wiring pattern of the corresponding ECC portion. It is not easy to replace a sense amplifier unit in which a normal sense amplifier is replaced with a redundant sense amplifier. If error correction is not possible by ECC, redundancy can be enabled while applying error correction by performing replacement in units of memory array for error correction. By preparing a redundancy memory array and repairing it, it is possible to eliminate defects that occur during manufacturing and to increase the ratio of chips.

In this way, redundancy relief is performed in units of memory arrays corresponding to ECC. In the configuration example of FIG. 5, the multiplexer MUX of the input / output buffer DQ is arranged and connected to the regular memory array ARY for this MUX. The / O line and the I / O line connected to the redundant memory array (RARY) are connected. When the DRAM receives an activation command, a word line in one memory mat (e.g., MAT0) is selected to move data from all the memory arrays (e.g., ARY0-3 and RARY0) in that memory mat to the sense amplifier array (SAA). Is read. In a normal memory array (eg, ARY0 to 3), data read out by SAA is selected by the column select line YS output from the column decoder YDEC and read out by the main I / O lines MIO 0 through 3. The same is read from the redundant memory array (eg RMIO) to the data redundant main I / O line (RMIO).

Data read by MIO 0 ~ 3, RMIO is amplified by main amplifier (MA) and output to rectified global I / O line (GIO 0 ~ 3), redundant global I / O line (RGIO). In this case, for example, when there are no fixed defects in ARY0 to 3 and no redundancy relief is performed, the data on GIO 0 to 3 passes through the multiplexer (MUX) and is output directly to the outside of the chip by the input / output buffers DQ0 to 3. On the other hand, when redundancy relief is performed, one of the redundancy select lines RN0 to 3 is activated, and either of GIO 0 to 3 and the data of RGIO are replaced by MUX. For this reason, the number of the memory array ARY to be repaired for each memory mat MAT is programmed in the fuse block FB in advance.

When the activate command is input to the DRAM, the mat selection signals MS0 to 31 corresponding to, for example, the memory mats MAT0 to 31 are input to the FB from the row address predecoder XPD. The memory array to be saved in the memory mat corresponding to the input selection signal is determined by the fuse information of the FB, and the redundant selection signal RN corresponding to the memory array is activated. As a result, for example, it is possible to save ARY 0 to RARY 0 in MAT0 0 and to save ARY 6 to ARY 1 in MAT1. In addition, although the case where a solution exchange is performed with the read from a memory array was demonstrated, the case of writing to a memory array is the same and redundantly substituted.

FIG. 6 is a circuit showing the details of the internal circuit in the configuration example of FIG. 5, (a) is a circuit configuration example of a multiplexer, and (b) is a circuit configuration example of a fuse block. As shown in Fig. 6A, the multiplexer MUX is formed of a pass transistor and is provided corresponding to the input / output buffer DQ. The redundant global I / O line (eg RGIO) is connected to the input / output buffer (DQ) when the redundant select signal (eg RN0) output from the fuse block (FB) is active. The / O line (e.g. GIO 0) is connected to the DQ.

As shown in Fig. 6B, the fuse block FB is provided with a fuse corresponding to each memory array ARY for each memory mat MAT. That is, when the fuse FUSE corresponding to the memory array ARY which performs relief in each memory mat MAT is cut off and the mat selection signal MS is activated, the relief in the corresponding MAT is performed. A redundancy selection sign (RN) corresponding to ARY is activated. 6 (b) shows an example in which RN0 is activated when MS0 is activated and RN2 is activated when MS30 is activated.

FIG. 7 is a block diagram showing another example of the configuration in which the redundant area is provided in the memory bank of the semiconductor memory device of FIG. A difference from the configuration example of FIG. 5 is a method of connecting the regular global I / O line (GIO) and the multiplexer (MUX). In FIG. 5 described above, a regular global I / O line GIO and a redundant global I / O line RGIO are connected to a multiplexer MUX corresponding to each DQ. In the configuration example of FIG. 7, two adjacent GIOs, such as GIO0 and GIO1, are connected to the multiplexer MUX of DQ0, and thus, GIO3 and RGIO are connected to the last DQ3.

In such a configuration, for example, if ARY1 is defective in MAT0, the redundancy selection signal RN1 is decoded by the decoder DC, and the redundancy decode signal RD0 is deactivated to activate (RD1 to 3). As RD0 is deactivated, GIO0 is connected to DQ0 and GIO2 and DQ1, GIO3 and DQ2, and RGIO and DQ3 are connected, respectively, as RD1 to 3 are activated. Therefore, the redundancy can be saved while applying error correction by replacing memory units for error correction, and the operation speed is increased because the length of redundant global I / O line (RGIO) is shortened. There is this.

8 is a schematic diagram showing an example of a detailed connection relationship between the sense amplifier string and the error correction code circuit in the semiconductor memory device of FIG. The sense amplifier string SAA includes a sense amplifier SA to which a signal from a data bit is input and a sense amplifier SA to which a signal from a check bit is input. The error correction code circuit ECC is an ECC subcircuit ECS for data bits corresponding to a sense amplifier SA for data bits and an ECC subcircuit for check bits corresponding to a sense amplifier SA for check bits. (CKS). SA and ECS operate in a one-to-one correspondence and are shared by bit line pairs BLTU / BLBU and BLTD / BLBD disposed above and below. In addition, in FIG. 8, 64 pairs of bit line pairs ((BLT / BLB0 to 63) and 64 SA and ECS are provided corresponding to data bit signals, and 9 pairs of bit line pairs ((BLT / BLB64) are provided in correspondence with the signal of the check bit. 72) and nine SA and CKS are installed.

In addition, an ECC drive circuit (ECC enable circuit, ECE) is disposed in the cross area XP. In the ECE, nine syndrome preparation signals (P <0: 8> (hereafter, nine signals from P <8> to P <8> are collectively represented as P <0: 8>) are represented. The details of the ECE will be described later with reference to Fig. 11. This signal is propagated while calculating in the ECC from left to right and input into the CKS at the right end, and the calculation result in this CKS is syndrome (S) <. O: 8> One syndrome (S) <0: 8>, on the contrary, is used to specify a sense amplifier (SA) that propagates from right to left to perform error correction.

A detailed configuration example of a plurality of ECSs or a plurality of CKSs will be described below, but the same circuit configuration and circuit layout can be used, respectively, so that wiring with the syndrome preliminary signals P <0: 8> and syndromes (S) <0: 8> The layout is slightly different for each ECS or each CKS. Therefore, the layout can be easily or efficiently carried out corresponding to each sense amplifier, and the circuit area can be reduced.

FIG. 9 is a circuit diagram showing an example of a detailed configuration of a sense amplifier for the data bits and an ECC subcircuit in the configuration example of FIG. 8. Each sense amplifier SA includes a transfer gate (TGC), a precharge circuit (PCC), a cross-coupled amplifier (CC), and a read / write port (IOP). The transfer gate TGC is a circuit for connecting the sense amplifier SA and the memory array ARY in which the sense amplifier separation signal SHR signal is activated. The precharge circuit PCC equalizes between paired bit lines BLT and BLB when the bit line precharge signal BLEQ signal is activated, and precharges the bit line pre-judge level VBLR. The bit line precharge level VBLR is usually set to the midpoint VDL / 2 of the voltage VDL of the bit line amplitude (the same level as the power supply voltage VCC from the outside of the chip or the level at which the voltage is reduced).

The cross-coupler amplifier CC supplies the P-side common source line CSP to the voltage VDL and the N-side common source line after a minute read signal is generated from the memory cells MC on the bit lines BLT and BLB. A circuit for driving (CSN) to ground voltage (VSS) to amplify the higher voltage between BLT and BLB to VDL and the lower voltage to VSS and latch the amplified voltage. The read / write port I0P is a circuit for connecting the local I0 line (LIO line) LIOT / LIOB and the bit line pair BLT / BLB when the column select line YS is activated. The LIO line LIOT / LIOB is also held at precharge level during standby to prevent current consumption in the unselected sense amplifier array (SAA).

An ECC sub-circuit (ECC) for data bits includes a transfer gate (TGC), an exclusive-or circuit (EXOR), a comparator (COM), and an inverter (INV). Exclusive-OR circuits (EXOR) are in a pass transistor configuration and are used to generate checkbits and thereby generate syndromes to detect faulty sense amplifiers. EXOR performs an exclusive logical operation on the data in each sense amplifier (SA) (i.e., BLT / BLB) and the syndrome preliminary signal (i.e., PTI / P) from the left side, and the result (i.e., PTO / PBO) Is passed to ECS.

As described above, in the error correction method of the present embodiment, for example, a bit error correction is performed by adding a 9 bit check bit to a 64 bit data bit. Although the parity-check matrix used at this time is shown in FIG. 2 (detailed later), only 3 bits of the value of each column element can be set to 1, and the other can be set to 0. FIG. Therefore, three ECORs are arranged in each ECS, and three of nine syndrome preliminary signals P <0: 8> are connected to the inputs of the three EXORs. For example, for the nine wiring lines arranged in the wiring layer in the metal wiring layer, three of them may be dropped to the lower layer by using a contact and connected to the EXOR formed on the substrate.

The three numbers to be connected are the row numbers in which one of the columns corresponding to the sense amplifiers exists in the inspection column of FIG. As an example, in the second sense amplifier from the left, P <0>, P <2>, and P <4> of the syndrome preliminary signal are connected to the EXOR. In this case, in the example of FIG. 9, P <0> is connected to PTI0 (inverted signal of P <0> is PBI0), P <2> is connected to PTII (inverted signal of P <2> is PBI1), and P < 4> is connected to PTI2 (the inverted signal of P <4> is PBI2).

The comparison circuit (COMP) consists of a three-input NAND circuit and an inverter. If the value of syndrome S <0: 8> matches the value of some of the column elements in the test matrix (this is called the sense amplifier (ID)), then the sense amplifier corresponding to this matched sense amplifier (ID) is an error. It becomes. Therefore, the syndrome of the row number where 1 exists among the columns corresponding to the sense amplifier of the inspection column is input to the 3-input NAND. For example, in the case of the second sense amplifier from the left side described above, in FIG. 9, S <0> is connected to S0, S <2> is connected to Sl, and S <4> is connected to S2. When the syndrome (S) <0: 8> and the sense amplifier ID coincide with an error occurrence, the output of the three-input NAND becomes zero, and the RH inversion signal (RV) is activated. Therefore, such a circuit can confirm whether an error exists in the sense amplifier SA corresponding to the said circuit.

The inverting circuit (INV) consists of four NMOSs and starts with a pass transistor. In the initial state, the forward direction signal FW is activated, and a sense operation is performed in this state to latch data to the cross-coupled amplifier CC. Then, if an error is found in the data, the inverted signal (RV) is activated by matching the syndrome and sense amplifier (ID). As a result, since the connection relationship between the CC and the bit lines BLT / BLB is reversed in the opposite direction, the data of (BLT / BLB) can be reversed by the driving force of the CC.

FIG. 10 is a circuit diagram showing an example of a detailed configuration of a sense amplifier for the check bit and an ECC subcircuit in the example of the configuration of FIG. 8. Since the sense amplifier SA for the check bits is the same as the sense amplifier for the data bits described above, description thereof is omitted.

The ECC subcircuits (CKS) for check bits include transfer gates (TGC), exclusive OR circuits (EXOR), syndrome preliminary signal sense circuits (PSA), check bit write circuits (CWC), and syndrome sense circuits (SSA). have.

The syndrome preliminary signal sense circuit PSA is composed of a cross-coupled inverter type sense amplifier SE1 and a precharge circuit PCC. In standby, the syndrome preliminary signals PT and PB are precharged together to the ground voltage VSS. After the activation command is input and the signal is read out to the sense amplifier SA, the syndrome is calculated. As mentioned above, since the syndrome preliminary signal passes through a plurality of exclusive OR circuits of the pass transistor type, the amplitude of the CKS input terminal becomes very small. Therefore, the PSA is started as an amplifier circuit to amplify this minute signal to full amplitude.

During activation, the check bit write circuit CWC is inactive (CWE is at the 'L' level). At this time, an exclusive OR operation by EXOR is performed on the data on the syndrome preliminary signal PT / PB amplified by the PSA and the bit line pairs (BLT / BLB) read out from the check bits, and the operation effect is output as the syndrome S. If an error occurs in one of the sense amplifiers SA for the data bits, the syndrome S is activated. The state is latched by amplifying the syndrome S output in the syndrome sense circuit SSA and deactivating LT.

On the other hand, when the precharge command is received, amplify the syndrome preliminary signal (PT / PB) that has passed the exclusive logic operation on the data bit to the PSA, and then activate the check bit write circuit (CWC) (CWE to the 'H' level). do. The amplified PT hole / PB is written as a check bit into the sense amplifier SA and the memory cell for the check bit.

As described above, in the configuration example of FIG. 10, two sense amplifiers are provided in the CKS, and a pass gate is provided therebetween so that both can be separated. Therefore, the syndrome S calculated at the time of activation can be retained as the sense amplifier SE2 in the subsequent SSA. This makes it possible to hold the value of FW or RV until precharging becomes possible in FIG. 9, so that, for example, when there is an error correction (inverted write by RV), it can be surely performed. In addition, even when a write command occurs from the activation to the precharge, correct data can be written to the memory cell of the data bit.

In addition, by separating the SSA and PSA by LT, for example, when a write command occurs, the error correction information (syndrome) accompanying the activation is retained by the SSA, and the check bit generated with the subsequent write command is displayed. It is possible to hold the value (syndrome preliminary signal) with the PSA. The value held by the PSA is written to the memory cell of the check bit at the precharge time.

In addition, although the bit error occurs in the check bit, the check bit does not need to read out the data and does not need to be corrected. At this time, since the data bits do not coincide with each other, there is no problem and there is no problem. Before the precharge command is input and the word line is deactivated, the check bit is recalculated for the first time and a new data bit that can be rewritten at the time of writing is written into the memory cell.

In addition, in the data bits of N = 64 bits, the number of check bits added to detect a bit error may be 7 bits. If the number of check bits is M = 8 bits of log2 (N) + 2 or more, error detection of two bits is possible. However, in the present invention, in order to simplify the circuit configuration, only one bit error is detected and the circuit is simplified while the number of check bits is 9 bits or more of log2 (N) +2. This makes it possible to reduce the area and operation delay of the ECC circuit.

FIG. 11 is a circuit diagram illustrating an example of a configuration of a cross area in the semiconductor memory device of FIG. 1. Cross area (XP) includes SHR signal driver (SHD), LIO line precharge circuit (REQ), lead write gate (RGC), CS line driver (CSD), CS line precharge circuit (SEQ) and BLEQ signal driver (EQD). ), An FX line driver (FXD), and an ECC driver circuit (ECE) are disposed.

The HR signal driver XSHD receives a complementary signal SHRB of the SHR signal and outputs the inverted signal thereof. The LIO line precharge circuit REQ precharges the LIO line LIOT / B to the voltage VPC when the read write enable signal RWE is inactive. The lead light gate RRG is a LIO line LIOT / B when the lead write enable signal RWE is at an active voltage VCL (used as the external VCC level or used as a power supply voltage for the peripheral circuit at a level reduced by it). And main IO line MIOT / B.

The CS line driver (CSD) drives the N side common source line (NM0S, common source line, CSN) to the ground voltage (VSS) when the N side sense amplifier enable signal (SAN) is active. When the enable signal SAP1B is in an active state (VSS level), the P-side common source line (PM0S) is a circuit for driving the voltage (VDL, the 'H' level of the bit line).

The CS line precharge circuit (SEQ) is a circuit for precharging the P side and N side common source lines (CSP, CSN) to VDL / 2 when the BLEQ signal is activated. The BLEQ signal driver EQD receives the complementary signal BLEQB of the precharge signal BLEQ and outputs the inverted signal thereof. The FX line driver FXD receives the signal FXB and outputs its complementary signal to the sub word driver selection lines FX and FX lines.

The ECC driving circuit ECE receives the syndrome activation signal GE and nine syndrome preliminary signals PTI <0: 8> are activated by the VCL. PBI <0: 8> is in VSS state. As can be seen from the following 8, the signals PTI and PBI become initial values of the signal input to the first ECS, are propagated from left to right in the ECC, become check bits in the right-side CKS, and the syndrome (S) < 0: 8>. When the calculation of the syndrome is completed and the standby state after the precharge command is reached, the PCP is activated and precharged to the VSS together with PTI <0: 8> and PBI <0: 8>.

FIG. 12 is a diagram for explaining an example of code used as the error correction code circuit in the semiconductor memory device of FIG. 1, (a) is an explanatory diagram of an inspection matrix, and (b) is an element in the inspection matrix of (a). Is an explanatory diagram. The inspection column H shown in Fig. 12A has a configuration of 64 columns by 9 rows in which 8 partial columns of 8 columns by 9 rows are arranged, and the partial columns of 8 columns by 9 rows are shown in Fig. 12B. It becomes the value shown in (). In addition, the inspection matrix H of FIG. 12 (a) has a row direction in which each row element h0, h1, ..., h8 in this partial matrix is accompanied by an increase in the column number based on this partial matrix. In other words, it is in the form that it is circulated by 1 bit. When such a code is used, when an error occurs, three bits out of nine bits that constitute each column element of the partial matrix become '1', and the remaining six bits become '0'.

That is, when such a check matrix H is mounted on the error correction code circuit ECC, 64 columns of the check matrix H correspond to 64 sense amplifiers, respectively, and each row element (h0, hl ... h8) corresponds to the syndrome preliminary signals P <0: 8> and syndrome (S) <0: 8>, respectively. Here, for example, if p <2> (the third row of the inspection matrix H) is taken as an example, the sense corresponding to h2 in the ECS (0th, 1st, 5th from the left) of the left end of FIG. The amplifiers SA0, SA1, SA5 are computed with EXOR, and the result of the calculation is passed to the ESC on the right side, and the sense amplifiers SA11, SA12, SA15 corresponding to h1 in their ECS are computed with EXOR. Then, in the same manner, SA56, SA57, SA58, and SA59 corresponding to h4 are calculated as EXOR in the ECS of the right end to determine the final value of P <2>. For example, it inputs into 3rd CKS from the left side of FIG.

The operation result input to this CKS is written into the memory cell via the sense amplifier SA and the bit line pair BLT / BLB66 as check bits at the precharge command. Thereafter, the data of this memory cell is read out at the next activation command and the next P <2> data is generated in the same manner by the activation command. The read data and the generated P <2> data are calculated by EXOR in the third CKS, and the result of the calculation is syndrome (S) <2>. Thus, for example, when there is an error in the data of SA1 connected to P <2>, the value of S <2> becomes '1'. If there is an error in SA1, SA1 is connected to P <0> and S <0> and P <4> and S <4> in addition to P <2> and S <2> according to Fig. 12B. The values of S <O> and S <4> also become '1'.

Since the generated syndrome coincides with the column element of the inspection matrix corresponding to the errored sense amplifier, this column element can be regarded as a sense amplifier (ID). Therefore, the syndrome of the row number in which one of the columns corresponding to the sense amplifier of the inspection column exists is input to the three input NAND. Only when the syndrome and sense amplifier (ID) match, the output of the three-input NAND goes to zero and the inverting signal (RV) is activated. 2 (b) shows an example in which the syndromes S <0>, S <2>, and S <4> are activated and the second SA1 bit from the left is bit. At this time, the state of SA1 is corrected to the correct data by inverting the inverting circuit INV of FIG.

In addition, when comparing an input of 9 bits, a comparison circuit of 9 bits is required. However, since the error correction method of the present embodiment supports only one bit error correction, it is not necessary to determine the data pattern of all bits of the syndrome. In other words, the error correction method is based on the idea of ₉ C ₃ = 84 (≥64 bits). Therefore, in the ECS, as described above, the comparison circuit may be provided only with the three input NAND, thereby reducing the circuit area. In addition, the comparison can be performed at high speed.

In order to distinguish between 64 bits, however, a minimum 7 bit check bit is required. In this case, however, it is necessary to determine whether all of these 7 bits are 0 or 1, which complicates the comparison circuit and increases the circuit area. In the case of using 8-bit check bits, for example, ₈ C ₄ = 70 (≥64 bits), and thus the inspection matrix is determined based on this, it is possible to use a 4-input NAND comparison circuit in the ECS. In fact, it is said that the increase of the circuit area of ECS is also an allowable range. Therefore, it is preferable to provide 8 bits or more check bits for 64 bits, and more preferably 9 bits as shown in Fig. 12B. For example, when 12-bit check bits are used, ₂ C ₂ = 66 (≥64 bits), so that two input NANDs can be supported. This may be used if the area penalty of the memory cell accompanying the check bit is acceptable.

FIG. 13 is a diagram illustrating an example of a layout of the memory array in the semiconductor memory device of FIG. 1. 4 is a diagram illustrating an example of a cross-sectional configuration between A-A 'in the layout of FIG. The layout shown in FIG. 13 includes a plurality of word lines WL0 to 4 and a plurality of adjacent bit line pairs BLT / BLB, and is configured to perform complementary operations by the bit line pairs BLT / BLB. In this layout, bit line pairs (BLT / BLB) intersect with one word line and are referred to as two-point memory arrays.

In this layout, a plurality of active regions ACT are formed in parallel with the bit lines, and two word lines extend on each active region ACT. In each active region ACT, two memory cell transistors are formed which are gated on each of these two word lines. One end of the source / drain of these two memory transistors is connected to the bit line by a common bit line contact BC, and the other end is connected to each other storage node SN by different storage node contacts SC, respectively. . In addition, the width | variety of the bit line direction of each storage node SN can be made into the magnitude | size which overlaps with two adjacent word lines, for example.

Each DRAM memory cell has an N-channel MOS transistor (memory cell transistor) formed on the semiconductor substrate PW and a stack capacitor provided on the bit line BL as shown in FIG. In FIG. 14, two word lines WL are arranged on the active region ACT in the semiconductor substrate PW separated by the insulating film SiO ₂ , and the two word lines WL are used as gates of the memory cell transistors. An N-type diffusion layer region N serving as the source drain is provided in the semiconductor substrate PW.

A contact CB is disposed on the N-type diffusion layer region between these two word lines WL, and a bit line contact BC is disposed thereon. The bit line BL formed in the direction orthogonal to the direction in which the word line extends is disposed on the bit line contact BC. On the other hand, the contacts CB are arranged on the N-type diffusion layer region N outside the two word lines WL, and the accumulation node contacts SC are disposed on the upper portions thereof. The concave (cylindrical) accumulation node SN formed on the inner wall of the hole of the interlayer insulating film (not shown) is disposed above the accumulation node contact SC, and the plate electrode PL is disposed inside the accumulation node SN. Buried and they constitute a capacitor Cs with a capacitor insulating film CI interposed therebetween.

FIG. 15 is a diagram illustrating an example of a layout of a memory array different from that of FIG. 13 in the semiconductor memory device of FIG. 1. This layout is called a pseudo two-point memory array (quarter pitch memory array) and includes a plurality of word lines (WLO-4) and a plurality of bit lines, and a bit line pair (BLT / BLB) in which one bit line is sandwiched. This configuration is configured to perform the complementary operation.

In the layout of FIG. 5, unlike the FIG. 13 described above, the active region ACT is formed to be inclined with respect to the bit lines, and two accumulation node contacts SC in each active region ACT are formed to sandwich the bit lines. By using such a layout, since the shape of the accumulation node SN can be almost circular, there is an advantage that it becomes easy to secure the capacitor capacity even when miniaturization proceeds. In this pseudo-crosspoint memory array or the above-described two-crosspoint memory array, there is an advantage that noise can be reduced because the bit line where the signal is generated and the reference bit line exist in the same memory array.

FIG. 16 is a circuit diagram showing an example of the configuration of the sub word driver column in the semiconductor memory device of FIG. The sub word driver sequence SWDA is constituted by a plurality of sub word drivers SWD. As shown in Fig. 1B and the like, the sub word driver column SWDA is arranged around the memory array ARY.

The sub word driver SWD drives the word line WL in the memory array ARY disposed on both sides. As described with reference to FIG. 4, since the sub word driver strings SWDA are alternately arranged with respect to the memory array ARY, every other word line WL (sub word line) in the memory array ARY is alternated from left to right. It is connected to the sub word driver (SWD).

The sub word driver (SWD) consists of two N-channel MOS transistors and one P-channel MOS transistor. In one N-channel MOS transistor, the main word line MWLB is connected to the gate, the word line WL is connected to the RH drain, and the voltage VKK is connected to the source. In one N-channel MOS transistor, a complementary word driver select line FXB is connected to a gate, a word line WL is connected to a drain, and a voltage VKK is connected to a source. Where VKK is lower than VSS generated by the negative voltage generating circuit.

In the P-channel MOS transistor, a main word line MWLB is connected to a gate, a word line WL is connected to a drain, and a sub word driver type signal FX is connected to a source. One of the four sub word drivers (SWD), in which four sets of sub word driver select lines (FX0 to 4) are wired on one sub word driver string (SWDA), and selected as the main word line (MWLB) of the book. Select to activate one word line (WL) DL.

FIG. 17 is a block diagram showing another example of the configuration in which the redundant area is provided in the memory bank of the semiconductor memory device of FIG. The difference from the configuration example of FIG. 5 is the number of DQs and the method of connecting the global I / O line and the multiplexer. In the configuration example of FIG. 7, a plurality of regular global I / 0 lines IO0 to 3 and redundant global I / O lines RGIO are connected to the multiplexer MUXB corresponding to one input / output buffer DQ. Data from GIO0 to 3 are serially output to the DQ in accordance with the clock signal CK in order controlled by the burst counter BCNT. At this time, by controlling BCNT, data from the memory array ARY to be replaced is replaced with data from the redundant memory array RARY.

When performing a burst operation, the head addresses AS0 to 3 are input from the open-dress free decoder YPD to the burst counter BCNT. The number of memory arrays ARY to be remedied for each memory mat MAT is preprogrammed in the fuse block FB. When the activate command is input to the DRAM, the mat select lines MS0 to 31 are input to the FB from the row address predecoder XPD, and the redundant select signal RN corresponding to the memory array ARY to be remedied by the memory mat MAT is input. It is activated and sent to BCNT.

FIG. 18 is a circuit diagram showing an example of the configuration of the multiplexer in the example of the configuration of FIG. 17. In the multiplexer MUXB shown in FIG. 18, all regular global I / O lines GIO 0 to GIO 3 to which burst data are transmitted and redundant redundancy global I / O lines RGIO are connected. The connection between each global I / O line and the input / output buffer DQ is controlled by the GIO select signals B0 to B3, BR output from the bust counter BCNT. The burst head address (AS0-3) and redundancy select signal (RN0-3) are input to BCNT.

FIG. 19 shows an example of the operation in the configuration example of FIG. 18, (a) is a waveform example in the case of not performing replacement with redundant cell; FIG. (b) is a waveform example which shows the case where redundancy substitution is performed. 19 (a) shows a case where the head address is not replaced with 'O', and for example, AS0 = 'H' in the burst counter BCNT; AS1 ~ 3 = 'L'; RN0 ~ 3 = 'L' is input. In this case, the GTO selection signal is activated in the order of B0 to B3 in accordance with the clock signal CK, so that D0 to D3 corresponding to the data of GIO0 to GIO3 are output from the input / output buffer DQ to the serial.

FIG. 19B shows a case where ARY3 is replaced with RARY0 with the head address '1'. In the burst counter BCNT, for example, AS1 = 'H' · AS0, AS2, AS3 = 'L' RN0 to 2 = 'L' · RN3 = 'H'. In this case, the GIO selection signal is activated in the order of B1, B2, BR, and B0 in accordance with the clock signal CK, and when this BR is activated, the data D3 from GIO3 is replaced with the data DR from RGIO. Therefore, data is output from the input / output buffer DQ in the order of D1, D2, DR, and D0. With such a configuration and operation, it is possible to efficiently perform redundant block-based relief in the case of performing a burst operation with data from a plurality of memory arrays for a DRAM having a small number of input / output buffers (DQs) and a long burst length. Done.

20 is a schematic diagram illustrating a modification of the arrangement of the error correction code circuit in the example of the configuration of FIG. 4. In FIG. 20, only the connection relationship between the memory array ARY sense amplifier SA and the error correction code circuit ECC in FIG. 4 will be described. Increasing the error correction capability of the ECC complicates the circuit configuration of the ECC and increases the circuit area. Therefore, as described above, when ECC is mounted as a sense amplifier, it is practical to adopt an error correction method that can correct only bits. However, when a defect including a plurality of bits occurs due to a foreign material generated in manufacturing, if the plurality of bits are included in the same ECC, error correction cannot be performed.

In that respect, in the configuration example of Fig. 20, two ECC blocks are formed in each of the upper and lower sides of the sense amplifier SA alternately arranged up and down with respect to the memory array ARY. As a result, four consecutive pairs of bit lines are connected to different ECCs individually via a sense amplifier SA. In addition, the length of the long side direction of ECC_A, ECC_B, ECC_C, and ECC_D corresponding to each ECC is substantially the same as the length of the long side direction of the sense amplifier string SAA. In this way, for example, by matching four sets of ECCs to one memory array ARY, even if up to four sets of pairs of bit lines are consecutively defective, corrections can be made with ECCs, thereby increasing the ratio of chip products in manufacturing. .

As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it is a matter of course that this invention is not limited to the said embodiment and a various change is possible in the range which does not deviate from the summary.

The semiconductor memory device of the present invention is a technology particularly useful for application to DRAM products, and the present invention is not limited thereto, but may also be applied to an on-chip memory embedded in a logic chip such as a microprocessor or a digital signal processor (DSP).

When the effect obtained by the typical thing disclosed in this application is demonstrated briefly, it becomes possible to reduce the area penalty and operation cycle penalty by providing an error correction code circuit in a semiconductor memory device efficiently.

Claims (13)

A plurality of word lines; A plurality of memory arrays each including a plurality of bit lines and a plurality of memory cells; A plurality of sense amplifier strings each disposed in correspondence with the plurality of memory arrays, the plurality of sense amplifiers each including a plurality of sense amplifiers connected to the plurality of bit lines; And an error correction code circuit for correcting when a part of the data read out to the plurality of sense amplifiers adjacent to each of the plurality of sense amplifier strings has an error. In the semiconductor memory device according to claim 1, The plurality of memory arrays, A plurality of regular memory arrays, A redundant memory array used as redundant bits in redundancy relief, And the error correction code circuit is provided in the redundant memory array as in the plurality of normal memory arrays. In the semiconductor memory device according to claim 2, And said redundancy relief is performed by replacing one of said plurality of regular memory arrays and said redundant memory array by a memory array unit. In the semiconductor memory device according to claim 3, An input / output buffer that inputs and outputs data to and from the outside, A multiplexer corresponding to the input / output buffer, The semiconductor is characterized in that the multiplexer selects which of the plurality of regular memory arrays to use as the redundant memory array to select a connection object of the input / output buffer, wherein the replacement in the memory array unit accompanying the redundant relief is performed. Memory. In the semiconductor memory device according to claim 4, A plurality of the input / output buffers and a plurality of the multiplexers, A plurality of regular I / 0 lines for inputting and outputting data between the plurality of normal memory arrays; A redundant I / 0 line for inputting and outputting data between the redundant memory array, Each of the plurality of multiplexers is connected to either one of the plurality of regular I / 0 lines and the redundant I / 0 line. In the semiconductor memory device according to claim 4, A plurality of the input / output buffers and a plurality of the multiplexers, A plurality of regular I / 0 lines for inputting and outputting data between the plurality of normal memory arrays; A redundant I / 0 line for inputting and outputting data between the redundant memory arrays; Two adjacent to each other in the multiplexers are connected to either one of the plurality of regular I / O lines; Only one of the plurality of multiplexers is connected to the redundant I / 0 line. In the semiconductor memory device according to claim 4, A plurality of regular I / 0 lines for inputting and outputting data between the plurality of normal memory arrays; A redundant I / 0 line for inputting and outputting data between the redundant memory array, The plurality of regular I / 0 lines and the redundant I / 0 lines are connected to one multiplexer, And a portion of serial input / output data corresponding to the clock signal is replaced with input / output data of the redundant I / 0 line by changing the selection of a connection target in the one multiplexer according to a clock signal. In the semiconductor memory device according to claim 1, And the error correction code circuit generates eight or more check bits from the 64-bit or more data bits obtained through the sense amplifier string, and performs error correction based on the eight or more check bits. In the semiconductor memory device according to claim 1, At least four error correction code circuits correspond to each of the plurality of memory arrays, and adjacent bit lines included in each of the plurality of memory arrays are connected to different error correction code circuits. Device. In the semiconductor memory device according to claim 1, The error correction code circuit is constituted by a plurality of sense amplifiers included in the sense amplifier string and a plurality of sub-circuits corresponding one-to-one, The plurality of sub circuits are classified into a plurality of first sub circuits and a plurality of second sub circuits. The plurality of first sub-circuits initiates generation of a check bit using read data of a plurality of sense amplifiers corresponding to the plurality of first sub-circuits according to an activation command for the semiconductor memory device, and generates an error. In this case, correct the read data to the sense amplifier corresponding to the above error, The plurality of second sub-circuits determine whether there is an error by comparing and determining the check bits generated by the plurality of first sub-circuits and the previously stored check bits according to the activation command, and determining the result of the determination. In the precharge command to the plurality of first subcircuits and to precharge commands for the semiconductor memory device, a process for storing the value of the check bit generated in the plurality of first subcircuits immediately before the precharge command is performed. A semiconductor memory device, characterized in that. In a semiconductor memory device according to claim 10, The error correction code circuit, A plurality of syndrome preliminary signals for generating the check bits; A plurality of syndrome signals for specifying a sense amplifier corresponding to the error, Each of the plurality of first sub-circuits, Part of the syndrome preliminary signal and part of the syndrome signal, which are individually determined for each of the plurality of first subcircuits, and data of a bit line connected to a sense amplifier corresponding to the first sub-circuit, An EXOR circuit for performing exclusive logical summation of the value of the partial syndrome preliminary signal and the data of the bit line and reflecting the result of the operation to the value of the partial syndrome preliminary signal; A comparison circuit for generating a detection signal when the value of the partial syndrome signal is a specific value; An inverting circuit for inverting data of the bit line when a detection signal is generated in the comparison circuit; Each of the plurality of second sub-circuits, The data of the bit line connected to any one of the plurality of syndrome preliminary signals which have been calculated by the plurality of first sub-circuits and the sense amplifier corresponding thereto is input, In the determination of the presence or absence of the error, the match / dismatch between the value of the check bit read out on the bit line corresponding to the self and the value of one of the syndrome preliminary signals is compared with the activation command. A circuit for outputting one of the plurality of syndrome signals, And a circuit for outputting the value of one of the syndrome preliminary signals to the bit line corresponding to the self in storing the check bit value. In a semiconductor memory device according to claim 11, Each of the plurality of second sub-circuits, A latch circuit for holding the value of the one syndrome signal outputted along with the activation command until the precharge command is completed; And an amplifier circuit for amplifying a value of the input one syndrome preliminary signal. In the semiconductor memory device according to claim 1, The error correction code circuit generates M bits of log2 (N) +2 or more check bits from the N bits of data bits obtained through the sense amplifier string, and 1 bit in (N + M) bits based on the check bits. And a semiconductor memory device for detecting errors.

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