KR20070005777A - Circuit for compensating dc offset for wireless receivers of direct-conversion type - Google Patents

Abstract

A DC offset compensation circuit in a direct-conversion type radio receiver is provided to effectively remove a DC offset and a 1/f noise by embodying an integrated circuit having a high time constant value, without using an external resistor or an external capacitor element. A DC offset compensation circuit in a direct-conversion type radio receiver is comprised of a high pass filter(40) and a transconductance(50). The high pass filter(40) and transconductance(50) are connected to the input stage of an amplifier(A). The high pass filter(40), comprised of a resistor(R) and a capacitor(C), executes a function to interrupt the DC voltage inputted to the amplifier(A). The transconductance(50) having a positive feedback outputs current "GmVx" proportional to input voltage "Vin".

Description

Circuit for Compensating DC Offset for Wireless Receivers of Direct-Conversion type}

1 is a block diagram showing a circuit configuration of a general direct conversion type wireless receiver.

2 shows a configuration of a DC offset compensation circuit according to a first embodiment of the present invention.

3 shows a configuration of a DC offset compensation circuit according to a second embodiment of the present invention.

4 illustrates a circuit in which two transconductances in FIG. 3 are replaced with one transconductance according to a third embodiment of the present invention.

5 illustrates a circuit configuration of a conventional differential amplifier that can be implemented in an integrated circuit.

FIG. 6 adds a configuration for compensating for the DC offset to the circuit of the differential amplifier shown in FIG. 5 according to the fourth embodiment of the present invention.

7 shows another circuit configuration of a conventional differential amplifier that can be implemented in an integrated circuit.

FIG. 8 adds a configuration for compensating for the DC offset to the circuit of the linear amplifier shown in FIG. 7 according to the fifth embodiment of the present invention.

The present invention relates to a DC offset compensation circuit, and more particularly, a problem of deteriorating receiver sensitivity due to DC offset and 1 / f noise in a direct-conversion wireless receiver. It relates to a DC offset compensation circuit for improving the.

A radio receiver of the direct conversion method using a zero-intermediate frequency (IF) method does not go through a process of converting an input radio frequency signal into an intermediate frequency (IF) signal and immediately converts it into a baseband signal. Therefore, it does not include the intermediate frequency stage (intermediate frequency stage) of a conventional superheterodyne receiver. For this reason, the direct conversion wireless receiver has a simple structure and a low number of parts, which is considered to be an ideal structure for implementing a single chip integrated circuit, and has an advantage of not causing an IF image problem.

1 is a block diagram showing a circuit configuration of a general direct conversion type wireless receiver. The direct conversion wireless receiver includes an RF front-end 10, a channel select filter 20, and a baseband amplifier 30, as shown. do.

The RF shear unit 10 performs low frequency amplification of the input signal of the RF band received by the antenna, and then performs frequency down-conversion to move the signal to a band having a low frequency.

The channel selection filter 20 performs a function of selectively passing only a frequency signal of a desired channel among the output signals of the RF shearing unit 10.

The baseband amplifier 30 performs a function of amplifying the signal such that the size of the output signal of the channel selection filter 20 becomes a size suitable for processing by the demodulator.

However, in the direct conversion receiver, there is a problem in that the receiver sensitivity decreases due to DC offset and 1 / f noise. That is, in the direct conversion receiver, since a random DC offset voltage is transmitted to the entire receiver, there is a problem of saturating the final stage of the receiver. Therefore, in order to prevent the receiving end from being saturated by the random DC offset, an attempt has been made to remove the DC offset.

For example, in the configuration of a direct conversion type wireless receiver, a first high pass filter (HPF) consisting of a CR circuit is inserted between a channel selection filter and a baseband amplifier input to pass only a signal having a high frequency component. A manner of blocking the voltage can be used.

Alternatively, the low frequency signal component is extracted by feeding back the output signal of the baseband amplifier and passing through a low pass filter (LPF) composed of a CR circuit, and using the subtractor, extracting the low frequency signal component from the input signal. Subtracting may be used.

However, in the case of removing the DC offset in the above manner, the LPF or HPF circuit, which is composed of the resistor R and the capacitor C, inserted to remove the DC offset, should not seriously reduce the amplitude of the input signal. The time constant (RC) value of the LPF or HPF circuit is required to be much smaller than the BW of the input signal. This is expressed as follows.

In particular, for narrowband receivers (i.e., when the BW of the input signal is small), the time constant RC value of the inserted LPF or HPF circuit to remove the DC offset is required to have a very large value. However, in general, since the time constant RC value is too large to be implemented as an integrated circuit, in this case, there is a problem that an external resistor or an external capacitor device must be used.

Therefore, in order to remove the DC offset, there is a demand for a technology that can be implemented as an integrated circuit while having a high time constant value.

Therefore, the present invention is an amplifier that can be implemented as an integrated circuit without having an external resistor or an external capacitor element while having a high time constant value, and a DC offset compensation circuit capable of effectively removing DC offset problems and 1 / f noise. To provide.

A DC offset compensation circuit according to a first embodiment of the present invention for achieving the above object, the high-pass filter for removing the DC component of the signal input to the amplifier; And a transconductance having a positive feedback for providing a current proportional to an input voltage of the amplifier to an input terminal of the amplifier.

The DC offset compensation circuit according to the second embodiment of the present invention includes a first transconductance, an input resistor connecting the positive input terminal of the first transconductance and ground, and an output connecting the output terminal of the first transconductance and ground. A circuit for compensating for a DC offset of an amplifier comprising a resistor, said circuit comprising: a second input having a positive feedback coupled to an input of said first transconductance and having said output coupled to said positive input; It may be configured to include a transconductance.

A DC offset compensation circuit according to a third embodiment of the present invention includes a transconductance having a first output terminal and a second output terminal, the first output terminal having a positive feedback by being connected to a positive input terminal; An input resistor connecting the input terminal of the transconductance to ground; And an output resistor connecting the second output terminal of the transconductance to ground.

In the DC offset compensation circuit according to the fourth embodiment of the present invention, first and second amplifiers, first and second transistors having gate terminals connected to respective output terminals of the first and second amplifiers, and the first and second transistors, respectively. A current source having the same current value respectively connected to the drain terminals of the two transistors, a current source having the same current value respectively connected to the source terminals of the first and second transistors, a resistor connecting the drain terminals of the first and second transistors, And a resistor for connecting the drain terminals of the first and second transistors to compensate for the DC offset of the amplifier, wherein the gate terminal is commonly connected to the output terminal of the first amplifier together with the first transistor. 3 transistors; A fourth transistor having a gate terminal commonly connected to the output terminal of the second amplifier together with the second transistor; A current source having a current value KI scaled by a predetermined multiple K than the current value I of the current source, respectively connected to the drain terminals of the third and fourth transistors; And a current source having a current value KI scaled by a predetermined multiple K than the current value I of the current source, respectively connected to the source terminals of the third and fourth transistors.

The DC offset compensation circuit according to the fifth embodiment of the present invention includes a first and second transistors having respective current sources connected to drain terminals, and a third and second gate terminals connected to drain terminals of the first and second transistors. Fifth and sixth transistors having respective gate terminals commonly connected to source terminals of the fourth transistor, the third transistor, seventh and eighth transistors having respective gate terminals commonly connected to source terminals of the fourth transistor, DC of an amplifier including first and second input terminals for applying a voltage signal to the gate terminals of the first and second transistors, and two resistors having the same resistance values connecting the first and second input terminals, respectively. A circuit for compensating an offset, comprising: a current value 2KI scaled by a constant multiple of K at a middle node of the two resistors rather than twice the current value I of the current source; Supplying a constant current source; A ninth transistor having a drain terminal connected to the second input terminal and having a common base terminal with the seventh and eighth transistors; And a tenth transistor having a drain terminal connected to the first input terminal and having a common base terminal with the fifth and sixth transistors.

Hereinafter, a DC offset compensation circuit according to the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a configuration of a DC offset compensation circuit according to an embodiment of the present invention. As shown, it can be seen that the high pass filter 40 and the transconductance 50 having positive feedback are connected to the input terminal of the amplifier A. The high pass filter 40 including the capacitor C and the resistor R performs a function of blocking a DC voltage input to the amplifier A, and the transconductance 50 outputs a current GmVx proportional to the input voltage Vin. The equivalent resistance value Rx at the input node X of the amplifier can be expressed by the following equation.

In the above equation, when the GmR value is less than 1 and close to 1, the equivalent resistance Rx value has a larger resistance value than the original resistance value R when no positive feedback circuit is applied. From Equation 2, it can be seen that the increase ratio of the input resistance is (1-GmR) ^-1 . Therefore, the equivalent resistance value Rx of the circuit can be increased by adjusting the parameter Gm value of the transconductance 50.

On the other hand, a general voltage amplifier is composed of an input resistance, a transconductance, an output resistance bar. In the embodiment of FIG. 2, the voltage amplifier A may be configured as shown in FIG. 3 by replacing the voltage amplifier A with an input resistance, a transconductance, and an output resistance. have.

As shown in FIG. 3, it can be seen that a transconductance Gm2 having positive feedback is connected to an input terminal of an amplifier composed of an input resistor R, a transconductance Gm1, and an output resistor Rout.

Meanwhile, instead of using two transconductances Gm1 and Gm2 as in the embodiment of FIG. 3, if a transconductance cell capable of outputting two or more different current values is applied, only one transconductance of FIG. A circuit that performs the same function as the circuit can be implemented. The configuration thereof is shown in FIG. 4.

The transconductance Gm4 of FIG. 4 has two output currents KGmVin and GmVin. Among the output currents of the transconductance of FIG. 4, the current KGmVin of the feedback side may be scaled. In the embodiment of FIG. 4, it can be seen that K is scaled.

5 illustrates a circuit configuration of a conventional differential amplifier that can be implemented in an integrated circuit.

As shown, the first input voltage Vin1 is input to the first amplifier A1 and the output of the first amplifier A1 is connected to the gate of the first transistor Q1. The output resistor Rout and the resistor Rm are respectively connected to the drain and source terminals of the first transistor Q1, and the constant current source I is connected to the drain and source terminals of the first transistor Q1, respectively. Meanwhile, the negative input terminal of the first amplifier A1 is connected to the source terminal of the first transistor Q1.

Further, symmetrically with the above-described circuit configuration, the second input voltage Vin2 is input to the second amplifier A2, and the output of the second amplifier A2 is connected to the gate of the second transistor Q2. The output resistor Rout and the resistor Rm are respectively connected to the drain and source terminals of the second transistor Q2. A constant current source I is also connected to the drain and source terminals of the second transistor Q2, respectively. Meanwhile, the negative input terminal of the second amplifier A2 is connected to the source terminal of the second transistor Q2.

The value of the transconductance parameter Gm and the voltage gain A of the linear amplifier shown in FIG. 5 may be expressed as in the following equation.

FIG. 6 adds a configuration for compensating the DC offset to the circuit of the linear amplifier shown in FIG. 5 in accordance with the present invention.

As shown, the output of the first amplifier A1 is commonly connected to the gate terminal of the first transistor Q1 and the newly added third transistor Q3. In addition, a current source KI having a current value scaled by a predetermined multiple K is connected to the drain terminal of the newly added third transistor Q3, and the source of the first and third transistors Q1 and Q3 is connected. A current source having a current value (K + 1) I equal to the sum of the current values (KI, I) of each current source connected to the drain terminal is commonly connected to the terminal.

Also, symmetrically with the above-described circuit configuration, the output of the second amplifier A2 is commonly connected to the gate terminal of the second transistor Q2 and the newly added fourth transistor Q4. In addition, a current source KI having a current value scaled by a predetermined multiple K is connected to the drain terminal of the newly added fourth transistor Q4, and the source of the second and fourth transistors Q2 and Q4 is connected. A current source having a current value K + 1 I equal to the sum of the current values KI and I of each current source connected to the drain terminal is commonly connected to the terminal.

Meanwhile, the drain terminal of the newly added third transistor Q3 is connected to the positive input terminal of the second amplifier A2, and the source terminal of the newly added fourth transistor Q4 is connected to the positive input terminal of the first amplifier A1. Thus, the second amplifier A2 and the first amplifier A1 each have positive feedback.

In the linear amplifier of FIG. 6, the increase ratio of the input resistance may be expressed by the following equation.

In the circuit of Fig. 6, for example, if the values of the two resistors R and Rm are the same and K = 0.9, the rate of increase of the input resistance is 10. That is, the input resistance is equivalently 10 times, and thus the time constant is also 10 times.

7 shows another circuit configuration of a conventional differential amplifier that can be implemented in an integrated circuit. Briefly looking at the circuit configuration of Figure 7 as follows.

The first input terminal V11 is connected to the gate terminal of the first transistor Q11 and is connected to the second input terminal V12 via two resistors R / 2 and R / 2 having the same value. The drain terminal of the first transistor Q11 is connected to the gate terminal of the current source I and the third transistor Q13, the source terminal of the first transistor Q11 is grounded through the sixth transistor Q16, and the source of the second transistor Q12 is connected through the resistor Rm. Connected. The gate terminal of the sixth transistor Q16 is connected to the source terminal of the third transistor Q13 and the gate terminal of the fifth transistor Q15, and is also grounded through the current source I. The drain terminal of the fifth transistor Q15 is connected to the current source I, and the source terminal is grounded.

Symmetrically to the above-described configuration, the second input terminal V12 is connected to the gate terminal of the second transistor Q12 while being connected to the first input terminal V11 via two resistors R / 2 and R / 2. A current source and a gate terminal of the fourth transistor Q14 are connected to the drain terminal of the second transistor Q12, a source terminal of the second transistor Q12 is grounded through an eighth transistor Q18, and connected to a source of the first transistor Q11 through a resistor Rm. do. The gate terminal of the eighth transistor Q18 is connected to the source terminal of the fourth transistor Q14 and the gate terminal of the seventh transistor Q17 and is grounded through the current source I. The drain terminal of the seventh transistor Q17 is connected with a current source, and the source terminal is grounded.

8 adds a configuration for compensating for DC offset in the circuit of the linear amplifier shown in FIG. 7 in accordance with the present invention. As shown, it can be seen that one current source 2KI is further connected to a node between a resistor R / 2 connected to the first input terminal V11 and a resistor R / 2 connected to the second input terminal.

In addition, a tenth transistor Q10 having a drain connected to the first input terminal V11 is added, and the gate of the tenth transistor Q12 has a common base terminal with the seventh transistor Q17 and the eighth transistor Q18, and its source terminal is grounded. . Symmetrically, a ninth transistor Q19 having a drain connected to the second input terminal V12 was added, and the gate of the ninth transistor Q19 has a common base terminal with the fifth transistor Q15 and the sixth transistor Q16, and a source terminal thereof. Is grounded.

While specific embodiments of the present invention have been illustrated and described, the technical spirit of the present invention is not limited to the accompanying drawings and the above description, and various modifications can be made without departing from the spirit of the present invention. It will be apparent to those skilled in the art, and variations of this form will be regarded as belonging to the claims of the present invention without departing from the spirit of the present invention.

As described above, the present invention can be implemented as an integrated circuit without using an external resistor or an external capacitor element while having a high time constant value, thereby effectively eliminating the DC offset problem and 1 / f noise. can do.

Claims (8)

A high pass filter for removing the DC component of the signal input to the amplifier; And And a transconductance having a positive feedback for providing a current proportional to an input voltage of the amplifier to an input terminal of the amplifier. The method of claim 1, The high pass filter may include a resistor connecting between the input terminal and the ground of the amplifier and a capacitor connecting the input terminal and the voltage input terminal of the amplifier. A circuit for compensating for a DC offset of an amplifier comprising a first transconductance, an input resistor connecting the positive input terminal of the first transconductance and ground, and an output resistor connecting the output terminal of the first transconductance and ground To And a second transconductance having a positive feedback by connecting a positive input terminal to an input terminal of the first transconductance and having an output terminal connected to the positive input terminal. A transconductance having a first output terminal and a second output terminal, the transconductance having positive feedback by being coupled to the positive input terminal; An input resistor connecting the input terminal of the transconductance to ground; And And an output resistor connecting the second output terminal of the transconductance to ground. The method of claim 4, wherein And an output value of the first output terminal is a value obtained by scaling an output value of the second output terminal. First and second amplifiers A1 and A2, first and second transistors Q1 and Q2 having gate terminals connected to respective output terminals of the first and second amplifiers, respectively, and drain terminals of the first and second transistors. A resistor connecting the current source I having the same current value connected to each other, the current source I having the same current value connected to the source terminals of the first and second transistors, and the drain terminals of the first and second transistors, respectively. A circuit for compensating for a DC offset of an amplifier comprising Rout and a resistor Rm connecting the drain terminals of the first and second transistors, A third transistor having a gate terminal commonly connected to the output terminal of the first amplifier together with the first transistor; A fourth transistor having a gate terminal commonly connected to the output terminal of the second amplifier together with the second transistor; A current source having a current value KI scaled by a predetermined multiple K than the current value I of the current source, respectively connected to the drain terminals of the third and fourth transistors; And And a current source having a current value KI scaled by a predetermined multiple K than the current value I of the current source, respectively connected to the source terminals of the third and fourth transistors. The method of claim 6, And a drain terminal of the third transistor is connected to the positive input terminal of the second amplifier, and a drain terminal of the fourth transistor is connected to the positive input terminal of the fourth amplifier. First and second transistors having respective current sources connected to drain terminals, third and fourth transistors having respective gate terminals connected to drain terminals of the first and second transistors, and respective gates of source terminals of the third transistor. Voltage signals are applied to the fifth and sixth transistors of which the terminals are commonly connected, the seventh and eighth transistors of which the gate terminals are commonly connected to the source terminals of the fourth transistor, and the gate terminals of the first and second transistors, respectively. A circuit for compensating for a DC offset of an amplifier including first and second input terminals to be applied, and two resistors having the same resistance value connecting the first and second input terminals. A constant current source supplying an intermediate node of the two resistors with a current value 2KI scaled by a predetermined multiple K than a double value of the current value I of the current source; A ninth transistor having a drain terminal connected to the second input terminal and having a common base terminal with the seventh and eighth transistors; And And a tenth transistor having a drain terminal connected to the first input terminal and having a common base terminal with the fifth and sixth transistors.

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