KR20070001768A - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

A liquid crystal display device and a method for fabricating the same are provided to improve brightness by overcoming a limitation on an increase of an aperture ratio by mixing an IPS(In Plane Switching) mode and an FFS(Fringe Field Switching) mode, and improve a viewing angle by realizing micro multi-domains. Gate bus lines(111) are arranged on a lower substrate in a first direction. Data bus lines(121) are arranged in a second direction crossing the first direction. Common electrode lines(117) are arranged at areas formed by crossing the gate bus lines and the data bus lines, consisting of a plurality of common electrodes(117a) and plate common electrodes(117b). Thin film transistors are formed at areas where the gate bus lines and the data bus lines cross each other. Pixel electrode lines(131) are arranged on the lower substrate including the common electrode lines, insulated from the common electrode lines, consisting of a plurality of pixel electrodes(131a) placed between the plurality of common electrodes and a plurality of pixel electrodes(131a) overlapped with the plate common electrodes. An upper substrate is opposite to the lower substrate at a certain gap, having a color filter layer. A liquid crystal layer is arranged between the upper substrate and the lower substrate.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a layout diagram schematically showing an IPS mode liquid crystal display device according to the prior art;

2 is a cross-sectional view taken along the line II-II of FIG. 1 in the IPS mode liquid crystal display device according to the prior art.

3 is a layout diagram schematically showing a FFS mode liquid crystal display device according to the prior art;

4 is a cross-sectional view taken along line IV-IV of FIG. 3 in the conventional FFS mode liquid crystal display device.

5 is a layout diagram schematically illustrating a hybrid liquid crystal display device having a structure in which an IPS mode and an FFS mode are combined according to the present invention.

FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5 in the hybrid liquid crystal display having the structure in which the IPS mode and the FFS mode are combined according to the present invention.

7 is a graph illustrating a comparison of transmittance between the present invention and the prior art according to an applied voltage in a hybrid liquid crystal display having a structure in which an IPS mode and an FFS mode are combined according to the present invention.

-Code description of main parts of drawing-

110: lower substrate 111: gate bus line

113: gate electrode 115: storage wiring

Reference numeral 117: common electrode line 117a: common electrode 117b: plate portion 119: gate insulating film 121: data bus line 123: source electrode 125: drain electrode 127: insulating film 129: drain contact hole 131: pixel electrode line

131a: pixel electrode

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device having a high brightness and a high aperture ratio and a manufacturing method thereof.

The rapid development of device performance of active matrix liquid crystal displays has led to the widespread use of active matrix liquid crystal displays for applications such as flat panel television systems or high-information monitors for portable computers.

However, the TN display mode of the active matrix liquid crystal display devices currently used has fundamental problems such as narrow reagent angle characteristics and late response characteristics, especially late response characteristics in gray scale operation.

In order to solve this problem, various new concepts of the liquid crystal display have been proposed. For example, one method uses a multi-domain TN structure in which one calcination is divided into several subpixels, and the other method is a liquid crystal display. It uses OCB (Optically Compensated Birefringence) mode to compensate for the physical properties of the molecule.

However, the multi-domain method is complicated to form a multi domain, and there is a limit in improving the viewing angle. In addition, the OCB mode method has excellent electro-optical performance in terms of viewing angle characteristics and response speed, but has a disadvantage in that it is difficult to stably control and maintain the liquid crystal by a bias voltage.

Recently, as part of a new display mode, an IPS (In Plane Switching) mode in which electrodes for driving liquid crystal molecules are all formed on the same substrate has been proposed.

The liquid crystal display of the conventional IPS mode is described with reference to FIG. 1 as follows.

1 is a layout diagram schematically illustrating an IPS mode liquid crystal display device according to the related art.

As shown in FIG. 1, in the liquid crystal display of the conventional IPS mode, a plurality of gate bus lines 11 are arranged in parallel with each other in a first direction, that is, in an X direction, on a lower substrate. (21) are arranged parallel to each other in the second direction, that is, the Y direction, to form a matrix array. In this case, each matrix array defines a unit pixel area.

 In addition, the gate bus line 11 and the data bus line 21 are insulated with a gate insulating film (not shown) therebetween.

The common electrode line 15 is composed of, for example, a plurality of common electrodes 15a in a unit pixel space. In this case, the common electrode line 15 is disposed on the surface of the lower substrate 10 together with the gate bus line 11.

In addition, the pixel electrode line 31 is arranged on the common electrode line 15 with a gate insulating film (not shown) therebetween, and is composed of a plurality of pixel electrodes 31a. In this case, the plurality of pixel electrodes 31a are disposed to be positioned between the common electrodes 15a.

In addition, a thin film transistor is disposed at an intersection of the gate bus line 11 and the data bus line 21. The thin film transistor includes a gate electrode 13 extending from the gate bus line 11 and a data bus line ( A source electrode 23 extending from 21 and a drain electrode 25 spaced apart from the source electrode 23 by a predetermined interval. In this case, a channel layer (not shown) is formed between the source electrode 23 and the drain electrode 25 and the gate electrode 13 positioned below them.

In addition, the storage capacitors (not shown) are formed at overlapping portions of the common electrode line 15 and the pixel electrode 31.

A method of manufacturing the IPS mode liquid crystal display device configured as described above will be described with reference to FIG. 2 as follows.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1 in the conventional IPS mode liquid crystal display device.

As shown in FIG. 2, a metal film is formed on the lower substrate 10 to have a predetermined thickness. At this time, the metal film is made of at least one metal selected from the group consisting of aluminum, titanium, tantalum, chromium and combinations thereof.

Next, a predetermined portion of the metal film is patterned to form a common electrode line 15 including the gate bus line 11 and the plurality of common electrodes 15a.

Subsequently, a gate insulating layer 17 is formed on the lower substrate 10 on which the gate bus line 11 and the common electrode line 15 are formed.

Next, although not shown in the drawing, a channel layer (not shown) of a thin film transistor (not shown) is formed in a predetermined portion of the gate insulating film 17.

Subsequently, at least one metal film selected from the group consisting of aluminum, titanium, tantalum, chromium and combinations thereof is formed on the gate insulating film 17 on which the channel layer (not shown) is formed to have a predetermined thickness.

Next, the metal film is patterned to form a data bus line (not shown in FIG. 1) and a drain electrode (not shown in FIG. 1). In this case, a source electrode (not shown; 23 in FIG. 1) extends from the data bus line.

Subsequently, a planarization insulating layer 27 is formed on the lower substrate 10 on which the data bus line (not shown; 21 in FIG. 1) and the drain electrode (not shown) 25 are formed, and then a part of the planarization insulating layer 27 is formed. To form a drain contact hole (not shown; 29 of FIG. 1) exposing the drain electrode (not shown; 25 of FIG. 1).

Next, a transparent material such as ITO is deposited on the planarization insulating layer 27 including the drain contact hole (not shown; 29 of FIG. 1), and then patterned to connect to the drain electrode (not shown; 25 of FIG. 1). A pixel electrode (not shown; 31 in FIG. 1) is formed. In this case, the pixel electrode 31 is composed of a plurality of pixel electrodes 31a spaced apart from each other by a predetermined interval. In addition, each of the plurality of pixel electrodes 31a is disposed to be positioned between the plurality of common electrodes 15a previously formed.

Subsequently, although not shown in the drawing, a first alignment layer (not shown) is formed on the lower substrate 10 on which the pixel electrode line 31 is formed.

Although not shown in the drawings, a color filter layer (not shown) is stacked together with a black matrix (not shown) to prevent light from being transmitted on the upper substrate (not shown), and then a second alignment layer (not shown) is disposed thereon. To form.

After the fabrication of the lower substrate and the upper substrate is completed, the two substrates are arranged to be bonded to each other at a predetermined distance, and then the liquid crystal is injected between these substrates to complete the manufacture of the liquid crystal display device in the IPS mode.

As described above, according to the conventional liquid crystal display of the IPS mode, the transmittance at each electrode is low but the transmittance at the opening region is very good.

However, in the liquid crystal display of the IPS mode, since all or one of the common electrode and the pixel electrode use metal electrodes, the opening area of the liquid crystal display is reduced, and thus the transmittance is lowered. Therefore, as a result, since a strong backlight must be used to obtain an appropriate brightness, power consumption increases.

In addition, in order to solve this problem, a method of forming the common electrode and the pixel electrode with a transparent material has been proposed. Although this method has been slightly increased in terms of aperture ratio, it is not so excellent in terms of transmittance. That is, in order to form an in-plane field, the common electrode and the pixel electrodes should have a relatively wide width. In this structure, however, an electric field almost parallel to the substrate is formed between the electrodes, but the influence of the electric field does not affect the liquid crystal in most regions of the electrodes having a wide width, so that an equipotential surface is generated. do.

Therefore, because of this, the liquid crystal molecules on the upper electrode maintain the initial arrangement, so that the transmittance is hardly improved.

Meanwhile, the liquid crystal display of the FFS mode proposed to supplement the disadvantage of the liquid crystal display of the IPS mode will be described with reference to FIG. 3.

3 is a layout diagram schematically showing a FFS mode liquid crystal display device according to the prior art.

As shown in FIG. 3, in the conventional FFS mode liquid crystal display, a plurality of gate bus lines 41 are arranged in parallel with each other in a first direction, that is, in an X direction, on a lower substrate. (51) are arranged parallel to each other in the second direction, that is, the Y direction, to form a matrix array. In this case, each matrix array defines a unit pixel area.

 In addition, the gate bus line 41 and the data bus line 51 are insulated with a gate insulating film (not shown) therebetween.

A storage wiring 45a is formed on the lower substrate in the X direction, which is the first direction.

In addition, a common electrode line 45 is formed in a plate shape in a unit pixel space on a lower substrate including the storage wiring 45a. Here, the common electrode line 45 is made of a transparent conductive material.

A gate insulating film (not shown) is formed on the common electrode line 45, and a fringe field can be formed on the gate insulating film (not shown). A pixel electrode line 65 formed of four comb-shaped pixel electrodes 65a is formed.

In addition, a thin film transistor is disposed at the intersection of the gate bus line 41 and the data bus line 51. The thin film transistor includes a gate electrode 43 extending from the gate bus line 41 and a data bus line ( A source electrode 53 extending from 51 and a drain electrode 55 spaced apart from the source electrode 53 by a predetermined interval. Here, a channel layer (not shown) is formed between the source electrode 53 and the drain electrode 55 and the gate electrode 43 positioned below them.

A manufacturing method of the FFS mode liquid crystal display device configured as described above will be described with reference to FIG. 4 as follows.

4 is a cross-sectional view taken along line IV-IV of FIG. 3 in the FFS mode liquid crystal display device according to the prior art.

As shown in FIG. 4, a transparent material layer is formed on the lower substrate 40 to have a predetermined thickness.

Next, the transparent material layer is patterned to form a gate bus line 41 and a storage wiring 45a.

Subsequently, a transparent material layer is further formed on the lower substrate 10 including the storage wiring 45a and then patterned to form a common electrode line 45 having a plate shape.

Next, a gate insulating film 47 is formed on the lower substrate 40 on which the gate bus line 41 and the common electrode line 45 are formed.

Subsequently, although not shown in the drawing, a channel layer (not shown) of the thin film transistor (not shown) is formed in a predetermined portion of the gate insulating film 47.

Next, at least one metal film selected from the group consisting of aluminum, titanium, tantalum, chromium, and combinations thereof is formed to have a predetermined thickness on the gate insulating film 47 on which the channel layer (not shown) is formed.

Subsequently, the metal film is patterned to form a data bus line (not shown) and a drain electrode (not shown). In this case, a source electrode (not shown) extends from the data bus line.

Next, a planarization insulating layer 57 is formed on the lower substrate on which the data bus line (not shown) and the drain electrode (not shown) are formed, and then a portion of the planarization insulating layer 57 is patterned to form the drain electrode (not shown). A drain contact hole (not shown; 59 in FIG. 3) exposing 55 of FIG. 3 is formed.

Subsequently, a transparent material such as ITO is deposited on the planarization insulating layer 57 including the drain contact hole (not shown; 59 in FIG. 3), and then patterned and connected to the drain electrode (not shown; 55 in FIG. 3). A pixel electrode (not shown; 65 in FIG. 3) is formed. In this case, the pixel electrode 65 is composed of a plurality of pixel electrodes 65a spaced apart from each other by a predetermined interval. In addition, the plurality of pixel electrodes 65a overlap the common electrode line 45 having a plate shape.

Subsequently, although not shown, a first alignment layer (not shown) is formed on the lower substrate 40 on which the pixel electrode line 65 is formed.

Although not shown in the drawings, a color filter layer (not shown) is stacked together with a black matrix (not shown) to prevent light from being transmitted on the upper substrate (not shown), and then a second alignment layer (not shown) is disposed thereon. To form.

After fabrication of the lower substrate and the upper substrate is completed, the two substrates are arranged at a predetermined distance to each other, and then bonded to each other, and then liquid crystal is injected between these substrates to complete the manufacture of the liquid crystal display device of the FFS (Fringe Field Switching) mode. .

As described above, according to the proposed liquid crystal display of the FFS mode to solve the problems of the conventional liquid crystal display of the IPS mode, although the transmittance at the electrode is present, the transmittance at the opening region, i. It has a decreasing characteristic.

In addition, since the portion where the common electrode part and the pixel electrode overlap is applied as a parasitic capacitor, the problem does not occur in the small model, but in the large model, the capacitor size becomes too large, which may cause problems such as poor charging characteristics. have.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, by applying a hybrid liquid crystal display device in which the conventional IPS mode and FFS mode are mixed to improve high brightness / high aperture ratio and compensate for a wide viewing angle. The present invention provides a liquid crystal display and a method of manufacturing the same, which can achieve variable storage capacity.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a gate bus line disposed in a first direction on a lower substrate and a data bus line disposed in a second direction crossing the first direction; A common electrode line disposed in an area where the gate bus line and the data bus line cross each other and including a plurality of common electrodes and a plate common electrode; A thin film transistor having a gate bus line and a data bus line intersected at each other; A plurality of pixel electrodes disposed on the lower substrate including the common electrode line and insulated from the common electrode line, and disposed to overlap the common plate electrode and the plurality of pixel electrodes positioned between the plurality of common electrodes. A pixel electrode line; An upper substrate disposed on the lower substrate so as to face each other at a predetermined interval and provided with a color filter layer; And a liquid crystal layer disposed between the upper substrate and the lower substrate.

In addition, the manufacturing method of the liquid crystal display device according to the present invention for achieving the above object comprises the steps of providing a lower substrate and an upper substrate which are disposed facing a predetermined interval; Forming a gate bus line on the lower substrate; Forming a common electrode line including a plurality of common electrodes and a plate common electrode on a unit pixel area of the lower substrate; Forming a data bus line to cross the gate bus line; Forming a thin film transistor in an area where the gate bus line and the data bus line cross each other; A pixel electrode comprising a plurality of pixel electrodes insulated from the common electrode line on the lower substrate including the common electrode line and positioned between the plurality of common electrodes and a plurality of pixel electrodes overlapping with the plate common electrode. Forming a line; Forming a color filter layer on the upper substrate; Arranging the upper substrate to face each other at a predetermined interval on the lower substrate; And disposing a liquid crystal layer between the upper substrate and the lower substrate.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a layout diagram schematically illustrating a hybrid liquid crystal display device having a structure in which an IPS mode and an FFS mode are combined according to the present invention.

As shown in FIG. 5, in the hybrid liquid crystal display having a mixed structure of the IPS mode and the FFS mode according to the present invention, a plurality of gate bus lines 111 are arranged in a first direction, that is, X on the lower substrate. Directions are arranged parallel to each other, and a plurality of data bus lines 121 are arranged in parallel to each other in the second direction, that is, the Y direction, thereby forming a matrix array. In this case, each matrix array defines a unit pixel area.

In addition, the gate bus line 111 and the data bus line 121 are insulated with a gate insulating film (not shown) therebetween.

In addition, the storage substrate 115 is formed on the lower substrate by being spaced apart from the gate bus line 111 by a predetermined interval in the X direction, which is the first direction.

In addition, a common electrode line 117 including a plurality of common electrodes 117a and a plate portion 117b is formed in a unit pixel space on a lower substrate on which the storage wiring 115 is formed. In this case, the common electrode line 117 is disposed on the surface of the lower substrate (not shown; 110 in FIG. 6) together with the gate bus line 111 and the storage wiring 115.

A gate insulating film (not shown) is formed on the lower substrate on which the common electrode line 117 including the plurality of common electrodes 117a and the plate portion 117b is formed. Pixel electrode lines 131 formed of four comb-shaped pixel electrodes 131a are formed. Here, a region consisting of pixel electrodes 131a positioned between the plurality of common electrodes 117a constitutes a liquid crystal display device in an IPS mode, and has a plurality of comb-shaped teeth overlapping with the plate portion 117b. The area composed of the pixel electrodes 131a constitutes a liquid crystal display device in FFS mode.

In addition, a thin film transistor is disposed at an intersection of the gate bus line 111 and the data bus line 121. The thin film transistor includes a gate electrode 113 extending from the gate bus line 111 and a data bus line ( A source electrode 123 extending from 121 and a drain electrode 125 spaced apart from the source electrode 123 by a predetermined interval. In this case, a channel layer (not shown) is formed between the source electrode 123 and the drain electrode 125 and the gate electrode 113 positioned below them.

A method of manufacturing a hybrid liquid crystal display according to the present invention configured as described above will be described with reference to FIG. 6.

FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5 in the hybrid liquid crystal display having a structure in which the IPS mode and the FFS mode are combined according to the present invention.

Referring to FIG. 6, a metal film, for example, is formed on the lower substrate 110 to have a thickness of 2500 to 3500 mm 3. At this time, the metal film is made of at least one metal selected from the group consisting of aluminum, titanium, tantalum, chromium and combinations thereof.

Next, a predetermined portion of the metal film is patterned to form a common electrode line 117 including a gate bus line (not shown in FIG. 5), a plurality of common electrodes 117a, and a plate portion 117b.

Subsequently, a gate insulating layer 119 is formed on the lower substrate 110 on which the gate bus line 111 and the common electrode line 117 are formed.

Next, although not shown in the drawing, a channel layer (not shown) of the thin film transistor (not shown) is formed in a predetermined portion of the gate insulating film 119.

Subsequently, at least one metal film selected from the group consisting of aluminum, titanium, tantalum, chromium, and combinations thereof is formed on the gate insulating film 1179 on which the channel layer (not shown) is formed, for example, at a thickness of 4000 to 4500 kPa. do.

Next, the metal layer is patterned to form a data bus line (not shown; 121 in FIG. 5) and a drain electrode (not shown; 125 in FIG. 5). In this case, a source electrode (not shown) 123 of FIG. 5 is extended from the data bus line.

Subsequently, the planarization insulating film 127 is formed on the lower substrate 110 on which the data bus line (not shown; 121 of FIG. 5) and the drain electrode (not shown; 125 of FIG. 5) are formed using an organic film or an insulating material. After forming, a portion of the planarization insulating layer 127 is patterned to form a drain contact hole (not shown; 129 of FIG. 5) exposing the drain electrode 125 (see FIG. 5).

Subsequently, a transparent material such as ITO is deposited on the planarization insulating layer 127 including the drain contact hole (not shown; 129 of FIG. 5), and then patterned to connect to the drain electrode (not shown; 125 of FIG. 5). A pixel electrode (not shown) 131 of FIG. 5 is formed. In this case, the pixel electrode 131 is composed of a plurality of comb-shaped pixel electrodes 131a spaced apart from each other by a predetermined interval. In addition, some of the plurality of pixel electrodes 131a are disposed to be positioned between the plurality of common electrodes 117a previously formed, and some of the plurality of pixel electrodes 131a overlap the plate portion 117b of the common electrode line 117. It is arranged. In this case, an area in which the plurality of pixel electrodes 131a and the plurality of common electrodes 117a are positioned forms a liquid crystal display device in an IPS mode, and the plurality of pixel electrodes 131a and the common electrode line 117 The plate portion 117b forms a liquid crystal display device in FFS mode.

Subsequently, although not shown, a first alignment layer (not shown) is formed on the lower substrate 110 on which the pixel electrode line 131 is formed.

On the other hand, although not shown in the drawing, after laminating a color filter layer (not shown) together with a black matrix (not shown) on the upper substrate (not shown) bonded to the lower substrate 110 to prevent light from being transmitted. A second alignment film (not shown) is formed thereon.

After fabrication of the lower substrate and the upper substrate is completed, the two substrates are arranged and bonded together at a predetermined distance from each other, and then the liquid crystal is injected between these substrates to form a hybrid liquid crystal display in which the IPS mode and the FFS mode are mixed. Complete the manufacture of the device.

On the other hand, with reference to Figure 7 with respect to the light transmittance of the hybrid type liquid crystal display device of the IPS mode and FFS mode mixed as described above and the conventional liquid crystal display device of the IPS mode and FFS mode as follows.

7 is a graph illustrating a comparison between transmittances of the present invention and the prior art according to an applied voltage in a hybrid liquid crystal display having a structure in which an IPS mode and an FFS mode are combined according to the present invention.

As shown in FIG. 7, as a result of simulation using the same area, the conventional IPS mode and the FFS mode in the case of the hybrid liquid crystal display device having the combined structure of the IPS mode and the FFS mode according to the present invention. It can be seen that the mode transmittance is higher than that, and the transmittance-voltage (TV) characteristic is moderate, which is advantageous for dividing gray.

As described above, according to the liquid crystal display and the manufacturing method thereof according to the present invention, a plurality of pixel electrodes are formed on the common electrode of the plate type and the IPS mode of the structure in which the pixel electrodes are disposed between the plurality of common electrodes, respectively. By applying the mixed FFS mode with overlapping structure, luminance can be improved by overcoming the limit of aperture ratio increase due to the gap between electrodes and the limit of the number of blocks in the existing IPS, and the fine operation by the mixed operation of IPS mode and FFS mode Multi-domainization is enabled, which is effective for improving the viewing angle.

In addition, in a panel of 30 inches or less, which is large in FFS mode, an increase in storage capacity causes an increase in wiring load and poor charging characteristics of the panel. However, when the structure of the present invention is used, only the required storage capacity is used to drive the FFS. The opening ratio can be improved compared to the existing structure.

On the other hand, while described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below And can be changed.

Claims (14)

Lower substrate; A gate bus line disposed in a first direction on the lower substrate and a data bus line disposed in a second direction crossing the first direction; A common electrode line disposed in an area where the gate bus line and the data bus line cross each other and including a plurality of common electrodes and a plate common electrode; A thin film transistor having a gate bus line and a data bus line intersected at each other; A plurality of pixel electrodes disposed on the lower substrate including the common electrode line and insulated from the common electrode line, and disposed to overlap the common plate electrode and the plurality of pixel electrodes positioned between the plurality of common electrodes. A pixel electrode line; An upper substrate disposed on the lower substrate so as to face each other at a predetermined interval and provided with a color filter layer; And And a liquid crystal layer disposed between the upper substrate and the lower substrate. The liquid crystal display device according to claim 1, wherein an insulating film is formed between the common electrode line and the pixel electrode line. The thin film transistor of claim 1, wherein the thin film transistor includes a gate electrode extending from the gate bus line, a source electrode extending from the data bus line, and a drain electrode formed to be spaced apart from the data bus line by a predetermined distance. LCD display device. 4. The liquid crystal display device according to claim 3, wherein a gate insulating film and a channel layer are formed between the gate electrode and the source electrode and the drain electrode disposed thereon. The display device of claim 1, wherein an area insulated from the common electrode line and provided with a plurality of pixel electrodes respectively positioned between the plurality of common electrodes forms an IPS mode liquid crystal display, and overlaps the plate common electrode. And an area having a plurality of pixel electrodes positioned in such a manner as to constitute an FFS mode liquid crystal display device. The liquid crystal display of claim 1, wherein a storage wiring is formed on a surface of the lower substrate spaced apart from the gate bus line by a predetermined distance. The liquid crystal display of claim 1, wherein the common electrode line and the pixel electrode line are transparent. Providing a lower substrate and an upper substrate disposed to face each other at a predetermined interval; Forming a gate bus line on the lower substrate; Forming a common electrode line including a plurality of common electrodes and a plate common electrode on a unit pixel area of the lower substrate; Forming a data bus line to cross the gate bus line; Forming a thin film transistor in an area where the gate bus line and the data bus line cross each other; A pixel electrode comprising a plurality of pixel electrodes insulated from the common electrode line on the lower substrate including the common electrode line and positioned between the plurality of common electrodes and a plurality of pixel electrodes overlapping with the plate common electrode. Forming a line; Forming a color filter layer on the upper substrate; Arranging the upper substrate to face each other at a predetermined interval on the lower substrate; And Disposing a liquid crystal layer between the upper substrate and the lower substrate. The method of claim 8, further comprising forming an insulating layer between the common electrode line and the pixel electrode line. The thin film transistor of claim 8, wherein the thin film transistor includes a gate electrode extending from the gate bus line, a source electrode extending from the data bus line, and a drain electrode formed to be spaced apart from the data bus line by a predetermined distance. Liquid crystal display device manufacturing method. The method of claim 10, further comprising forming a gate insulating layer and a channel layer between the gate electrode and the source electrode and the drain electrode disposed thereon. The LCD device of claim 8, wherein an area insulated from the common electrode line and provided with a plurality of pixel electrodes respectively positioned between the plurality of common electrodes forms an IPS mode liquid crystal display, and overlaps the plate common electrode. And a region having a plurality of pixel electrodes positioned so as to form an FFS mode liquid crystal display device. 10. The method of claim 8, wherein the storage bus line is formed at the same time as the gate bus line at a predetermined interval from the gate bus line. The method of claim 8, wherein the common electrode line and the pixel electrode line are transparent.

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