KR20070000186A - Ball grid array type stack package - Google Patents

Ball grid array type stack package Download PDF

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Publication number
KR20070000186A
KR20070000186A KR1020050055718A KR20050055718A KR20070000186A KR 20070000186 A KR20070000186 A KR 20070000186A KR 1020050055718 A KR1020050055718 A KR 1020050055718A KR 20050055718 A KR20050055718 A KR 20050055718A KR 20070000186 A KR20070000186 A KR 20070000186A
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South Korea
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package
semiconductor chip
lead
exposed
inner lead
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KR1020050055718A
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Korean (ko)
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KR20060136156A (en
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문기일
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주식회사 하이닉스반도체
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Priority to KR1020050055718A priority Critical patent/KR20060136156A/en
Priority claimed from KR1020050055718A external-priority patent/KR20060136156A/en
Publication of KR20070000186A publication Critical patent/KR20070000186A/en
Publication of KR20060136156A publication Critical patent/KR20060136156A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Abstract

A ball grid array type stack package is provided to reduce a total size of a stacked package by minimizing a size of a single package. A plurality of single packages includes exposed upper and lower patterns and are stacked by using ACFs(Anisotropic Conductive Films)(40). A solder ball(50) is attached on the exposed lower pattern of the single package. A semiconductor chip(33) is loaded on a die paddle(32) of a lead frame which is curved to a top part in order to form a perpendicular state between an outside inner-lead and an inside inner-lead. An inner lead(31) is sealed by using a sealant in order to be exposed to upper and lower surfaces including a lateral surface of the single package.

Description

볼 그리드 어레이 타입 스택 패키지{Ball Grid Array type stack package}Ball Grid Array type stack package

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는 단품 패키지의 크기를 최소화시켜 스택된 패키지 전체 사이즈를 감소시킨 볼 그리드 어레이(Ball Grid Array: 이하, BGA)타입 스택 패키지에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a ball grid array (hereinafter referred to as BGA) type stack package which minimizes the size of a single package and reduces the total size of the stacked package.

전기/전자 제품의 고성능화가 진행됨에 따라 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 많은 기술들이 제안 및 연구되고 있다. 그런데, 패키지는 하나의 반도체 칩이 탑재되는 것을 기본으로 하기 때문에 소망하는 용량을 얻는데 한계가 있다. As the performance of electrical / electronic products is advanced, many technologies for mounting a larger number of packages on a limited size substrate have been proposed and studied. By the way, since a package is based on which one semiconductor chip is mounted, there is a limit in obtaining desired capacity.

따라서, 소망하는 용량을 얻기 위한 방법으로서 스택킹(stacking) 기술이 개발되었고, 현재 이에 대한 연구가 활발히 진행되고 있다. Therefore, a stacking technique has been developed as a method for obtaining a desired capacity, and research on this is actively conducted.

반도체 업계에서 말하는 스택킹이란, 적어도 2개 이상의 반도체 칩을 스택하여 메모리 용량을 배가시키는 기술이다. 이러한 스택킹 기술에 의하면, 2개의 128M DRAM급 칩을 스택하여 256M DRAM급으로 구성할 수 있으며, 이에 따라, 실장 밀도 및 실장 면적 사용의 효율성을 높일 수 있다. Stacking as used in the semiconductor industry is a technique of stacking at least two or more semiconductor chips to double the memory capacity. According to such a stacking technology, two 128M DRAM chips can be stacked to be 256M DRAM, thereby increasing the mounting density and the efficiency of using the mounting area.

여기서, 스택 패키지의 구현 방법으로는 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 칩 스택 방법과 패키징된 2개의 패키지를 스택하는 패키지 스택 방법이 있다. Here, the stack package may be implemented as a chip stack method for embedding two stacked chips in one package and a package stack method for stacking two packaged packages.

이하에서는 종래의 스택 패키지들을 도 1 및 도 2를 참조하여 간략하게 설명하도록 한다. Hereinafter, the conventional stack packages will be briefly described with reference to FIGS. 1 and 2.

도 1은 TSOP(Thin Small Outline Package) 타입 스택 패키지를 도시한 단면도이다. 1 is a cross-sectional view illustrating a thin small outline package (TSOP) type stack package.

도시한 바와 같이, 이 스택 패키지는 TSOP 타입 바텀 패키지(10a) 상에 TSOP 타입 탑 패키지(10b)가 스택되어 있고, 상기 패키지들(10a, 10b)의 연직 선상에 놓인 아우터 리드들(12a, 12b)이 상호 연결된 구조이다. As shown, this stack package includes a stack of TSOP type top packages 10b on a TSOP type bottom package 10a and outer leads 12a and 12b lying on a vertical line of the packages 10a and 10b. ) Is an interconnected structure.

이러한 스택 패키지는 각 패키지(10a, 10b)에서의 아우터 리드들(12a, 12b)이 외부로 노출되어 있으므로, 그 구현이 비교적 용이하다. Such a stack package is relatively easy to implement since the outer leads 12a and 12b in each package 10a and 10b are exposed to the outside.

도 2는 덴스 팩(Dense PAC)의 스택 패키지를 도시한 단면도이다. 2 is a cross-sectional view illustrating a stack package of a dense pack (Dense PAC).

도시한 바와 같이, 이 스택 패키지는 기판(22a, 22b) 상에 패키지를 실장한 상태로 언더필 (underfill)을 행하여 바텀 패키지(20a) 및 탑 패키지(20b)를 구현한 후, 기판들 (22a, 22b) 사이에 인터포져(interposer : 24) 및 솔더 컬럼(solder column)를 개재시켜 스택 및 전기적 연결이 이루어지도록 한 구조이다. As shown, the stack package underfills the package on the substrates 22a and 22b to implement the bottom package 20a and the top package 20b, and then the substrates 22a, The stack and the electrical connection are made through the interposer 24 and the solder column between 22b).

도면부호 26은 실장시 이용되는 솔더 볼을 나타낸다. Reference numeral 26 denotes a solder ball used for mounting.

그러나, 도 1의 스택 패키지는 TSOP 패키지들의 스택은 가능하겠지만, BGA 패키지는 몸체에 솔더 볼이 존재하는 것과 관련해서 외부로 트레이스(trace)를 연결해야 하는 바, BGA 패키지들의 스택은 실질적으로 곤란하다. However, although the stack package of FIG. 1 may be a stack of TSOP packages, the BGA package requires a trace to be connected to the outside in relation to the presence of solder balls in the body, which makes stacking of BGA packages practically difficult. .

도 2의 스택 패키지는 두 개의 기판을 사용해야 하고, 그리고, 인터포져와의 솔더링을 행해야 하므로 공정이 복잡하고 제조비용이 많이 소요된다. 아울러, 측면 쪽으로 인터포져가 차지하는 면적이 크며, 또한, 두개의 개별 패키지가 적층되는 구조를 가지므로, 패키지의 소형화 및 박형화 구현이 어려워지는 문제가 있다.The stack package of FIG. 2 requires the use of two substrates, and soldering with an interposer is complicated and expensive to manufacture. In addition, since the interposer occupies a large area toward the side, and also has a structure in which two individual packages are stacked, there is a problem that it is difficult to reduce the size and thickness of the package.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 단품 패키지의 크기를 최소화시켜, 스택된 패키지 전체의 크기를 감소시킨 BGA 타입 스택 패키지를 제공함에 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a BGA type stack package that minimizes the size of a single package, thereby reducing the size of the entire stacked package.

상기와 같은 목적을 달성하기 위하여, 본 발명의 일면에 따라, BGA 타입 스택 패키지가 제공되며: 이 스택 패키지는, 상부면 및 하부면에 패턴이 노출되며, ACF(Anisotropic Conductive Film)을 매개로 상하로 적층되는 다수의 단품 패키지; 및 최하면에 위치한 상기 단품 패키지의 하부면에 노출된 패턴 상에 부착되는 솔더 볼;을 포함하며, 상기 단품 패키지는, 외측 인너 리드가 내측 인너 리드에 수직하도록 상부로 휘어져 있는 리드 프레임의 다이 패들 상에 반도체 칩이 탑재되고, 상기 인너 리드가 패키지의 측면을 포함한 상부 및 하부면에 노출되도록 봉지제에 의해 밀봉된 것을 특징으로 한다.In order to achieve the above object, according to an aspect of the present invention, there is provided a BGA type stack package: the stack package, the pattern is exposed on the upper and lower surfaces, the upper and lower via an anisotropic conductive film (ACF) A plurality of single packages stacked in a stack; And a solder ball attached to a pattern exposed on a lower surface of the one-piece package located at a bottom surface thereof, wherein the one-piece package includes a die paddle of a lead frame in which the outer inner lead is bent upwardly so as to be perpendicular to the inner inner lead. A semiconductor chip is mounted thereon, and the inner lead is sealed by an encapsulant such that the inner lead is exposed to the upper and lower surfaces including the side surface of the package.

상기 구성에서, 상기 단품 패키지에 탑재된 반도체 칩은 상기 다이 패들 상에 접착제를 매개로 페이스 업 방식으로 부착되며, 상기 반도체 칩의 본딩패드와 상기 리드 프레임의 인너 리드는 금속 와이어에 의해 전기적으로 접속된다.In the above configuration, the semiconductor chip mounted on the single package is attached to the die paddle in a face-up manner via an adhesive, and the bonding pad of the semiconductor chip and the inner lead of the lead frame are electrically connected by metal wires. do.

상기 구성에서, 상기 단품 패키지에 탑재되는 반도체 칩은 상기 다이 패들 상에 접착제를 매개로 페이스 다운 방식으로 부착되며, 상기 반도체 칩의 본딩패드와 상기 리드 프레임의 인너 리드는 범프를 통해 전기적으로 접속된다.In the above configuration, the semiconductor chip mounted in the single package is face down attached to the die paddle by means of an adhesive, and the bonding pad of the semiconductor chip and the inner lead of the lead frame are electrically connected through bumps. .

(실시예)(Example)

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3에는 본 발명의 실시예에 따른 BGA 타입 스택 패키지의 단면도를 도시한다.3 is a cross-sectional view of a BGA type stack package according to an embodiment of the present invention.

도시한 바와 같이, 본 발명의 실시예에 따른 BGA 타입 스택 패키지는, 상부면 및 하부면에 패턴이 노출된 단품 패키지(30)가 ACF(Anisotropic Conductive Film:40)를 매개로 상하로 적층되며, 아래에 위치한 단품 패키지(30)의 하부면에 노출된 패턴에는 솔더 볼(50)이 부착된 구조를 갖는다. 여기서, ACF(40)는 내부에 포함된 접착층을 통해 단품 패키지(30)를 상하로 접착시키며, 또한, 내부에 포함된 전도성 입자(conductive particle:41)를 통해 적층된 단품 패키지(30)의 노출된 패턴을 전기적으로 연결한다. 아울러, 단품 패키지(30)는 인너 리드(31)의 외측이 내측에 수직하도록 상부로 휘어져 있는 리드 프레임의 다이 패들(32) 상에 반도체 칩(33)이 탑재되고, 상기 인너 리드(31)가 패키지의 측면을 포함한 상부 및 하부면에 노출되도록 봉지제(35)에 의해 밀봉된 구조를 갖는다. 구체적으로, 단품 패키지(30)에 탑재되는 반도체 칩(33)은 접착제(36)를 매개로 리드 프레임의 다이 패들(32) 상에 페이스 업 방식으로 부착되며, 반도체 칩(33)의 본딩 패드(도시안됨)와 리드 프레임의 인너 리드(31)는 금속 와이어(34)에 의해 전기적으로 연결된다.As shown, in the BGA type stack package according to the embodiment of the present invention, the single-piece package 30 having patterns exposed on the top and bottom surfaces thereof is stacked up and down via an ACF (Anisotropic Conductive Film) 40, The pattern exposed on the lower surface of the unit package 30 positioned below has a structure in which solder balls 50 are attached. Here, the ACF 40 bonds the unit package 30 up and down through an adhesive layer included therein, and also exposes the unit package 30 stacked through the conductive particles 41 contained therein. The connected patterns are electrically connected. In addition, in the single package 30, the semiconductor chip 33 is mounted on the die paddle 32 of the lead frame bent upward so that the outer side of the inner lead 31 is perpendicular to the inner side, and the inner lead 31 is It has a structure sealed by the encapsulant 35 to be exposed to the upper and lower surfaces including the side of the package. Specifically, the semiconductor chip 33 mounted on the unit package 30 is attached to the die paddle 32 of the lead frame via the adhesive 36 in a face-up manner, and the bonding pads of the semiconductor chip 33 Not shown) and the inner lead 31 of the lead frame are electrically connected by a metal wire 34.

이하에서는, 도 4 내지 도 9를 참조하여 본 발명의 실시예에 따른 BGA 타입 스택 패키지의 제조 공정을 설명하기로 한다.Hereinafter, a manufacturing process of a BGA type stack package according to an embodiment of the present invention will be described with reference to FIGS. 4 to 9.

먼저, 도 4를 참조하면, 인너 리드(31) 및 다이 패들(32)를 구비하며, 인너 리드(31)의 외측이 내측에 수직하도록 상부로 휘어져 있는 리드 프레임을 제작한다.First, referring to FIG. 4, a lead frame having an inner lead 31 and a die paddle 32 is bent upward so that an outer side of the inner lead 31 is perpendicular to an inner side thereof.

다음, 도 5를 참조하면, 리드 프레임의 다이 패들(32) 상에는 접착제(36)를 매개로 반도체 칩(33)이 페이스 업 방식으로 부착되며, 반도체 칩(33)의 본딩 패드(도시안됨)와 리드 프레임의 인너 리드(31)는 금속 와이어(34)에 의해 상호 전기적으로 연결된다.Next, referring to FIG. 5, the semiconductor chip 33 is attached to the die paddle 32 of the lead frame through the adhesive 36 in a face-up manner, and the bonding pad (not shown) of the semiconductor chip 33 is attached to the die paddle 32. The inner leads 31 of the lead frame are electrically connected to each other by metal wires 34.

그런 다음, 도 6을 참조하면, 금속 와이어(34) 및 반도체 칩(33)을 보호하고 패키지 외형을 형성하기 위해, 반도체 칩(33)을 포함한 일정영역을 봉지제(35)로 밀봉한다.Then, referring to FIG. 6, in order to protect the metal wire 34 and the semiconductor chip 33 and form a package outline, a certain region including the semiconductor chip 33 is sealed with the encapsulant 35.

그리고, 도 7을 참조하면, 봉지제(35)에 의해 외형이 형성된 단품 패키지의 상부면 및 하부면에 그라인딩(grinding)이 실시되어, 스택에 사용되어질 두께가 최소화된 단품 패키지(30)를 얻을 수 있다. 이 때, 패키지는 인너 리드(31)가 패키지의 측면을 포함한 상부 및 하부면에 노출되도록 봉지제(35)에 의해 밀봉된 구조를 갖게된다.7, grinding is performed on the top and bottom surfaces of the one-piece package in which the external shape is formed by the encapsulant 35 to obtain the one-piece package 30 having the minimum thickness to be used in the stack. Can be. At this time, the package has a structure sealed by the encapsulant 35 such that the inner lead 31 is exposed to the upper and lower surfaces including the side of the package.

그리고 나서, 도 8을 참조하면, 그라인딩이 완료된 단품 패키지(30) 상부면에는 ACF(40)가 부착된다.Then, referring to FIG. 8, the ACF 40 is attached to the upper surface of the unit package 30 in which grinding is completed.

이 후, 도 9를 참조하면, ACF(40)가 부착된 단품 패키지(30) 상부면에는 또 다른 단품 패키지(30)가 적층되고, 하층 단품 패키지(30)의 하부면에 노출된 인너 리드(31)에는 솔더 볼(50)이 부착된다. 이 때, ACF(40)는 내부에 포함된 접착층을 통해 단품 패키지(30)를 상하로 접착시키며, 또한, 내부에 포함된 전도성 입자(conductive particle:41)를 통해 적층된 단품 패키지(30)의 노출된 인너 리드(32)를 전기적으로 연결한다. Subsequently, referring to FIG. 9, another single package 30 is stacked on an upper surface of the single package package 30 to which the ACF 40 is attached, and an inner lead exposed to the lower surface of the lower single package package 30 ( 31, a solder ball 50 is attached. At this time, the ACF 40 adheres the unit package 30 up and down through an adhesive layer included therein, and further, the unit package 30 of the unit package 30 stacked through the conductive particles 41 contained therein. The exposed inner lead 32 is electrically connected.

이상, 전술한 본 발명의 실시예에서는 두개의 단품 패키지(30)가 상하로 적층된 구조를 설명하였지만, 본 발명에 따른 BGA 타입 스택 패키지는 도 10에 도시한 바와 같이, 두개 이상의 단품 패키지(30)를 적층할 수 있다.In the above-described embodiment of the present invention, a structure in which two single-piece packages 30 are stacked up and down has been described, but the BGA type stack package according to the present invention is shown in FIG. ) Can be laminated.

또한, 도 11에 도시한 바와 같이, 본 발명에 따른 BGA 타입 스택 패키지에 적용되는 단품 패키지(30)는, 리드 프레임의 다이 패들(32) 상에 접착제(36)를 매개로 에지패드 형 반도체 칩(37)이 페이스 다운 방식으로 부착되며, 반도체 칩(37)의 본드 핑거(도시안됨)와 리드 프레임의 인너 리드(31)는 범프(38)를 통해 전기적으로 연결된 구조를 적용할 수 있다.In addition, as shown in FIG. 11, the one-piece package 30 applied to the BGA type stack package according to the present invention is an edge pad type semiconductor chip on the die paddle 32 of the lead frame via an adhesive 36. The 37 is attached in a face-down manner, and the bond finger (not shown) of the semiconductor chip 37 and the inner lead 31 of the lead frame may have a structure electrically connected to each other through the bump 38.

이상에서 살펴 본 바와 같이, 본 발명에 따른 BGA 타입 스택 패키지는, 인너리드의 구조를 변형한 리드 프레임 상에 반도체 칩을 탑재하고, 그라인딩을 통해 패키지의 높이를 최소화시킨 단품 패키지가 ACF를 매개로 적층되는 구조를 가짐으로써, 스택 패키지의 높이를 최소화시킬 수 있다.As described above, in the BGA type stack package according to the present invention, a semiconductor package is mounted on a lead frame in which the inner lead structure is modified, and a single package that minimizes the height of the package through grinding is connected via ACF. By having a stacked structure, it is possible to minimize the height of the stack package.

상기한 바와 같은 본 발명의 구성에 따라, 패키지 스택의 형태를 가짐과 동시에 칩 스택 만큼의 박형화된 패키지의 구현이 가능하다.According to the configuration of the present invention as described above, it is possible to implement a thin package as much as the chip stack while having the form of a package stack.

본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

도 1은 TSOP(Thin Small Outline Package) 타입 스택 패키지를 도시한 단면도. 1 is a cross-sectional view showing a thin small outline package (TSOP) type stack package.

도 2는 덴스 팩(Dense PAC)의 스택 패키지를 도시한 단면도. 2 is a cross-sectional view showing a stack package of a dense PAC.

도 3은 본 발명의 실시예에 따른 BGA 타입 스택 패키지의 단면도.3 is a cross-sectional view of a BGA type stack package according to an embodiment of the present invention.

도 4 내지 도 9는 본 발명의 실시예에 따른 BGA 타입 스택 패키지의 제조 공정을 설명하기 위한 도면.4 to 9 are views for explaining the manufacturing process of the BGA type stack package according to an embodiment of the present invention.

도 10 및 도 11은 본 발명의 다른 실시예에 따른 BGA 탕비 스택 패키지의 단면도.10 and 11 are cross-sectional views of the BGA Tangy stack package according to another embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

30: 단품 패키지 31: 인너 리드30: Single piece package 31: Inner lead

32: 다이 패들 33: 반도체 칩32: die paddle 33: semiconductor chip

34: 금속 와이어 35: 봉지제34: metal wire 35: sealing agent

36: 접착제 40: ACF36: adhesive 40: ACF

41: 전도성 입자 50: 솔더 볼41: conductive particle 50: solder ball

Claims (3)

상부면 및 하부면에 패턴이 노출되며, ACF(Anisotropic Conductive Film)을 매개로 상하로 적층되는 다수의 단품 패키지; 및A plurality of single-piece packages having patterns exposed on the top and bottom surfaces thereof, stacked up and down via an anisotropic conductive film (ACF); And 최하면에 위치한 상기 단품 패키지의 하부면에 노출된 패턴 상에 부착되는 솔더 볼;을 포함하며,And a solder ball attached to a pattern exposed on a lower surface of the unit package located at a lowermost surface thereof. 상기 단품 패키지는, 외측 인너 리드가 내측 인너 리드에 수직하도록 상부로 휘어져 있는 리드 프레임의 다이 패들 상에 반도체 칩이 탑재되고, 상기 인너 리드가 패키지의 측면을 포함한 상부 및 하부면에 노출되도록 봉지제에 의해 밀봉된 것을 특징으로 하는 BGA 타입 스택 패키지.The single package may include an encapsulant such that a semiconductor chip is mounted on a die paddle of a lead frame having an outer inner lead perpendicular to an inner inner lead and exposed to the upper and lower surfaces including the side surface of the package. BGA type stack package, characterized in that sealed by. 제 1 항에 있어서,The method of claim 1, 상기 단품 패키지에 탑재되는 반도체 칩은 상기 다이 패들 상에 접착제를 매개로 페이스 업 방식으로 부착되며, The semiconductor chip mounted in the unit package is attached to the die paddle in a face-up manner via an adhesive, 상기 반도체 칩의 본딩패드와 상기 리드 프레임의 인너 리드는 금속 와이어에 의해 전기적으로 접속되는 것을 특징으로 하는 BGA 타입 스택 패키지.The bonding pad of the semiconductor chip and the inner lead of the lead frame are electrically connected by a metal wire. 제 1 항에 있어서,The method of claim 1, 상기 단품 패키지에 탑재되는 반도체 칩은 상기 다이 패들 상에 접착제를 매개로 페이스 다운 방식으로 부착되며,The semiconductor chip mounted in the unit package is attached to the die paddle by a face down method through an adhesive. 상기 반도체 칩의 본딩패드와 상기 리드 프레임의 인너 리드는 범프를 통해 전기적으로 접속되는 것을 특징으로 하는 BGA 타입 스택 패키지.And a bonding pad of the semiconductor chip and an inner lead of the lead frame are electrically connected through bumps.
KR1020050055718A 2005-06-27 Ball Grid Array type stack package KR20060136156A (en)

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* Cited by examiner, † Cited by third party
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KR20160041581A (en) * 2014-10-08 2016-04-18 앰코 테크놀로지 코리아 주식회사 Package on package and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160041581A (en) * 2014-10-08 2016-04-18 앰코 테크놀로지 코리아 주식회사 Package on package and method for manufacturing the same
US9633966B2 (en) 2014-10-08 2017-04-25 Amkor Technology, Inc. Stacked semiconductor package and manufacturing method thereof

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