KR20060126033A - Majority voter circuit of digital mode - Google Patents

Abstract

A majority vote circuit of a digital mode is provided to reduce current consumption and prevent a malfunction in a driving process by using the digital mode. A plurality of first determination units include four determination units in order to output first determination signals of 2 bits according to an inverting state of non-overlapping present data of 2 bits and previous data of 2 bits corresponding to the present data of 2 bits. A plurality of second determination units includes four determination units in order to receive the first determination signals and determine the number of inverted data. A plurality of third determination units include two determination units in order to receive output signals of the second determination units and determine the inverting states of the present data. A fourth determination unit receives output signals of the third determination units and generates an output signal when the number of inverted data of the present data exceeds a majority vote.

Description

Majority voter circuit of digital mode

1 shows a majority vote determination circuit according to the prior art;

2 and 3 show a majority vote determination circuit in accordance with the present invention.

4 shows another embodiment of the fourth judging means according to the present invention;

* Names of symbols for main parts of the drawings

210,220,230,240: first judging means 310,320,330,340: second judging means

410, 420: third judging means 500: fourth judging means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a majority vote determination circuit, and more particularly, to a digital majority vote determination circuit for determining whether a data signal switched to a plurality of signal lines is more than a majority.

In recent years, as the data transfer speed between semiconductor integrated circuits including memory devices increases, not only the switching current of the data increases but also the effective section of the data decreases due to noise of signal lines. To improve this, if the number of data to be switched is more than half, a method of reducing the number of data signal lines to be switched by transmitting the data to the opposite value can be used. At this time, a majority vote determination circuit for counting the number of signal lines to which data is switched is required.

1 is a view showing a majority vote determination circuit according to the prior art.

As shown in the drawing, the majority decision circuit according to the prior art detects a voltage difference caused by the number of NMOS transistors 101 and PMOS transistors 102 turned on in accordance with the number of signal lines to which data is switched. to be. In other words, a voltage difference is generated between 'node0' and 'node1' by the number of NMOS transistors 101 and PMOS transistors 102 that are turned on. Determine whether the number is more than half or less.

However, the conventional circuit consumes a large amount of current because current continuously flows through the plurality of NMOS transistors 101 and PMOS transistors 102. Further, the potentials of 'node0' and 'node1' have a potential between the power supply voltage VDD and the ground VSS, not the potential level of the power supply voltage VDD or the ground voltage VSS. Therefore, the NMOS transistor 101 and the PMOS transistor 102 used in the conventional circuit cause deterioration of the device due to hot carriers, as well as due to noise generated in 'node0' and 'node1'. There is a problem that may cause malfunction.

Accordingly, an object of the present invention is to provide a majority decision circuit using a digital method.

In order to achieve the object as described above, according to an aspect of the present invention, by receiving 8-bit current data (consisting of the upper 4-bit current data and the lower 4-bit current data), the logical level of the current data is compared with the previous data. A digital majority decision circuit for determining a case in which a majority is inverted by comparison: the circuit includes two bits of current data that are adjacent to each other of the eight bits of current data and corresponding two bits of the above data. Four first determining means for respectively outputting a two-bit first discriminating signal according to whether or not to invert the previous data; Four second judging means for receiving the first judging signals, respectively, and judging the number of inverted data among the two bits of the current data applied to each of the first judging means; Receiving an output signal of a pair of second determination means which are adjacent to each other of the second determination means and not duplicated, and whether the upper 4 bits of current data applied to the first determination means are reversed, and the current of the lower 4 bits. Two third determining means for determining whether or not to invert the data; And fourth determining means for receiving the output signal of the third determining means and generating an output signal when the number of data inverted from the 8-bit current data is more than half.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 and 3 are diagrams showing a majority decision circuit according to the present invention.

The majority decision circuit according to the present invention comprises four first determination means for receiving two bits of current data which are adjacent to each other among the upper four bits and the lower four bits of current data, and two bits of previous data corresponding thereto. (210-240); Four second determining means (310 to 340) for receiving the output signals of the first determining means (210 to 230) and determining the number of inverted data among the current data, respectively; Receiving the output signals of the second determination means (310 to 320), respectively, the third determination means (410, 420) and the third determination means (410, 420) for determining whether to invert the current 4-bit and lower 4-bit current data Thus, when the number of data inverted from the 8-bit current data is more than half, fourth determining means 500 for generating an output signal. Here, the plurality of first determination means 210 to 230, the second determination means 310 to 330, and the third determination means 410 and 420 have the same configuration and operation characteristics, respectively. Therefore, in the following description, only one component will be described in detail.

The first judging means 210 outputs the exclusive ora gates 211 and 212 and the exclusive ora gates 211 and 212 which receive a single bit of current data D0 and D1 and corresponding previous data D0_old and D1_old, respectively. vert0 and inverters 213 and 214 which generate inverted output signals vert0b and vert1b. Through this configuration, when the first determination means 210 is inverted by comparing the current data D0 and D1 with the previous data D0_old and D1_old, respectively, as shown in Table 1 below, the output of the high level is output. Output signals vert0 and vert1.

D0 _old D0 vert0 Inverted current data Number of 0 0 0 0 0 One One One One 0 One One One One 0 0

TABLE 1

The second judging means 310 comprises: end means 311 for receiving the output signals 'vert0b' and 'vert1b' and generating an output signal 'a0'; The NAND gate 312 receives the output signals' vert0 'and' vert1b ', the NAND gate 313 receives the output signals' vert0b' and 'vert1', and the output signal of the NAND gates 312 and 313 receives the output signal ' a NAND gate 314 generating a1 '; And an end unit 315 for receiving the output signals 'vert0' and 'vert1' and generating an output signal 'a2'. Through this configuration, the second judging means 310 determines how many values having a high level are among the output signals vert0 and vert1 of the first judging means 210. Therefore, the output signals a0 to a2 of the second determination means 310 indicate the number of inverted current data D0 and D1 as shown in Table 2 below. Here, the output signals b0 to b2, c0 to c2, d0 to d2 of the remaining second determination means 320 and 330 also have the same characteristics as the output signals a0 to a2 of the second determination means 310.

vert1 vert0 a0 a1 a2 The number of current data inverted 0 0 One 0 0 0 0 One 0 One 0 One One 0 0 One 0 One One One 0 0 One 2

TABLE 2

The third judging means 410 receives the output signals 'a0' and 'b0' and outputs a NAND gate 411 for generating the output signal 'e0b' and an inverted signal 'e0' with the output signal 'e0b'. Inverter 412; NAND gate 413 receiving output signals a0 and b2, NAND gate 414 receiving output signals a1 and b1, NAND gate receiving output signals a2 and b0 415 and a NAND gate 415 which receives an output signal of the NAND gates 413 to 415 and generates an output signal 'e2'; NAND gate 417 for receiving output signals a1 and b2, NAND gate 418 for receiving output signals a2 and b1, and output signals of NAND gates 417 and 418 for receiving an output signal a NAND gate 419 generating (e3); And a NAND gate 420 which receives the output signals 'a2' and 'b2' and generates an output signal 'e4b', and an inverter 421 which generates the inverted output signal 'e4' of the output signal 'e4b'. It is composed. Through this configuration, the third judging means 410 determines how many values having a high level are among the output signals vert0 to vert3 of the first judging means 210. Accordingly, the third judging means 410 determines the number of inverted data among the first four bits of current data D0 to D3 that are input first as shown in Table 4 below. Here, the output signals f0 to f4 of the remaining third determination means 420 have the same characteristics as the output signals e0 to e3 of the third determination means 410. Accordingly, the third judging means 420 determines the number of inverted data among the first four bits of current data D4 to D8 that are input first.

The number of current data inverted a0  + b0  = e0 0 a0  + b2  = e2 2 a1  + b1  = e2 2 a2  + b0  = e2 2 a1  + b2  = e3 3 a2  + b1  = e3 3 a2  + b2  = e4 4

TABLE 4

The fourth judging means 500 uses the output signals e0 to e4, f0 to f4 of the third judging means 410 and 420, and is high among the output signals vert0 to vert7 of the first judging means 210 to 240. FIG. It is determined whether the number of signals having the level is 5 or more, and when the number is 5 or more, the output signal 'over5' is generated. Specifically, the fourth judging means 500 does not require any combination of the output signals e0 to e4, f0 to f4 of the third judging means 410 and 420. That is, as shown in Table 5 below, a circuit may be implemented through a logical sum of a portion having a number of 5 or more.

e0 e1 e2 e3 e4 f0 0 One 2 3 4 f1 One 2 3 4 5 f2 2 3 4 5 6 f3 3 4 5 6 7 f4 4 5 6 7 8

In Table 5, the logical expression of the portion having the number of 5 or more is as follows.

over5  = / e0 ㆍ f4  + e2 ㆍ f3  + e3 ㆍ f2  + e3 ㆍ f3  + e4 ㆍ / f0

In addition, the fourth determination means 500 may be implemented through the logical sum of the portions having a number less than five in Table 5. The logic at this time is as follows, and the circuit according to the logic is shown in FIG.

over5  = / ( e0  + f4  + e1 ㆍ / f4  + e2 ㆍ f2  + / e4 ㆍ f1 )

As described above, the majority decision circuit according to the present invention can reduce the current consumption because there is no continuous current flow compared to the conventional analog method, and the problem of device degradation due to hot carriers It can also prevent and have greater immunity to noise.

 According to the configuration as described above of the present invention, by implementing the majority decision circuit digitally can reduce the current consumption, it is possible to prevent malfunction due to noise during driving.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

Claims (1)

In a digital majority decision circuit for receiving 8-bit current data (consisting of upper 4-bit current data and lower 4-bit current data) and determining when the logic level of the current data is inverted by more than half compared to previous data. , Four first bits each outputting two-bit first discrimination signals according to whether two bits of the current data that are adjacent to each other of the 8-bit current data and which are not duplicated and the corresponding 2-bit previous data are respectively inverted. Determination means; Four second judging means for receiving the first judging signals, respectively, and judging the number of inverted data among the two bits of the current data applied to each of the first judging means; Receiving an output signal of a pair of second determination means which are adjacent to each other of the second determination means and not duplicated, and whether the upper 4 bits of current data applied to the first determination means are reversed, and the current of the lower 4 bits. Two third determining means for determining whether or not to invert the data; And And a fourth determining means for receiving the output signal of the third determining means and generating an output signal when the number of data inverted from the 8-bit current data is more than half. .

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