KR20060115284A - Multilayer pcb and the manufacturing method thereof - Google Patents

Abstract

A multi-layered printed circuit board and a method for manufacturing the same are provided to increase a space efficiency of a mounted component by installing decoupling capacitors in a substrate. Plural capacitors are built in an intermediate layer of a multi-layered printed circuit board, and are connected in parallel to each other along a desired electrode pattern. A first electrode(825) forms a pattern corresponding to arrangement of the capacitors so that the first electrode is electrically connected to a first terminal of the capacitor. A second electrode(840) is isolated from the first electrode, and has a pattern corresponding to the arrangement of the capacitors to connect with a second terminal of the capacitor.

Description

Multilayer PCB and its manufacturing method

1 illustrates a power distribution circuit equivalent model of a multilayer wiring board having one decoupling capacitor.

2 is a diagram showing an equivalent power distribution circuit equivalent model of a multilayer wiring board having a plurality of decoupling capacitors according to an exemplary embodiment of the present invention.

3 shows the relationship between frequency and impedance in the circuit shown in FIG.

FIG. 4 is a diagram illustrating an equivalent model of a power distribution circuit of a multilayer wiring board in which a plurality of decoupling capacitors having different capacitance values according to a preferred embodiment of the present invention are divided into groups according to capacitance values.

5 shows the relationship between frequency and impedance for the circuit shown in FIG.

6 is a cross-sectional view of a multi-layered wiring board in which a plurality of decoupling capacitors having different capacitance values according to a preferred embodiment of the present invention are divided into groups according to capacitance values.

7 is a schematic diagram in which a group of a plurality of decoupling capacitors having different capacitance values according to a preferred embodiment of the present invention is stacked on a multilayer wiring board.

8 is a cross-sectional view of a multilayer wiring board incorporating a plurality of decoupling capacitors according to a preferred embodiment of the present invention.

9 to 11 illustrate a multilayer wiring board incorporating a plurality of decoupling capacitors according to a first embodiment of the present invention.

12 to 14 illustrate a multilayer wiring board incorporating a plurality of decoupling capacitors according to a second preferred embodiment of the present invention.

15 to 17 illustrate a multilayer wiring board incorporating a plurality of decoupling capacitors according to a third exemplary embodiment of the present invention.

18 is a graph showing a relationship between frequency and impedance of a plurality of decoupling capacitors connected in parallel according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

810: First digital device

820: first insulating layer

825: first electrode

830: a plurality of decoupling capacitors

840: second electrode

850: second insulating layer

860: second digital device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate and a method of manufacturing the same, and more particularly to a multilayer wiring substrate and a method of manufacturing the same.

Recently, as ubiquitous computing and digital convergence trends are accelerated, semiconductor integrated circuits are integrated enough to perform system functions on a single chip, signal processing speed is high, and low power is suitable for portable environment. In such an electronic product use environment, the importance of circuit design technology for securing a noise margin by lowering a signal-to-noise ratio is increasing. In order to meet the noise margin determined in the semiconductor integrated circuit at the module design stage, the main method is to minimize the parasitic inductance of the power distribution circuit in the module. This parasitic inductance interferes with the high instantaneous current supply required when digital devices in a semiconductor integrated circuit are placed under simultaneous switching conditions, and acts as a noise source by temporarily lowering the power supply voltage. In order to reduce the noise level, the decoupling capacitor can perform charge / discharge function of the charge in the main frequency band defined by the rising or falling rate of the clock signal, and stabilizes the voltage of the power supply stage by keeping it below the target impedance value. The importance of is getting very large.

However, when looking at the internal structure of the decoupling capacitor according to the prior art, it has a structure in which one capacitor is connected to each power stage pin of the integrated circuit, so the impedance reduction effect seen in the power stage of the integrated circuit is not large.

The present invention provides a multi-layered wiring board and a method of manufacturing the same, by embedding a plurality of decoupling capacitors connected in parallel in a substrate to increase the space efficiency of mounting components and to reduce the size of a system module.

In addition, the present invention provides a multi-layered wiring board and a method of manufacturing the same, by embedding a plurality of decoupling capacitors connected in parallel in a substrate to improve the electrical characteristics by optimizing the power distribution circuit in a given space.

The present invention also provides a system by grouping a plurality of decoupling capacitors by capacitance and embedding them in a matrix of various shapes, and connecting the terminals of the embedded capacitors to a power / grounding electrode having a predetermined pattern located at the top and bottom thereof. Provided are a multilayer wiring board capable of providing a stable voltage to a module and a method of manufacturing the same.

According to an aspect of the present invention, a plurality of capacitors embedded in an intermediate layer of a multi-layered wiring board and a plurality of capacitors connected in parallel according to a predetermined electrode pattern to form a pattern corresponding to the arrangement of the capacitors to be electrically connected to the first terminals of the capacitors. A multi-layered wiring board including a first electrode and a second electrode insulated from the first electrode and forming a pattern corresponding to the arrangement of the capacitor to be electrically connected to the second terminal of the capacitor can be provided.

Here, the plurality of capacitors may be arranged in a matrix form, the first electrode and the second electrode may be electrically connected to a power source and a ground, respectively, and the plurality of capacitors may each have the same or different capacitances.

According to another aspect of the present invention, the first insulating layer, the first electrode which is positioned on the first insulating layer and forms a predetermined pattern, is stacked on top of the first electrode and the first terminal is electrically connected to the first electrode. A plurality of capacitors arranged in correspondence with the pattern of the first electrode to be connected, the plurality of capacitors positioned on top of the capacitor, insulated from the first electrode, and forming a pattern corresponding to the arrangement of the capacitor to be electrically connected to the second terminal of the capacitor. A multi-layered wiring board including a second electrode and a second insulating layer positioned on the second electrode may be provided.

Here, the plurality of capacitors may be connected in parallel in a matrix form.

In addition, the multilayer wiring board may further include a copper-clad laminate in which a circuit pattern is formed on both surfaces of the multilayer wiring board in combination with the first electrode or the second electrode.

In addition, a plurality of via holes may be formed in the first insulating layer or the second insulating layer, and the first electrode and the second electrode may be electrically connected to a power source and a ground, respectively.

In addition, each of the plurality of capacitors may have the same or different capacitances, and a plurality of chips may be mounted on the first insulating layer or the second insulating layer.

According to another aspect of the invention, forming a first electrode having a predetermined pattern located on the intermediate layer of the multi-layered wiring substrate, the first electrode is located on top of the first electrode and is electrically connected to the first electrode Stacking a plurality of capacitors arranged in correspondence with the pattern of the first electrode, the second capacitor having a pattern corresponding to the arrangement of the capacitors so as to be insulated from the first electrode and electrically connected to the second terminal of the capacitor; A method of manufacturing a multilayer wiring board including forming two electrodes can be provided.

Here, the plurality of capacitors may be connected in parallel in a matrix form.

In addition, the first electrode and the second electrode may be electrically connected to the power source and the ground, respectively, and the plurality of capacitors may have the same or different capacitances.

According to another aspect of the invention, forming a first insulating layer, forming a first electrode on the first insulating layer and having a predetermined pattern, located on top of the first electrode and the first electrode Stacking a plurality of capacitors arranged in correspondence with the pattern of the first electrode such that the first terminal is electrically connected to the first terminal, wherein the plurality of capacitors are disposed on the capacitor and insulated from the first electrode, and electrically connected to the second terminal of the capacitor. A method of manufacturing a multilayer wiring board may be provided, including forming a second electrode having a pattern corresponding to an arrangement of capacitors, and forming a second insulating layer positioned on the second electrode.

Here, the plurality of capacitors may be connected in parallel in a matrix form, and the method for manufacturing a multilayer wiring board may further include forming a plurality of via holes in the first insulating layer or the second insulating layer.

In addition, the method for manufacturing a multi-layered wiring board may further include mounting a plurality of chips on the first insulating layer or the second insulating layer.

In addition, the method for manufacturing a multi-layered wiring board may further include stacking a copper-clad laminate in which a circuit pattern is formed on both surfaces and coupled to the first electrode or the second electrode.

Hereinafter, preferred embodiments of a multilayer wiring board and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. And duplicate description thereof will be omitted.

FIG. 1 is a diagram illustrating an equivalent model of a power distribution circuit of a multilayer wiring board generally having one decoupling capacitor. Referring to FIG. 1, the digital device 110, voltage regulator modules (VRM) 120, a first wiring 130, a second wiring 140, a decoupling capacitor 150, and a parasitic inductance 160. An equivalent model is shown for.

The digital element 110 is formed of a general chip and stores or processes signals as 0 and 1, and includes a memory (DRAM, Flash Memory, SRAM, etc.), an EPROM, an EEPROM, a CPU, and the like. Referring to FIG. 1, the digital element 110 is simply represented by an IC. The voltage regulator module 120 is connected to a mains power source, such as a computer, and utilizes transformers and solid-state circuitry to provide essentially unchanged smoothness over a suitable range of operating parameters (eg, temperature). One reference voltage is generated to supply power to the digital device 110. The digital element 110 and the voltage regulator module 120 are connected to each other by the first wiring 130 and the second wiring 140.

The decoupling capacitor 150 is embedded to lower the impedance of the power distribution circuit measured at the power stage of the integrated circuit to bypass power stage noise to ground or to supply the required current for a short time in the integrated circuit. The decoupling capacitor 150 may generally be a single capacitor or a multi-layer ceramic capacitor (MLCC) facing a pair of electrodes. The parasitic inductance 160 is generated by the internal structure of the decoupling capacitor 150 and the physical electrode length connecting it to the power stage.

Here, the decoupling capacitor 150 should have high capacitance and low parasitic inductance for the above-described electrical performance. According to the present invention, this effect can be obtained by arranging a plurality of decoupling capacitors 150 in a matrix form in a multilayer wiring substrate. Here, the matrix form refers to a shape in which a plurality of capacitors are arranged in parallel to form a specific pattern.

FIG. 2 is a diagram illustrating a power distribution circuit equivalent model of a multilayer wiring board having a plurality of decoupling capacitors according to a preferred embodiment of the present invention, and FIG. 3 illustrates a relationship between frequency and impedance in the circuit shown in FIG. Drawing.

Referring to FIG. 2, a plurality of decoupling capacitors 210 (1), 210 (2), 210 (3) and a plurality of parasitic inductances 220 (1), 220 (2) and 220 (3) are shown. . When a plurality of capacitors of the same capacitance value are connected in parallel in a matrix form, capacitance increases and parasitic inductance decreases. The overall impedance formed by the plurality of decoupling capacitors 210 (1), 210 (2), and 210 (3) is as follows.

(1)

(One)

Z _t is the overall impedance, j is the complex number, C is the capacitance, and L is the parasitic inductance. As a result, the capacitance increases, and as the parasitic inductance decreases, the overall impedance decreases.

Referring to FIG. 3, the characteristic of the 1-port impedance according to the number of decoupling capacitors of the same capacitance is schematically illustrated. When the multilayer wiring board includes a plurality of decoupling capacitors 320 than the case in which one decoupling capacitor is embedded 310, the impedance as a whole becomes smaller. Here, each graph has a bent portion, and this bent portion is formed at a resonance frequency of Z _t = 0 in Equation (1).

4 is a diagram illustrating a power distribution circuit equivalent model of a multilayer wiring board having a group of a plurality of decoupling capacitors having different capacitance values according to a preferred embodiment of the present invention, and FIG. 5 is a circuit diagram of FIG. 4. It is a figure which shows the relationship between a frequency and an impedance.

Referring to FIG. 4, the digital element 410, the voltage regulator module 420, the first wiring 430, the second wiring 440, the decoupling capacitors 450 (1), 450 (2), and 450 (3). , 450 (4)) and parasitic inductances 460 (1), 460 (2), 460 (3), and 460 (4), and a plurality of decoupling capacitors with different impedances are arranged with different patterns (470 (1), 470 (2), 470 (3), 470 (4)). Here, the plurality of decoupling capacitors 450 (1), 450 (2), 450 (3), and 450 (4) may be arranged by various methods. For example, a plurality of capacitors having the same capacitance are arranged in a matrix form, and the plurality of groups formed by connecting them in parallel are arranged to have different capacitances, or a plurality of capacitors having various capacitances are connected in parallel. Can form a plurality of groups. Such an arrangement of capacitors is designed to suit the electrical characteristics of the mounted IC, and various embodiments may be implemented by those skilled in the art.

Referring to FIG. 5, the characteristic 510 of impedance according to the number of decoupling capacitors of different capacities is schematically illustrated. Since the capacitance of the decoupling capacitors varies, synthetic impedance bends are formed at various resonance frequencies. Therefore, a multilayer wiring board incorporating decoupling capacitors having different capacities can have a small impedance less than a predetermined value seen at an integrated circuit power stage in a wide broadband frequency range.

6 is a cross-sectional view of a multilayer wiring substrate having a group of a plurality of decoupling capacitors having different capacitance values according to a preferred embodiment of the present invention. Referring to FIG. 6, a digital device 610, a voltage regulator module 620, a first insulating layer 630, a second insulating layer 640, and a plurality of decoupling capacitors 650 are shown. For convenience of explanation, only capacitors mainly affecting impedance are shown, and parasitic inductances are not shown.

The plurality of decoupling capacitors 650 are provided to combine the first insulating layer 630 and the second insulating layer 640 with electrodes. Accordingly, the plurality of decoupling capacitors 650 are coupled in parallel by the same electrode to form both ends insulated from each other, and both ends are respectively connected to power and ground by the voltage regulator module 620. The digital element 610 may be coupled to both ends of the plurality of decoupling capacitors 650 to receive a stable voltage. In addition, when a plurality of digital elements 610 are mounted on a multilayer wiring board, a low-speed signal processing integrated element (low speed digital element) is directly electrically connected to a position where a decoupling capacitor having a large parasitic inductance is embedded. The signal processing integrated devices (high speed digital devices) can be electrically connected directly to the location where the decoupling capacitors with low parasitic inductances are embedded so that the digital devices can be effectively affected by the composite impedances of the embedded capacitors. .

FIG. 7 is a schematic diagram in which groups of a plurality of decoupling capacitors having different capacitance values according to a preferred embodiment of the present invention are stacked on a multilayer wiring board to form a predetermined pattern. Referring to FIG. 7, groups of a plurality of decoupling capacitors 720 (1), 720 (2), 720 (3), and 720 (4) forming a specific pattern 720 and a corresponding patterned electrode 710 is shown.

Here, the groups 720 (1), 720 (2), 720 (3), and 720 (4) of the plurality of decoupling capacitors are illustrated in a manner in which capacitors having the same or different capacities are arranged differently. The capacity of each group may be the same or different from each other, and the shapes arranged differently are indicated by patterns. In addition, the electrode 710 is formed to correspond to the pattern formed by the groups 720 (1), 720 (2), 720 (3), and 720 (4) of the plurality of decoupling capacitors. That is, the electrodes (so that both ends formed in the groups 720 (1), 720 (2), 720 (3), and 720 (4) of the plurality of decoupling capacitors arranged and arranged in parallel may be connected to the power source and the ground, respectively) A pattern is formed at 710. Such a pattern may be generated in various ways by the shape of the groups 720 (1), 720 (2), 720 (3), 720 (4) of the plurality of decoupling capacitors.

8 is a cross-sectional view of a multilayer wiring board including a plurality of decoupling capacitors according to an exemplary embodiment of the present invention. Referring to FIG. 8, a first digital element 810, a first electrode pad 813 of a first digital element, a second electrode pad 815 of a first digital element, a first insulating layer 820, and a first The electrode 825, the decoupling capacitor 830, the second electrode 840, the second insulating layer 850, the second digital element 860, the first electrode pad 863 of the second digital element, and the first digital The second electrode pad 865 of the device is shown. The first insulating layer 820 and / or the second insulating layer 850 may be a resin coated copper foil (RCC). The decoupling capacitor 830 is embedded between the power and ground layers of the multi-layered wiring board. Specifically, the decoupling capacitor 830 is coupled to the first electrode 825 at the upper part and serves to stabilize the voltage between the power and the ground. Coupled with the two electrodes 840. In addition, a copper clad lamination (CCL) (not shown) may be deposited at a predetermined position between the first insulating layer 820 and the second insulating layer 850. The first electrode 825 and the second electrode 840 are insulated from each other, and a pattern corresponding to the arrangement of the decoupling capacitor 830 is formed to be electrically connected to different ends of the decoupling capacitor 830, respectively. Therefore, the first digital device 810 is connected to the first electrode 825 through the first electrode pad 813, and is connected to the second electrode 840 through the second electrode pad 815. In addition, the second digital device 860 is connected to the second electrode 840 through the first electrode pad 863, and is connected to the first electrode 825 through the second electrode pad 865.

In addition, a multilayer wiring board is generally manufactured by various methods such as a batch lamination method and a build-up method. The multilayer wiring board is formed by screen printing, electroless plating, or electroplating on the upper and lower sides of the insulating layer, and then performs etching or the like to form electrodes, and then prints resin on the upper and lower sides of the insulating layer. Via holes and through holes are formed, and an electrode is formed through a process such as etching after forming a plating layer electrically connected to the resin, via holes, and through holes using electroless plating or electrolytic plating. Thereafter, the resin, the via hole and the through hole may be additionally formed as necessary.

In the above description, an equivalent model or a cross-sectional view of a multilayer wiring board and a method of manufacturing the same has been described. Hereinafter, a multilayer wiring board and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings. Shall be. Embodiments according to the present invention are largely divided into three, first, a method for embedding the decoupling capacitor in the single-sided multilayer wiring board, second, a method for embedding the decoupling capacitor in the double-sided multilayer wiring board, third, devia by forming a via hole in the electrode It is divided into a method of connecting a capacitor and a digital device. It demonstrates in order below.

9 to 11 are diagrams illustrating a multilayer wiring board in which a plurality of decoupling capacitors are incorporated in a single-sided multilayer wiring board according to a first embodiment of the present invention.

9, the digital device 910, the first insulating layer 920, the first electrodes 930 (1) and 930 (2), the plurality of decoupling capacitors 940, the second electrode 950, and the like. Second insulating layer 960 is shown. The digital device 910 is connected to the second electrode 950 by using a via hole or the like, and is mounted on one surface of the multilayer wiring board. Referring to FIGS. 10 and 11, patterns of the first electrodes 930 (1) and 930 (2) and the second electrode 950 viewed from above of the multilayer wiring board are illustrated. In order to couple the plurality of decoupling capacitors 940 in parallel, the first electrodes 930 (1) and 930 (2) are connected to one end of the plurality of decoupling capacitors 940 and are connected to a power terminal or a ground. In addition, the second electrode 950 is connected to the other end where the first electrodes 930 (1) and 930 (2) are not connected to the plurality of decoupling capacitors 940, and the first electrodes 930 (1) and 930. (2)) is connected to an unconnected ground or power stage. The capacitance formed by the planes of the first electrodes 930 (1), 930 (2) and the second electrode 950 is small because the dielectric constant of the interplanar dielectric material is not high (for example, tens of pF). Accordingly, since the first electrodes 930 (1), 930 (2), and the second electrode 950 cause high impedance due to the generation of structural resonance, the plurality of decoupling capacitors 940 connected in parallel and having a high capacitance are connected. The power can be stabilized by interposing between the first electrodes 930 (1), 930 (2) and the second electrode 950.

12 to 14 illustrate a multilayer wiring board in which a plurality of decoupling capacitors are embedded in a double-sided multilayer wiring board according to a second exemplary embodiment of the present invention. Referring to FIG. 12, the upper digital device 1210, the first insulating layer 1220, the first electrode 1230, the plurality of decoupling capacitors 1240, the second electrode 1250, and the second insulating layer ( 1260 and bottom digital device 1270 are shown. The second embodiment differs from the first embodiment described above in that a digital element is mounted on both sides of the multilayer wiring board, and shows an example of a specific pattern generated by groups of the plurality of decoupling capacitors 1240.

Referring to FIGS. 13 and 14, the pattern of the first electrode 1230 and the second electrode 1250 and the plurality of decoupling capacitors 1240 viewed from the top of the multilayer wiring board are illustrated.

The first electrode 1230 and the second electrode 1250 are each electrically connected to different ends of the plurality of decoupling capacitors 1240 and correspond to the arrangement of the plurality of decoupling capacitors 1240 formed to be suitable for the system module configuration. A pattern is formed. In addition, the first electrode 1230 and the second electrode 1250 are connected to ground and a power terminal, respectively. Here, a pattern is formed in the first electrode 1230 and the second electrode 1250 such that there are no isolated electrode regions.

15 to 17 are diagrams illustrating multilayer wiring boards in which via holes are formed in an electrode according to a third exemplary embodiment of the present invention and in which a plurality of decoupling capacitors are embedded. Referring to FIG. 15, the digital element 1510, the first insulating layer 1520, the first electrode 1530, the plurality of decoupling capacitors 1540, the second electrode 1550, and the second insulating layer 1560 are formed. Is shown. The third embodiment differs from the above-described first embodiment in that via holes or through holes are formed in the first electrode 1530 and / or the second electrode 1550, so that a convenient side of the system module is provided. to be.

16 and 17, the pattern of the first electrode 1530 and the second electrode 1550 and the plurality of decoupling capacitors 1540 viewed from the top of the multilayer wiring board are illustrated. 15 is a cross-sectional view formed by the cutting lines K-K 'shown in FIGS. 16 and 17. The first electrode 1530 and the second electrode 1550 are each electrically connected to different ends of the plurality of decoupling capacitors 1540 and correspond to the arrangement of the plurality of decoupling capacitors 1540 formed to be suitable for the system module configuration. A pattern is formed. Via holes may be formed in the first electrode 1530 and the second electrode 1550 to allow signal lines to pass through empty spaces formed between the plurality of decoupling capacitors 1540. In addition, the first electrode 1530 and the second electrode 1550 are connected to ground and a power terminal, respectively. Here, a pattern is formed on the first electrode 1530 and the second electrode 1550 such that there are no isolated electrode regions.

18 is a graph illustrating a relationship between frequency and impedance of a plurality of decoupling capacitors connected in parallel calculated using an electromagnetic simulator according to a preferred embodiment of the present invention. Each graph is a graph produced by five 10 nF, 1 nF, 100 pF, 10 pF capacitors, and a group of capacitors arranged all of these capacitors, respectively. When all capacitors are arranged in parallel, a low impedance is formed over the broadband. In addition, the fluctuation range of the impedance is small, so that a stable voltage can be maintained.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the multilayer wiring board and the manufacturing method thereof according to the present invention can reduce the size of the system module by increasing a space efficiency of the mounting component by embedding a plurality of decoupling capacitors in the substrate.

In addition, the multilayer wiring board and the method of manufacturing the same according to the present invention may improve electrical characteristics by embedding a plurality of decoupling capacitors in a substrate to optimize a power distribution circuit in a given space.

In addition, the multilayer wiring board and the method of manufacturing the same according to the present invention group a plurality of decoupling capacitors by capacitance value and embed them in a matrix of various shapes, and each terminal of the embedded capacitor has a predetermined pattern located at the upper and lower parts thereof. The connection to the power / ground electrode can provide a stable voltage to the system module.

Claims (23)

In the multilayer wiring board, A plurality of capacitors embedded in the middle layer of the multilayer wiring substrate and connected in parallel according to a predetermined electrode pattern; A first electrode forming a pattern corresponding to the arrangement of the capacitor to be electrically connected to the first terminal of the capacitor; And And a second electrode insulated from the first electrode and forming a pattern corresponding to the arrangement of the capacitor to be electrically connected to the second terminal of the capacitor. The method of claim 1, The plurality of capacitors are arranged in a matrix form a multi-layer wiring board. The method of claim 1, And the first electrode and the second electrode are electrically connected to a power supply and a ground, respectively. The method of claim 1, And a plurality of capacitors each having the same capacitance as each other. The method of claim 1, And a plurality of capacitors, each having a different capacitance from each other. A first insulating layer; A first electrode on the first insulating layer and forming a predetermined pattern; A plurality of capacitors stacked on the first electrode and arranged in correspondence with the pattern of the first electrode such that a first terminal is electrically connected to the first electrode; A second electrode positioned over the capacitor and insulated from the first electrode, the second electrode forming a pattern corresponding to the arrangement of the capacitor to be electrically connected to the second terminal of the capacitor; And And a second insulating layer disposed on the second electrode. The method of claim 6, The plurality of capacitors are multi-layered wiring board connected in parallel in the form of a matrix. The method of claim 6, The multilayer wiring board further comprises a copper-clad laminate plate coupled to the first electrode or the second electrode, the circuit pattern is formed on both sides. The method of claim 6, The multilayer wiring board having a plurality of via holes formed in the first insulating layer or the second insulating layer. The method of claim 6, And the first electrode and the second electrode are electrically connected to a power supply and a ground, respectively. The method of claim 6, Each of the plurality of capacitors is a multi-layer wiring board with the same capacitance. The method of claim 6, Each of the plurality of capacitors has a capacitance different from each other. The method of claim 6, And a plurality of chips mounted on the first insulating layer or the second insulating layer. In the multilayer wiring board manufacturing method, Forming a first electrode on an intermediate layer of the multilayer wiring substrate and having a predetermined pattern; Stacking a plurality of capacitors positioned on the first electrode and arranged in correspondence with the pattern of the first electrode such that a first terminal is electrically connected to the first electrode; And Forming a second electrode positioned on the capacitor and insulated from the first electrode and electrically connected to the second terminal of the capacitor, the second electrode having a pattern corresponding to the arrangement of the capacitors; Way. The method of claim 14, And a plurality of capacitors are connected in parallel in a matrix form. The method of claim 14, And the first electrode and the second electrode are electrically connected to a power supply and a ground, respectively. The method of claim 14, And a plurality of capacitors each having the same capacitance as each other. The method of claim 14, And a plurality of capacitors each having a different capacitance from each other. Forming a first insulating layer; Forming a first electrode on the first insulating layer and having a predetermined pattern; Stacking a plurality of capacitors positioned on the first electrode and arranged in correspondence with the pattern of the first electrode such that a first terminal is electrically connected to the first electrode; Forming a second electrode positioned over the capacitor and insulated from the first electrode, the second electrode having a pattern corresponding to the arrangement of the capacitor to be electrically connected to the second terminal of the capacitor; And And forming a second insulating layer on the second electrode. The method of claim 19, And a plurality of capacitors are connected in parallel in a matrix form. The method of claim 19, The method of claim 1, further comprising forming a plurality of via holes in the first insulating layer or the second insulating layer. The method of claim 19, And mounting a plurality of chips in the first insulating layer or the second insulating layer. The method of claim 19, A method of manufacturing a multilayer wiring board further comprising the step of laminating a copper foil laminated plate which is bonded to the first electrode or the second electrode and the circuit pattern is formed on both surfaces.

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