KR20060113969A - Capacitor - Google Patents

Abstract

A method of creating a capacitor in an integrated circuit. According to a basic version of the invention the capacitor uses intensive fringing fields to create a capacitance. This is achieved by creating a capacitor with vertical overlapping conducting electrodes between two planes of the integrated circuit, instead of plates parallel to the planes. A capacitor according to the invention can additionally comprise horizontal, i.e. parallel plates. A capacitor according the method is also disclosed.

Description

Capacitor {CAPACITOR}

FIELD OF THE INVENTION The present invention relates to capacitors, in particular capacitors, resonators, and filters in sub-micrometer COMS technology integrated circuits, and more particularly, to a method for producing high capacitance per unit area of a silicon chip, and to capacitors, resonators, filters, And a transmission line.

There is a need to be able to use integrated circuits for high frequency circuits in the microwave range and beyond. The need to increase speed / frequency requires a size feature that reduces the current gate length to less than 1.0 GHz in COMS and related technologies. The result is a rapid increase in price per unit area of silicon chips, ie $ / mm ² .

Attempts have been made to use high integration density, low cost standard silicon technologies such as CMOS and bipolar. This silicon technology has a low resistivity of less than 10-20 Ohm cm. In order to use such silicon in the manufacture of microwave integrated circuits, such as high speed digital integrated circuits, there is a high loss in passive components connected with low resistivity silicon substrates. Passive components include, for example, transmission lines, interconnects, inductors, and capacitors.

Typically, two different types of on-chip capacitors have been used in standard silicon technology. Metal-Insulator-Metal (MIM) of the first type used in standard silicon integrated circuits has high loss and low self-resonance frequency due to the small thickness and low conductivity of the capacitor plate. MIM capacitors can also be argued as having reliability issues. The second type of metal-insulator-metal-insulator-metal (MIMIM) capacitor has similar drawbacks as above. There seems to be room for improvement in how capacitors are implemented in integrated circuits such as COMS or bipolar, particularly low resistivity integrated circuits.

It is an object of the present invention to define a method for producing a capacitor which overcomes the above mentioned drawbacks and to define the capacitor.

Another object of the present invention is to define a method for producing a capacitor requiring a minimum unit area and to define the capacitor.

Another object of the present invention is to define a method for producing passive components such as transmission lines, and to specify passive components such as transmission lines with low losses.

The above mentioned object is achieved by a method of producing a capacitor in an integrated circuit according to the invention. According to the basic form of the invention, the capacitor uses a strong fringing field to generate capacitance. This is accomplished by creating a capacitor with a vertical overlapping conductive electrode between the two planes of the integrated circuit, instead of a plate parallel to the plane. The capacitor according to the invention may further comprise a horizontal, ie parallel, plate. Also disclosed is a capacitor according to the method.

The above mentioned object is also achieved by a method of arranging on-chip capacitors. The on-chip capacitor creates capacitance between the first conductive junction of the first plane of the chip and the second conductive junction of the second plane of the chip. According to the invention, the method comprises producing at least one first type of conducting extension from the first conduction point to the third plane in the second plane direction. The first type of extension always starts in the first plane and extends in the second plane direction. The method further includes generating at least one second type of conductive extension from the second conductive connection point to the fourth plane in the first plane direction. The second type of extension always starts in the second plane and extends in the first plane direction. The fourth plane is located between the first plane and the second plane. The third plane is located between the fourth plane and the second plane. The first conductive extension is separated from the second conductive extension by a dielectric that causes an electric field to be created between the extensions. Thus, the conductive extensions overlap and are appropriately close to each other, but are spaced apart so that there is no flash-over or failure of the dielectric. It is suitable for the first type and the second type of extension to basically extend parallel to the perpendicular of the plane in which they extend.

The method suitably further comprises generating a plurality of first and / or second types of conductive extensions. In this case, the first and second conduction points, which can be applied respectively, take the form of a conducting region. Sometimes the first plane is one side of the first metal layer and the second plane is one side of the second metal layer, wherein the first and second metal layers are different metal layers. In some forms, the third and fourth planes are different sides of the third metal layer. In another form, the third plane is one side of the third metal layer and the fourth plane is one side of the fourth metal layer, wherein the third and fourth metal layers are different metal layers.

In some form of the method, the method starts the first and / or second type of conductive extension or extensions in one metal layer, and thus the first and / or second type of conductive extension or extension in one metal layer. Terminating the parts. In this form, it may often be appropriate for the method to further include extending the first type of conductive extension or extensions through at least one other metal layer.

To increase the capacitance of the capacitor, the method further suitably includes extending the first conductive connection point in the first plane of the chip to include the conductive plate, and / or the second plane of the chip to include the conductive plate. And expanding the second conductive connection point in the.

Conductive extensions are suitably made as vias of solid or hollow.

One or more features of the different methods described above according to the invention may be combined in any desired manner unless the features conflict.

The above mentioned object is also achieved by a method of producing an on-chip resonant circuit. The method includes generating a resonant circuit by arranging one or more capacitors and at least one other passive component in accordance with any of the methods described above.

The above mentioned object is also achieved by a method of creating an on-chip transmission line. The method includes arranging one or more capacitors in a transmission line according to any of the methods described above.

The above mentioned object is also achieved according to the invention by an on-chip capacitor having a capacitance between the first conductive connection point of the first plane of the chip and the second conductive connection point of the second plane of the chip. According to the invention, the on-chip capacitor comprises at least one first type of conductive extension from the first conduction point to the third plane in the second plane direction. The first type of extension always starts in the first plane and extends in the second plane direction. The on-chip capacitor also includes at least one second type of conductive extension from the second conductive connection point to the fourth plane in the first plane direction. The second type of extension always starts in the second plane and extends in the first plane direction. The fourth plane is located between the first plane and the second plane. The third plane is located between the fourth plane and the second plane. The first conductive extension is separated from the second conductive extension by a dielectric that allows an electric field to be created between the extensions. It is suitable for the first type of extension and the second type of extension to basically extend parallel to the perpendicular of the plane in which they extend.

The on-chip capacitor may suitably further comprise a plurality of first and / or second types of conductive extensions. In this case, the first and second types of conducting points, which can be applied respectively, take the form of conducting regions. The first plane may be one side of the first metal layer, and the second plane may be one side of the second metal layer, wherein the first and second metal layers are different metal layers. The third and fourth planes may in some embodiments be different sides of the third metal layer. In another embodiment, the third plane may be one side of the third metal layer and the fourth plane may be one side of the fourth metal layer, wherein the third and fourth metal layers are different metal layers.

The first and / or second type of conductive extension or extensions may, in some embodiments, start with one metal layer as appropriate and end with one metal layer. In any of the above embodiments, the first and / or second type of conductive extension or extensions extends properly through at least one additional metal layer.

In some embodiments, the first conductive connection point of the first plane of the chip may comprise a conductive plate. In the same or another embodiment as above, the second conductive connection point of the second plane of the chip may comprise a conductive plate.

Conductive extensions are suitable for solid or cavity vias.

The features of the different embodiments described above of the on-chip capacitor according to the invention can be combined in any desired manner as long as a collision does not occur.

The above-mentioned object is also achieved by an on-chip resonant circuit in accordance with the present invention, the resonant circuit comprising one or more capacitors according to any of the embodiments described above.

The above-mentioned object is also achieved by an on-chip transmission line according to the invention, which comprises one or more capacitors according to any of the embodiments described above.

The above-mentioned object is also achieved by a transmission line based component such as a resonator, matching network, or power divider, the transmission line based component comprising a transmission line according to any of the embodiments described above.

By providing a method for producing on-chip capacitors, transmission lines, and other passive components in accordance with the present invention, and embodiments thereof, a number of advantages over conventional methods and components are obtained. The primary object of the present invention is to propose a new design of high density and Q-factor capacitors, resonators, and associated microwave components that can be compatible with sub-micrometer COMS and bipolar silicon processes. According to the present invention, this is made possible by basically increasing the capacitance per unit area by using vias in a multilayer silicon process to create a strong edge region between the vias and additional plates of capacitors. Other advantages of the present invention will become apparent from the detailed description.

The present invention will now be described in more detail with reference to the following drawings for purposes of explanation and not limitation.

1A illustrates an example of a plate capacitor.

1B illustrates a metal-insulator-metal (MIM) integrated plate capacitor.

1C illustrates a metal-insulator-metal-insulator-metal (MIMIM) integrated plate capacitor.

2 is a top view of an interdigitated capacitor layout.

3A is a side view of a basic embodiment of a capacitor structure according to the present invention.

3B is a side view of a preferred basic embodiment of a capacitor structure according to the present invention.

3C is a cross sectional view through A-A of FIG. 3B of a capacitor structure according to the present invention;

3d is a three dimensional view of the preferred basic embodiment of a capacitor structure according to the invention.

3E is a cross-sectional view of an optional form of conductive extension.

4A is a side view of a preferred basic capacitor structure in accordance with the present invention in a three metal layer chip structure.

4B is a cross-sectional view through the intermediate metal layer of FIG. 4A.

4c is a side view of a capacitor structure according to the present invention in a four metal layer chip structure;

5A is a side view of a more complex capacitor structure in accordance with the present invention in a four metal layer chip structure.

5B-5D are cross-sectional views through one of the intermediate metal layers of FIG. 5A, showing examples of different layouts of conductive extensions.

6A-6B illustrate another cross-sectional view of an example of a different layout of a conductive extension.

7a-7b show examples of resonant circuits of the structure according to the invention;

8 is a view showing a transmission line structure according to the present invention.

In order to clarify the method and the apparatus according to the invention, examples of its use will be described with reference to FIGS.

1A shows an example of a plate capacitor that includes a first plate 110 and a second plate 120. The plates 110 and 120 are separated 150 by a set distance. The space between the plates 110, 120 includes a dielectric 100, which may be a gas, vacuum, or solid material, such as air. The capacitance between the plates is provided by the area of the plates 110, 120, the distance 150 between the plates 110, 120, and the dielectric 100 in the space between the plates 110, 120.

As mentioned above, there are a number of methods for generating on-chip capacitance. 1B illustrates a metal-insulator-metal (MIM) integrated plate capacitor. An on-chip capacitor is produced in the silicon wafer 115, on which a plurality of metal layers 110, 120, 121 are formed with a dielectric 100 therebetween. Capacitors of the MIM type comprise two particularly thinly manufactured metal plates 171, 172 with a capacitance created therebetween. Each of the given metal plates 171, 172 includes vias 161, 162 to corresponding general metal layer portions 121, 122. Another type of on-chip capacitor is shown in FIG. 1C. 1C illustrates a metal-insulator-metal-insulator-metal (MIMIM) integrated plate capacitor. MIMIM integrated plate capacitors do not require special metal plates as in MIM. Capacitors of the MIMIM type generally use metal layers 111, 112, 121, 122, 131, and 132 to create a plate with dielectric 100 therebetween over silicon wafer 105. MIMIM also has the problem of requiring a relatively large unit area for the desired capacitance.

Instead of arranging capacitor plates on top of each other, completely different types of capacitors have been proposed that are arranged adjacent to the same plane. 2 shows a top view of the interdigitated capacitor layout of such a capacitor, which includes a first portion 211 of the metal layer and a second portion 212 of the same metal layer as above. Capacitance is obtained, in part, by the thickness of the plate / finger creating a small plate in close proximity to each other, and the edge region between the plate / finger. This type of capacitor has the advantage that it can be formed in one single metal layer, but requires a relatively large surface area.

The present invention produces optimum capacitance in the limited surface area. This is achieved by using the depth of the structure in which the capacitor is created to create a surface in which an electric field can be created. 3A shows a side view of a basic embodiment of a capacitor structure according to the present invention. The basic embodiment includes a first metal layer 310 at least partially creating a first conduction point in the first plane, and a second metal layer 320 at least partially creating a second conduction point in the second plane. It is shown in a simple chip structure. The first metal layer 310 and the second metal layer 320 are separated by the dielectric 300. According to the invention, the capacitor structure comprises at least one first type of conductive extension 365 extending in a second plane direction from the first conduction point 320, and a first plane from the second conduction point 310. At least one second type of conductive extension 366 extending in a direction. Conductive extensions 365 and 366 are separated with distance 352 and overlap by distance 354 along the extension. In accordance with the present invention, capacitance is created between the conductive extensions 365 and 366 extending substantially perpendicular to the plane of the metal layers 310 and 320. The larger the cross-sectional area, the longer the overlapping length along the extension, the closer the extension is to each other, the higher the resulting capacitance seen between the first and second conduction points.

Instead of having only the first and second conduction points 310, 320 it is advantageous to allow the metal layer to form a conductive plate which contributes to the capacitance. FIG. 3B shows a side view of a preferred basic embodiment of a capacitor structure according to the present invention having additional capacitor plates / conductive plates 315, 325 in addition to conductive extensions 365, 366. FIG. The capacitance obtained will depend on the dielectric 300, the actual area of the capacitor plate, and the actual distance therebetween, as described above. In accordance with the present invention, conductive extensions 365 and 366 create a capacitor plate that extends into the chip structure. The actual capacitor plate area obtained from the conductive extensions 365 and 366 will depend on the geometry of the extensions and the amount of overlap 354. As can be seen in FIG. 3B, the total capacitance obtained is mainly due to the capacitive coupling 391 between the first conductive plate 315 and the second conductive plate 325, and the second type of conductive extension 366. Capacitive coupling 393 between first conductive plate 315, capacitive coupling 394 between first type of conductive extension 365 and second type of conductive extension 366, and first type Is obtained by a combination of capacitive coupling 395 between conductive extension 365 and second conductive plate 325.

3C illustrates a cross-sectional view across AA of FIG. 3B of a capacitor structure in accordance with the present invention, wherein a first example of first 365 and second 366 conductive extensions is shown above the first conductive plate 315. It is. The invention is not dependent or limited to any type of cross section or cross section, and the first and second types of conductive extensions need not have the same type of cross section or cross section. FIG. 3D is a three-dimensional view of a preferred basic embodiment of a capacitor structure according to the present invention having a first 315 and a second 325 conductive plate, a first extension 365 and a second extension 366. To show. 3E illustrates a cross-sectional view of optional extensions of conductive extensions 365 and 366 on the first 315 conductive plate.

Manufacturing a conductive extension between two metal layers of an integrated circuit is difficult and expensive, and generally not a preferred method of practicing the present invention. A preferred method of making the present invention is to make the conductive extension in the form of a via. The vias may be filled, ie in the form of solids or cavities such as conductive tubes. 4A shows a side view of a preferred basic capacitor structure according to the present invention in a three metal layer chip structure. This compact structure includes a first metal layer 416 including the first conductive plate, a portion serving as a termination of the vias of the second metal layers 426 and 427, and a third metal layer 436 including the second conductive plate. Between the dielectric 400 is included. Thus, at least some of the first and second types of conductive extensions are vias between the metal layers. In this example, the first type of conductive extension includes a via 465 between the first metal layer 416 and the second metal layer 426, and a portion of the second metal layer 426 where the via 465 terminates. Done. The second type of conductive extension will include a via 466 between the second metal layer 426 and the third metal layer 436, and a portion of the second metal layer 427 where the via 466 terminates. In this example, the capacitance is primarily a capacitive coupling 491 between the first conductive plate 416 and the second conductive plate 436, the second metal layer 427 and the first conductive plate 416 of the second conductive extension. Capacitive coupling 493 between), in the overlap region, in this example the capacitive between the first conductive extension and the second conductive extension in the second metal layer in which the vias of the first and second conductive Bond 494, and a capacitive bond 495 between second metal plate 426 of first conductive extension and second conductive plate 436.

FIG. 4B shows a cross section through the intermediate metal layer of FIG. 4A, in which the second metal layer portion 426 of the first conductive extension, the second metal layer portion 427 of the second conductive extension, the first conductive extension Via portion 465 and via portion 466 of the second conductive extension are shown.

The present invention is not limited to the number of metal layers included in the chip structure. 4c shows a side view of a capacitor structure according to the invention in a four metal layer chip structure. As before, the structure includes a first metal layer 418, an intermetallic layer, in this example second 428, 429 and third metal layers, a final fourth metal layer 448, and a dielectric 400 between the metal layers. It includes. The first metal layer 418 and the fourth metal layer 448, the last metal layer, also advantageously include a conductive plate for adding capacitance in addition to providing a conduction point for the capacitor connection. In this example, the first type of conductive extension is the portion of the first via 465 between the first metal layer 418 and the second metal layer 428, the portion of the second metal layer 428 where the first via 465 terminates. , The second via 467 between the second metal layer 428 and the third metal layer 438, and the portion of the third metal layer 438 where the second via 467 ends. The second type of conductive extension is the first via 466 between the third metal layer 439 and the fourth metal layer 448, the portion of the third metal layer 439 where the first via 466 terminates, the second metal layer. A second via 468 between the 429 and the third metal layer 439 and a portion of the fourth metal layer 439 where the second via 468 terminates. By inserting another metal layer, the overlap of the first and second types of conductive extensions increases to include the second vias 467 and 468 as well as the second 428 and 429 and third 438 and 439 metal layers. . This drastically increases the efficiency of the capacitor.

As described above, the present invention is not limited to any number of conductive extensions of the first and / or second type. Figure 5a shows a side view of a more complex capacitor structure according to the present invention in four metal layer chip structures. The structure is similar to the structure of FIG. 4C with four metal layers 511, 521, 522, 531, 532, 541, vias 561, 562, 572, 573, and a filled dielectric 500. However, the structure shown in FIG. 5A uses a plurality of first and second types of conductive extensions.

Depending on where the side view of FIG. 5A is located, a number of different capacitor layouts can be represented. The first and second types of conductive extensions are uniformly distributed, arranged in rows, and arranged in a circle or any desired shape. Differences in layout may arise, for example, due to screening purposes or space constraints. 5B-5D show cross sections through one of the intermediate metal layers of FIG. 5A, showing different layout examples of conductive extensions. In order to correctly identify the layout, FIGS. 5B-5D show a first via portion of the first type of conductive extension 561, the corresponding end serving as an intermediate termination for the via (s) of the first type of conductive extension. Part of the second metal layer 521, and further a second via portion 572 of the second type of conductive extension, and a corresponding second metal layer 522 that serves as a termination for the via (s) of the second type of conductive extension. ) Part.

6A and 6B show another cross sectional view of a different layout example of a conductive extension, where, as before, the first via portion 661 of the first type of conductive extension, the via (s) of the first type of conductive extension; A corresponding second metal layer 621 portion is shown that serves as an intermediate termination for the second type of conductive extension of the second type of conductive extension, and the via (s) of the second type of conductive extension. A corresponding portion of the second metal layer 622 is shown acting as a termination for

According to the invention, portions of the structure can be used to make other passive and active devices. 7A and 7B show an example of a resonant circuit of the structure according to the present invention. Basically, an RL segment 781 is added to the second metal layer connected to the first metal layer 711 by the first via 761. The RL segment 781 is also connected to the fourth metal layer 741 through the first via 773, the portion 731 of the third metal layer, and the second via 722. The other portions of the second 722 and third 732 metal layers form terminations or intermediate terminations for the vias for forming the first and second types of conductive extensions.

The capacitive structure according to the invention can be advantageously used for transmission lines because of its ability to be distributed. The characteristic impedance of the transmission line, or impedance per unit length, is directly proportional to the characteristic inductance and inversely proportional to the characteristic capacitance. This means that the increase in the characteristic inductance increases the characteristic impedance, and the increase in the characteristic capacitance decreases the characteristic impedance. The electrical length is directly proportional to the characteristic inductance and directly proportional to the characteristic capacitance. This means that the increase in the characteristic inductance increases the electric length, and the increase in the characteristic capacitance also increases the electric length. Thus, the function for also controlling the characteristic capacitance of the transmission line is a powerful means for forming the transmission line with the predetermined characteristic. 8 shows a first conductive extension 865 disposed at least substantially uniformly along the first metal strip 886 and a second conductive extension disposed at least substantially uniformly along the second metal strip 884. 866 shows a transmission line structure in accordance with the present invention. There is a distributed capacitive bond between the first conductive extension 865 and the second conductive extension 866. Therefore, the characteristic capacitance of the transmission line can be increased / controlled.

In summary, the present invention can be described basically as a method of providing an efficient on-chip capacitor. This is accomplished by creating a capacitive bond therebetween, creating a conductive extension that extends at least substantially vertically from at least two metal layer planes and overlaps with a dielectric therebetween. The invention is not limited to the embodiments described above, but may vary within the scope of the appended claims.

1A shows an example of a plate capacitor,

100 dielectrics,

110 first plate,

120 second plate,

150 distance between the first plate and the second plate.

1B illustrates a metal-insulator-metal (MIM) integrated plate capacitor,

100 dielectrics,

105 silicon wafer,

110 first general metal layer,

121 first portion of the second common metal layer,

122 second portion of the second common metal layer,

161 via (s) between the first portion of the second common metal layer and the first predetermined thin metal plate,

162 via (s) between the second portion of the second common metal layer and the second predetermined thin metal plate,

171 first predetermined thin metal plate,

172 Second predetermined thin metal plate.

1C illustrates a metal-insulator-metal-insulator-metal (MIMIM) integrated plate capacitor,

100 dielectrics,

105 silicon wafer,

111 first portion of the first metal layer,

112 second portion of the first metal layer,

121 first portion of the second metal layer,

122 second portion of the second metal layer,

131 first portion of the third metal layer,

132 Second portion of the third metal layer.

2 shows a top view of the interdigitated capacitor layout,

211 first portion of the metal layer,

212 Second portion of the metal layer.

3a shows a side view of a basic embodiment of a capacitor structure according to the invention,

300 dielectrics,

310 first metal layer, first conduction point in the first plane,

320 second metal layer, second conduction point in the second plane,

352 the distance between the first conductive extension and the second conductive extension,

354 an overlap distance of the first conductive extension and the second conductive extension,

365 first conductive extension from the first conduction point in a second planar direction,

366 A second conductive extension in the first planar direction from the second conductive point.

3b shows a side view of a preferred basic embodiment of a capacitor structure according to the invention,

300 dielectrics,

315 first metal layer, first conductive plate in the first plane,

325 second metal layer, a second conductive plate in the second plane,

365 first conductive extension from the first conduction point in a second planar direction,

366 a second conductive extension in a first planar direction from the second conductive point,

391 capacitive coupling between the first conductive plate and the second conductive plate,

393 capacitive coupling between the second conductive extension and the first conductive plate,

394 capacitive coupling between the first conductive extension and the second conductive extension,

395 capacitive coupling between the first conductive extension and the second conductive plate.

3c shows a cross sectional view through A-A of FIG. 3b of a capacitor structure according to the invention,

315 first conductive plate,

365 cross section of the first conductive extension,

366 Cross section of second conductive extension.

3d shows a three-dimensional view of a preferred basic embodiment of a capacitor structure according to the invention,

315 first conductive plate,

325 second conductive plate,

365 first conductive extension,

366 second conductive extension.

3E shows a cross-sectional view of an optional form of conductive extension,

315 first conductive plate,

365 cross-section of an optional first conductive extension,

366 Cross section of optional second conductive extension.

Figure 4a shows a side view of a preferred basic capacitor structure according to the present invention in three metal layer chip structures.

400 dielectrics,

416 first metal layer and first conductive plate,

426 a portion of the second metal layer, termination to the via (s) from the first metal layer / first conductive plate,

427 a portion of the second metal layer, termination to the via (s) from the third metal layer / second conductive plate,

436 a third metal layer, and a second conductive plate,

465 a portion of the first conductive extension, a via between the first metal layer and the second metal layer,

466 a portion of the second conductive extension, a via between the second metal layer and the third metal layer,

491 capacitive coupling between the first conductive plate and the second conductive plate,

493 capacitive coupling between the second conductive layer of the second conductive extension and the first conductive plate,

494 in the overlap region, in this example a capacitive coupling between the first conductive extension and the second conductive extension in the second metal layer where vias of the first and second conductive extensions terminate;

495 Capacitive coupling between the second conductive plate and the second metal layer of the first conductive extension.

4B shows a cross section through the intermediate metal layer of FIG. 4A, FIG.

426 second metal layer portion of the first conductive extension,

427 a second metal layer portion of the second conductive extension,

465 via portion of first conductive extension,

466 via portion of second conductive extension,

4c shows a side view of a capacitor structure according to the invention in a four metal layer chip structure,

400 dielectrics,

418 first metal layer, first conductive plate,

428 second metal layer, intermediate termination to the via (s) of the first conductive extension,

429 second metal layer, termination to via (s) of second conductive extension,

438 third metal layer, termination to the via of the first conductive extension,

439 third metal layer, intermediate termination to via of second conductive extension,

448 fourth metal layer, second conductive plate,

465 first via portion of the first conductive extension,

466 first via portion of the second conductive extension,

467 a second via portion of the first conductive extension,

468 A second via portion of the second conductive extension.

5a shows a side view of a more complex capacitor structure according to the invention in a four metal layer chip structure,

500 dielectrics,

511 first metal layer, first conductive plate,

521 second metal layer, intermediate termination to via (s) of first conductive extension,

522 second metal layer, termination to the via (s) of the second conductive extension,

531 third metal layer, termination to the via (s) of the first conductive extension,

532 third metal layer, intermediate termination to via (s) of second conductive extension,

541 fourth metal layer, second conductive plate,

561 first via portion of first conductive extension,

562 second via portion of the first conductive extension,

572 second via portion of the second conductive extension,

573 First via portion of the second conductive extension.

5B-5D show cross-sectional views through one of the intermediate metal layers of FIG. 5A, showing examples of different layouts of the conductive extensions,

521 second metal layer, intermediate termination to via (s) of first conductive extension,

522 second metal layer, termination to the via (s) of the second conductive extension,

561 first via portion of first conductive extension,

572 Second via portion of the second conductive extension.

6A-6B show another cross-sectional view of different layout examples of conductive extensions,

621 second metal layer, intermediate termination to the via (s) of the first conductive extension,

622 second metal layer, termination to the via (s) of the second conductive extension,

661 first via portion of first conductive extension,

672 The second via portion of the second conductive extension.

7a-7b show examples of resonant circuits in a structure according to the invention,

711 first metal layer / first conductive plate,

722 termination to the via (s) of the conductive extension from the second metal layer, the fourth metal layer / second conductive plate,

731 third metal layer, intermediate termination to conductive extension to RL,

732 intermediate termination to via (s) of the conductive extension from the third metal layer, fourth metal layer / second conductive plate,

741 fourth metal layer / second conductive plate,

761 first via portion from the first metal layer to RL of the second metal layer,

772 a second via from the fourth metal layer to the RL of the second metal layer through the third metal layer,

773 first via portion from the fourth metal layer,

781 RL segment of the second metal layer.

8 shows a transmission line structure according to the present invention,

865 first conductive extension (s) from the first metal strip,

866 second conductive extension (s) from the second metal strip,

884 second metal strip,

886 first metal strip.

Claims (29)

10. A method of arranging an on-chip capacitor that generates capacitance between a first conductive junction of a first plane of a chip and a second conductive junction of a second plane of a chip. Generating one or more conductive extensions of the first type from the first conductive point to the third plane in the second plane direction, and generating one or more conductive extensions from the second conductive connection point to the fourth plane in the first plane direction. Wherein the fourth plane is located between the first plane and the second plane, and the third plane is located between the fourth plane and the second plane, And wherein the first conductive extension is separated from the second conductive extension by a dielectric that allows an electric field to be generated between the extensions. The method of claim 1, Generating a plurality of conductive extensions of a first type. The method according to claim 1 or 2, Creating a second plurality of conductive extensions of the second type. The method according to any one of claims 1 to 3, And wherein the first plane is one side of the first metal layer, the second plane is one side of the second metal layer, and the first and second metal layers are different metal layers. The method of claim 4, wherein And the third and fourth planes are different sides of the third metal layer. The method of claim 4, wherein And wherein the third plane is one side of the third metal layer, the fourth plane is one side of the fourth metal layer, and the third and fourth metal layers are different metal layers. The method according to any one of claims 1 to 6, Generating a first type of conductive extension or extensions in the metal layer, and terminating the first type of conductive extension or extensions in the metal layer. The method of claim 7, wherein Extending the first type of conductive extension or extensions through one or more additional metal layers. The method according to any one of claims 1 to 8, Generating a second type of conductive extension or extensions in the metal layer and terminating the second type of conductive extension or extensions in the metal layer. The method of claim 9, Extending the second type of conductive extension or extensions through one or more additional metal layers. The method according to any one of claims 1 to 10, Extending the first conductive connection point of the first plane of the chip to include a conductive plate. The method according to any one of claims 1 to 11, Extending the second conductive connection point of the second plane of the chip to include the conductive plate. In the on-chip resonant circuit generation method, 13. A method of arranging an on-chip resonant circuit, comprising generating a resonant circuit by arranging one or more capacitors and one or more other passive components according to any of the preceding claims. In the on-chip transmission line generation method, 13. A method of generating an on-chip transmission line, comprising arranging at least one capacitor according to any one of the preceding claims on a transmission line. An on-chip capacitor having a capacitance between a first conductive connection point in a first plane of a chip and a second conductive connection point in a second plane of the chip, The on-chip capacitor comprises at least one first type of conductive extension from a first conduction point to a third plane in a second plane direction and at least one first agent from a second conductive connection point to a fourth plane in a first plane direction. Two types of conductive extensions, wherein the fourth plane is located between the first plane and the second plane, and the third plane is located between the fourth plane and the second plane, And the first conductive extension is separated from the second conductive extension by a dielectric that allows an electric field to be generated between the extensions. The method of claim 15, An on-chip capacitor further comprising a plurality of conductive extensions of a first type. The method according to claim 15 or 16, An on-chip capacitor further comprising a plurality of conductive extensions of a second type. The method according to any one of claims 15 to 17, The first plane is one side of the first metal layer, and the second plane is one side of the second metal layer, wherein the first metal layer and the second metal layer are different metal layers. The method of claim 18, And the third and fourth planes are different sides of the third metal layer. The method of claim 18, The third plane is one side of the third metal layer, and the fourth plane is one side of the fourth metal layer, wherein the third metal layer and the fourth metal layer are different metal layers. The method according to any one of claims 15 to 20, The first type of conductive extension or extensions extends from the metal layer and ends at the metal layer. The method of claim 21, And the first type of conductive extension or extensions extends through one or more additional metal layers. The method according to any one of claims 15 to 22, And the second type of conductive extension or extensions extends from the metal layer and ends at the metal layer. The method of claim 23, wherein The second type of conductive extension or extensions extends through one or more additional metal layers. The method according to any one of claims 15 to 24, And the first conductive connection point of the first plane of the chip comprises a conductive plate. The method according to any one of claims 15 to 24, And the second conductive connection point of the second plane of the chip comprises a conductive plate. In the on-chip resonant circuit, 27. An on-chip resonant circuit, comprising at least one capacitor according to any one of claims 15 to 26. In the on-chip transmission line, An on-chip transmission line comprising at least one capacitor according to any one of claims 15 to 26. For transmission line based components such as resonators, matching networks, or power dividers, A transmission line board component comprising the transmission line according to claim 28.

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