KR20060112829A - Thin film transistor, thin film transistor array panel, and manufacturing method thereof - Google Patents

Abstract

A thin film transistor is provided to prevent an electrical characteristic of a thin film transistor from being deteriorated while a gate insulation layer is not damaged by varying a mixture ratio of reaction gas when a semiconductor is formed by a CVD method. A first electrode is formed on a substrate. A gate insulation layer is formed on the first electrode. A semiconductor(151) overlaps the first electrode over the gate insulation layer, composed of first and second silicon layers having different densities. At least a part of first and second electrodes overlaps the semiconductor. A resistive contact member is formed between first and second electrodes and the semiconductor.

Description

Thin Film Transistor, Thin Film Transistor Display Panel and Manufacturing Method Thereof {THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL, AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display of FIG. 1 taken along the line II-II '. FIG.

3 is a cross-sectional view of the liquid crystal display of FIG. 1 taken along lines III-III 'and III'-III.

4 is a layout view at a first stage of a method of manufacturing a thin film transistor array panel of the liquid crystal display device shown in FIG. 1 to FIG.

5A and 5B are cross-sectional views taken along the line Va-Va 'and line Vb-Vb' of FIG. 4, respectively.

FIG. 6 is a layout view of a thin film transistor array panel in the next step of FIG. 4.

7A and 7B are cross-sectional views taken along line VIIa-VIIa 'and FIG. VIIb-VIIb', respectively, of FIG. 6.

8 is a graph showing the electrical characteristics of the thin film transistor according to the embodiment of the present invention and the prior art.

FIG. 9 is a layout view of a thin film transistor array panel in the next step of FIG. 6.

10A and 10B are cross-sectional views taken along the lines Xa-Xa 'and XB-Xb' of FIG. 9, respectively.

FIG. 11 is a layout view of a thin film transistor array panel in the next step of FIG. 9.

12A and 12B are cross-sectional views taken along the lines XIIa-XIIa 'and XIIb-XIIb' of FIG. 11, respectively.

13 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

14 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the line XIV-XIV ′.

FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the line XV-XV ′.

16 is a schematic equivalent circuit diagram of an organic light emitting panel according to another exemplary embodiment of the present invention.

17 is a layout view of one pixel of the organic light emitting panel of FIG. 16.

18 is a cross-sectional view of the organic light emitting panel of FIG. 17 taken along the line XVIII-XVIII ′.

FIG. 19 is a cross-sectional view of the organic light emitting panel of FIG. 17 taken along the line XIX-XIX ′.

※ Explanation of drawing code ※

110: insulated substrate

121: gate line

151: semiconductor

171: data line

190: pixel electrode

230: color filter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor array panels, and more particularly, to thin film transistor array panels including amorphous silicon.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor positioned on the gate electrode between the source electrode and the drain electrode. The data signal from the data line is transferred to the pixel electrode in accordance with the scanning signal of. In this case, the semiconductor of the thin film transistor is made of polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon).

Double amorphous silicon is mainly formed by chemical vapor deposition or the like. When the semiconductor is formed by chemical vapor deposition, the characteristics of the semiconductor vary depending on the process environment of chemical vapor deposition. That is, the mixing ratio of the reaction gas, the reaction temperature, the plasma power and the like for forming the semiconductor are important process variables. It is common to adjust the mixing ratio of the reaction gas among these process variables to improve the characteristics of the semiconductor.

As a reaction gas, a mixed gas of SiH ₄ and H ₂ is mainly used, and when a mixed gas of SiH ₄ and H ₂ is used, deposition and etching occur together in the chamber. That is, as the ratio of SiH ₄ increases, the deposition rate increases and the etching rate decreases, whereas as the ratio of H ₂ increases, the deposition rate decreases and the etching rate increases. The slower the formation rate of the semiconductor thin film, the denser the film quality, and thus the better the electrical properties of the thin film.

However, although it is preferable to increase the ratio of H ₂ in order to slow the formation rate of the thin film, the surface of the gate insulating film, which is a lower film of the semiconductor thin film, is damaged by H ₂ . Therefore, the interface characteristics between the gate insulating film and the semiconductor are deteriorated, and thus the electrical characteristics of the thin film transistor are deteriorated.

Accordingly, a technical object of the present invention is to provide a thin film transistor array panel having a semiconductor that does not affect the interfacial properties of the semiconductor and the gate insulating film and the film quality of the semiconductor, and a manufacturing method thereof.

The thin film transistor according to the present invention for achieving the above object is overlapping the first electrode formed on the substrate, the gate insulating film formed on the first electrode, the first electrode on the gate insulating film, the density of the film quality is different A semiconductor comprising first and second silicon layers, and first and second electrodes overlapping at least a portion of the semiconductor.

The contact member may further include an ohmic contact between the first and second electrodes and the semiconductor.

The film quality of the second silicon layer is preferably formed more densely than the film quality of the first silicon layer.

Moreover, it is preferable that the 1st silicon layer is formed in thickness of 100 GPa.

According to another aspect of the present invention, a thin film transistor array panel includes a substrate, a thin film transistor formed on the substrate, and a pixel electrode connected to the thin film transistor, wherein the thin film transistor comprises: a first thin film transistor formed on the substrate; An electrode, a gate insulating film formed on the first electrode, a semiconductor formed in a region overlapping with the first electrode of the gate insulating film, having a first and second silicon layers having different film qualities, and a second at least partially overlapping the semiconductor And a third electrode.

The contact member may further include an ohmic contact between the first and second electrodes and the semiconductor.

The film quality of the second silicon layer is preferably formed more densely than the film quality of the first silicon layer.

Moreover, it is preferable that the 1st silicon layer is formed in thickness of 100 GPa.

The display device may further include a common electrode facing the pixel electrode.

The organic light emitting diode may further include an organic light emitting member interposed between the pixel electrode and the common electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming a first electrode on a substrate, forming a gate insulating film on the first electrode, and forming a first insulating film on the gate insulating film. And forming a semiconductor comprising a second silicon layer, forming second and third electrodes on the semiconductor, forming a protective film on the semiconductor, and forming a pixel electrode on the protective film.

The forming of the semiconductor is preferably performed by varying the proportion of the reaction gas by chemical vapor deposition.

Further, the reaction gas is preferably a gas mixture of SiH ₂ and H _2.

The forming of the semiconductor may include forming a first silicon layer by depositing at a higher H ₂ ratio than SiH ₂ , and forming a second silicon layer to deposit at a high H ₂ ratio. It is desirable to.

Moreover, it is preferable to form a 1st silicon layer in thickness of 100 GPa or less.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display and a liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view of the liquid crystal display of FIG. 1 taken along the line II-II ′, and FIG. 3 is a liquid crystal display of FIG. 1. Is a cross-sectional view taken along lines III-III 'and III'-III.

1 to 3, the liquid crystal display according to the exemplary embodiment may include a lower panel 100, an upper panel 200 facing the lower panel 100, a lower panel 100, and an upper panel 200. Liquid crystal layer 3 and the like contained therein.

The lower panel includes a plurality of gate lines 121 and data lines 171 that are insulated and intersect on the insulating substrate 110. The gate line 121 transfers a scan signal and the data line 171 transfers an image signal. Here, the plurality of pixel areas P defined by the gate line 121 and the data line 171 together form a display area D for displaying an image of the liquid crystal display. Thin film transistors TFTs, which are switching elements, are formed in the plurality of pixel regions P, and the thin film transistors TFT turn on and off image signals according to scan signals.

Each thin film transistor TFT is connected to a pixel electrode (not shown), and the pixel electrode receives an image signal voltage from the thin film transistor TFT.

The upper panel includes a light blocking member having an opening corresponding to the pixel area, a color filter formed in the opening, a common electrode, and the like.

In addition, the liquid crystal display according to the embodiment is positioned between the polarizers 12 and 22 and the display panels 100 and 200 attached to the outer surfaces of the upper and lower display panels and passes through the liquid crystal layer (not shown). It may include a compensation plate (not shown) for compensating the phase of the light.

In this case, the liquid crystal layer may be aligned in a vertical alignment method or a twisted nematic alignment method, and may have a bent arrangement symmetrically with respect to the center planes of the two substrates 110 and 210. The transmission axes of the polarizing plates may be disposed perpendicular to or parallel to each other.

More specifically, the upper and lower display panels will be described.

1 and 3, a light blocking member called a black matrix for preventing light leakage on an insulating substrate 210 made of a transparent insulating material such as glass. 220 is formed. The light blocking member has a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode. The light blocking member 220 may further include a portion facing the thin film transistor and may extend only along the data line 171.

The light blocking member 220 may be formed of a single layer of chromium or a double layer of chromium and chromium oxide, or may be formed of an organic layer including a black pigment.

A plurality of color filters 230 is also formed on the substrate 210. The color filter 230 faces the pixel electrode 190, has a band shape extending in the vertical direction, and may display one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220 to prevent the color filter 230 from being exposed and to provide a flat surface. However, the overcoat 250 may be omitted. The common electrode 270 made of a transparent conductor such as ITO or IZO is formed on the overcoat 250, and an alignment layer 21 is formed thereon.

Next, the lower panel 100 will be described with reference to FIGS. 1 to 3, and a plurality of gate lines 121 and storage electrode lines 131 transmitting a gate signal on an insulating substrate 110, such as transparent glass, are described below. ) Is formed. Each gate line 121 mainly extends in a horizontal direction, and a portion of the gate line 121 is extended and used as a gate electrode 124. The end portion of the gate line 121 may have a large area for connection with an external driving circuit. The driving circuit may be mounted on a flexible printed circuit film attached to the substrate 110 or directly mounted on the substrate 110.

The storage electrode line 131 extends substantially in parallel with the gate line 121 and includes a plurality of storage electrodes 133a and 133b extending from the storage electrode line 131. The pair of storage electrode lines 133a and 133b extend in the vertical direction and are disposed at the edge of the pixel.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiO 2) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (a-Si) are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of projections 154 extend toward the gate electrode 124. In addition, the linear semiconductor 151 increases in width near the point where the linear semiconductor 151 meets the gate line 121 to cover a large area of the gate line 121.

The linear semiconductor 151 is made of amorphous silicon and is formed of a double layer having different densities of thin films. That is, the semiconductor 151 is formed of the first thin film 151a and the second thin film 151b formed on the first thin film 151a, and the first thin film 151a is formed to a thickness of 100 Å or less. The second thin film 151b is formed to a thickness of more than 100 GPa. The second thin film 151b has a denser density of the thin film than the first thin film 151a.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and positioned on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. Each data line 171 has a wide end portion for connecting a plurality of source electrodes 173 extending toward the gate electrode 124 with another layer or an external device.

The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to each other with respect to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 may include a conductive film made of an aluminum based metal, a silver based metal, a copper based metal, molybdenum based metal, chromium, titanium, tantalum, and an alloy thereof. However, they may have a multilayer film structure including two conductive films (not shown) having different physical properties. In this case, one conductive film is made of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop. On the other hand, other conductive films have excellent physical, chemical and electrical contact properties with other materials, especially indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum or alloys thereof. Is done. Examples of such a combination include a chromium lower film, an aluminum (alloy) upper film, an aluminum (alloy) lower film and a molybdenum (alloy) upper film.

Similarly to the gate line 121, the data line 171 and the drain electrode 175 are inclined at an angle of about 30 to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has a portion exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175. The linear semiconductor 151 also has a width of the linear semiconductor 151 smaller than that of the data line 171 in most places, but as described above, the width of the linear semiconductor 151 increases in a portion where it meets the gate line 121 to smooth the surface profile. Thus, disconnection of the data line 171 can be prevented.

An inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, and a low dielectric constant insulator are formed on the data line 171, the drain electrode 175, and the exposed portion of the semiconductor 151. Preferably, the dielectric constant of the low dielectric constant insulator is 4.0 or less, for example, a-Si: C: O, a-Si: O: F, etc., which are formed by plasma enhanced chemical vapor deposition (PECVD). Among the organic insulators, the protective layer 180 may be formed by having photosensitivity, and the surface of the protective layer 180 may be flat. In addition, the passivation layer 180 may be formed as a double layer structure of the lower inorganic layer and the upper organic layer so as to protect the exposed portion of the semiconductor 154 while utilizing the advantages of the organic layer.

The passivation layer 180 is provided with a plurality of contact holes 182 and 185 exposing one end portion of the data line 171 and at least a portion of the drain electrode 175, respectively. In addition, a plurality of contact holes 181 exposing end portions of the gate line 121 are formed in the passivation layer 180 and the gate insulating layer 140.

A plurality of pixel electrodes 190 and a plurality of contact auxiliary members 81 and 82 made of IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175. The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the upper panel 200 to which the common voltage is applied, thereby liquid crystal molecules of the liquid crystal layer 3 between the two display panels 100 and 200. Rearrange them.

In addition, as described above, the pixel electrode 190 and the common electrode 270 form a capacitor (hereinafter referred to as a “liquid crystal capacitor”) to maintain the applied voltage even after the thin film transistor is turned off. There are other capacitors connected in parallel with the liquid crystal capacitor, which are called maintenance capacitors. The storage capacitor is formed by overlapping the pixel electrode 190 and the neighboring gate line 121 (hereinafter, referred to as a shear gate line). The storage capacitor is connected with the gate line 121 to increase the capacitance of the storage capacitor, that is, the storage capacitance. An extended protrusion (not shown) is provided to increase the overlapped area, while a conductive capacitor (not shown) connected to the pixel electrode 190 and overlapping with the protrusion is placed under the protective film 180 between the two. You can get closer. Alternatively, a storage capacitor can be formed by overlapping a separate storage electrode line (see FIG. 1) and the pixel electrode 190.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact assistants 81 and 82 are connected to exposed ends of the gate line 121 and the data line 171 through the contact holes 181 and 182, respectively. The contact assistants 81 and 82 compensate for and protect the adhesiveness between the ends of the gate line 121 and the data line 171 and the external device.

Finally, an alignment layer 11 is formed on the pixel electrode 190, the contact auxiliary members 81 and 82, and the passivation layer 180.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 to 3 will be described in detail with reference to FIGS. 10 to 11 and FIGS. 2 to 4.

FIG. 4 is a layout view of a first step of a method of manufacturing a thin film transistor array panel of the liquid crystal display device shown in FIGS. 1 to 3 according to one embodiment of the present invention, and FIGS. 5A and 5B are respectively Va- of FIG. 6 is a cross-sectional view taken along line Va ′ and line Vb-Vb ′, and FIG. 6 is a layout view of a thin film transistor array panel in the next step of FIG. 4, and FIGS. 7A and 7B are lines VIIa-VIIa 'of FIG. 6, respectively. And FIG. 8 is a cross-sectional view taken along line VIIb-VIIb ′, and FIG. 8 is a graph illustrating electrical characteristics of a thin film transistor according to an exemplary embodiment of the present invention and a prior art, and FIG. 9 is a thin film transistor array panel in the next step of FIG. 6. 10A and 10B are cross-sectional views taken along line Xa-Xa 'and XB-Xb' of FIG. 9, respectively, and FIG. 11 is a layout view of a thin film transistor array panel in the next step of FIG. 12A and 12B are XIIa-XIIa ′ lines of FIG. 11, respectively. And a cross-sectional view taken along the line XIIb-XIIb '.

First, referring to FIGS. 4 to 5B, after the conductive film is stacked on the insulating substrate 110 by sputtering on the insulating substrate 110, the gate line 121 including the gate electrode 124 is formed by photolithography. Form.

Next, referring to FIGS. 6 to 7B, three layers of a gate insulating layer 140, intrinsic amorphous silicon, and an impurity amorphous silicon layer are successively stacked, and an impurity amorphous silicon layer and an intrinsic amorphous layer are stacked. The silicon layer is photo-etched to form a linear intrinsic semiconductor 151 including a plurality of linear impurity semiconductors 164 and protrusions 154.

Here, the intrinsic amorphous silicon layer uses a mixed gas of SiH ₂ and H ₂ as a reaction gas during deposition, and is formed by varying their mixing ratio. In other words, the ratio of H ₂ higher than the proportion of SiH _2, a first amorphous silicon layer (151a) formed and then SiH second amorphous silicon by the percentage of ₂ higher than the H ₂ layer (151b) have a thickness of about 100Å Form. Then, since the formation speed of the first amorphous silicon layer 151a is two or more times faster than that of the second amorphous silicon layer 151b, the first amorphous silicon layer 151a has a higher film quality than the second amorphous silicon layer 151b. I can't.

Here, the first amorphous silicon layer 151a is formed to have a minimum thickness to prevent the gate insulating layer 140 from being damaged when the second amorphous silicon layer is formed. do. Therefore, even if the second amorphous silicon layer 151b is formed to increase the ratio of H ₂ to form a dense film, the lower gate insulating layer 140 is not damaged.

8 is a graph showing the electrical characteristics of the thin film transistor according to the embodiment of the present invention and the prior art.

Referring to FIG. 8, according to the related art, Ion and μ gradually increase with increasing H ₂ , and then start to decrease after a certain level. However, according to the exemplary embodiment of the present invention, it can be seen that Ion and μ gradually increase with increasing H ₂ and continue to maintain a constant value without decreasing.

9 to 10B, a plurality of data lines 171 and a plurality of drain electrodes 175 including the source electrode 173 are formed by stacking and patterning a metal film by sputtering or the like.

The portions of the impurity semiconductor 164 that are not covered by the data line 171 and the drain electrode 175 are removed to remove the portions of the linear ohmic contact 161 including the protrusions 163 and the islands of ohmic contact. While completing 165, the portion of the intrinsic semiconductor 151 below it is exposed.

Next, as shown in FIGS. 11 through 12B, a passivation layer 180 is formed on the insulating substrate 110 and then patterned together with the passivation layer 180 and the gate insulating layer 140 to form a plurality of contact holes 181 and 182. , 185). The contact holes 181, 182, and 185 expose the gate line 121, the end of the data line, and the drain electrode 175, respectively.

1 to 3, a transparent conductive material such as IZO or ITO or the like is laminated and sputtered to form a plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82. .

Thereafter, a process of forming a substrate spacer (not shown) and the alignment layer 11 may be added. The substrate spacer may be formed on the upper insulating substrate 210.

Next, a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment will be described in detail with reference to FIGS. 13 to 15.

FIG. 13 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 14 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the line XIV-XIV ′, and FIG. Is a cross-sectional view of a thin film transistor array panel taken along the line XV-XV '.

13 to 15, the layer structure of the thin film transistor array panel for a liquid crystal display device according to the present exemplary embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display devices illustrated in FIGS. 1 to 3. That is, a plurality of gate lines 121 including the gate electrode 124 is formed on the substrate 110, and the plurality of linear semiconductors 151 including the gate insulating layer 140 and the protrusion 154 thereon. A plurality of linear ohmic contact members 161 including protrusions 163 and a plurality of island-type ohmic contact members 165 are sequentially formed. A plurality of data lines 171 including a source electrode 173 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165, and a plurality of contact holes 181, 182, and 185 are formed thereon. The branch has a protective film 180 formed thereon. A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180.

However, unlike the thin film transistor array panel of the liquid crystal display device illustrated in FIGS. 1 to 3, the linear semiconductor 151 is substantially connected to the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. Have the same planar shape. However, the protrusion 154 of the semiconductor 151 has an exposed portion, not covered by the data line 171 and the drain electrode 175, such as a portion between the source electrode 173 and the drain electrode 175.

The structures and methods illustrated in FIGS. 1 to 3 may also be applied to an organic light emitting panel, which will be described in detail with reference to FIGS. 16 to 18.

FIG. 16 is a schematic equivalent circuit diagram of an organic light emitting panel according to another embodiment of the present invention, FIG. 17 is a layout view of one pixel of the organic light emitting panel of FIG. 16, and FIG. 18 is an XVIII-type organic light emitting panel of FIG. 17. 19 is a cross-sectional view taken along the line XVIII ′, and FIG. 19 is a cross-sectional view taken along the line XIX-XIX ′ of the organic light emitting display panel of FIG. 17.

Referring to FIG. 16, the organic light emitting diode display according to the present exemplary embodiment includes a plurality of signal lines 121, 172, and 172, and a plurality of pixels P connected to the plurality of signal lines 121, 172, and 172 and arranged in a substantially matrix form. do.

The signal line includes a plurality of gate lines 121 for transmitting a scan signal, a data line 171 for transmitting a data signal, and a plurality of driving voltage lines 172 for transmitting a driving voltage. The gate lines 121 extend substantially in the row direction, and are substantially parallel to each other, and the data line 171 and the driving voltage line 172 extend substantially in the column direction, and are substantially parallel to each other.

Each pixel P includes an organic light emitting element LD, a driving transistor Qd, a capacitor Cst, and a switching transistor Qs.

The driving transistor Qd has a control terminal, an input terminal, and an output terminal. The control terminal is connected to the switching transistor Qs, the input terminal is connected to the driving voltage line 172, and the output terminal is an organic light emitting element. It is connected to (LD).

The organic light emitting element LD has an anode connected to the output terminal of the driving transistor Qd and a cathode connected to the common voltage Vcom. The organic light emitting element LD displays an image by emitting light at different intensities according to the output current of the driving transistor Qd. The current of the driving transistor Qd varies in magnitude depending on the voltage applied between the control terminal and the output terminal.

The switching transistor Qs also has a control terminal, an input terminal, and an output terminal. The control terminal is connected to the gate line 121, the input terminal is connected to the data line 171, and the output terminal is a driving transistor ( It is connected to the control terminal of Qd). The switching transistor Qs transfers the data line signal applied to the data line 171 to the driving transistor Qd according to the scan signal applied to the gate line 121.

The capacitor Cst is connected between the control terminal and the input terminal of the driving transistor Qd. This capacitor Cst charges and holds a data signal applied to the control terminal of the driving transistor Qd.

Next, a structure of the display panel for the organic light emitting diode display illustrated in FIG. 16 will be described in detail with reference to FIGS. 17 to 19.

17 is a layout view of an organic light emitting panel according to an exemplary embodiment of the present invention, and FIGS. 18 and 19 are cross-sectional views of the organic light emitting panel of FIG. 17 taken along lines XVIII-XVIII 'and XIX-XIX', respectively. One example.

17 to 19, a plurality of gate lines 121 including a first control electrode 124a and a plurality of second control electrodes 124b are disposed on the transparent insulating substrate 110. A gate conductor is formed.

The gate line 121 mainly extends in the horizontal direction and transmits a gate signal. The gate line 121 includes a wide end portion for connection with another layer or a driving circuit. The second control electrode 124b is connected to the sustain electrode 127 extending in the vertical direction.

The gate conductors 121 and 124b are made of molybdenum-based metal such as molybdenum (Mo) or molybdenum alloy, refractory metal such as chromium (Cr), titanium (Ti), tantalum (Ta), or an alloy thereof. Can lose. However, they may have a multilayer film structure including two conductive films (not shown) having different physical properties. In this case, one conductive film is made of a refractory metal, and the other conductive film has a low resistivity metal such as aluminum (Al) or aluminum alloy such as aluminum (Ag) to reduce signal delay or voltage drop. Or a silver alloy such as a silver alloy or a copper-based metal such as copper (Cu) or a copper alloy. An example of such a combination is a double film of an aluminum (alloy) bottom film and a chromium or molybdenum (alloy) top film.

The side surfaces of the gate conductors 121 and 124b are inclined, and the inclination angle is 30 to 80 ° with respect to the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiO 2) is formed on the gate line 121.

A plurality of linear semiconductors 151 and island semiconductors 154b made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140.

The linear semiconductor 151 and the island-like semiconductor 154b are made of amorphous silicon and are formed of double layers having different densities of thin films. That is, the semiconductor 151 is formed of the first thin film 151a and the second thin film 151b formed on the first thin film 151a, and the first thin film 151a is formed to a thickness of 100 Å or less. The second thin film 151b is formed to a thickness of more than 100 GPa. The second thin film 151b has a denser density of the thin film than the first thin film 151a.

The linear semiconductor 151 extends in the vertical direction, and a plurality of protrusions 154a extend toward the first gate electrode 124a to form a first channel portion overlapping the first gate electrode 124a. In addition, the width of the linear semiconductor 151 extends near a point where the linear semiconductor 151 meets the gate line 121. The island type semiconductor 154b includes a second channel portion crossing the second gate electrode 124b and is connected to the storage electrode portion 157 overlapping the storage electrode 127.

On top of the linear semiconductor 151 and the island-like semiconductor 154b, a plurality of linear and island resistive contact layers 161 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities such as silicide or phosphorus 165a, 163b, and 165b are formed. The linear contact layer 161 has a plurality of protrusions 163a, and the protrusions 163a and the island contact layer 165a are paired and positioned on the protrusions 154a of the linear semiconductor 151. In addition, the plurality of protrusions 163b and the island contact layer 165b face each other with respect to the second gate electrode 124b to form a pair and are positioned on the island semiconductor 154b.

Side surfaces of the semiconductors 151 and 154b and the ohmic contacts 161, 165a, 163b, and 165b are also inclined and have an inclination angle of 30 ° to 80 °.

The plurality of data lines 171, the plurality of driving voltage lines 172, and the plurality of first and second output electrodes 175a and 175b are disposed on the ohmic contacts 161, 165a, 163b, and 165b and the gate insulating layer 140, respectively. A data conductor comprising a is formed.

The data line 171 transmitting the data signal mainly extends in the vertical direction and intersects the gate line 121, and may have an end portion (not shown) having a large area for connection with another layer or an external device. When a data driving circuit (not shown) generating a data signal is integrated in the substrate 110, the data line 171 may be directly connected to the data driving circuit. Each data line 171 includes a plurality of horizontally extending first input electrodes 173a, and opposite the first output electrodes 175a are positioned.

The driving voltage line 172 transferring the driving voltage is adjacent to the data line 171 and mainly extends in the vertical direction. The driving voltage line 172 includes a plurality of second input electrodes 173b extending horizontally, and the first output electrode 175a is positioned opposite to the driving voltage line 172.

The data conductors 171, 172, 175a, and 175b include a conductive film made of aluminum-based metal, silver-based metal, copper-based metal, molybdenum-based metal, chromium, titanium, tantalum, and alloys thereof. However, they may have a multilayer film structure including two conductive films (not shown) having different physical properties. In this case, the limiting film is made of low resistivity metals such as aluminum-based metals, silver-based metals, and copper-based metals to reduce signal delays and voltage drops. In contrast, the other conductive film is made of a material having excellent physical, chemical and electrical contact properties with other materials, especially ITO and IZO, such as molybdenum-based metals, chromium, titanium, tantalum or alloys thereof. Examples of such a combination include a chromium lower film, an aluminum (alloy) upper film, an aluminum (alloy) lower film and a molybdenum (alloy) upper film.

The first control electrode 124a, the first input electrode 173a, and the first output electrode 175a form the switching thin film transistor Qs together with the semiconductor 154a and the ohmic contact members 163a and 165a, and the switching thin film. A channel of the transistor Qs is formed in the semiconductor 154a between the first input electrode 173a and the first output electrode 175a. The second control electrode 124b, the second input electrode 173b, and the second output electrode 175b form the driving thin film transistor Qd together with the semiconductor 154b and the ohmic contacts 163b and 165b, and the driving thin film. A channel of the transistor Qd is formed in the semiconductor 154b between the second input electrode 173b and the second output electrode 175b.

The passivation layer 180 is formed on the data conductors 171, 172, 175a, and 175b and the exposed semiconductors 151 and 154b. The passivation layer 180 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the low dielectric insulator is preferably 4.0 or less, for example, a-Si: C: O, a-Si: O: F, etc. formed by plasma chemical vapor deposition. Among the organic insulators, the protective layer 180 may be formed by having photosensitivity, and the surface of the protective layer 180 may be flat. In addition, the passivation layer 180 may be formed as a double layer structure of the lower inorganic layer and the upper organic layer so as to protect the exposed portions of the semiconductors 151 and 154 while utilizing the advantages of the organic layer.

The passivation layer 180 may include a plurality of first drain electrodes 175a, second gate electrodes 124b, second drain electrodes 175b, and a plurality of gate portions 129 and end portions 129 of the gate lines and the end portions 179 of the data lines, respectively. Contact holes 185b, 184, 185a, 182, and 181 are formed.

A plurality of pixel electrodes 190, a plurality of connection members 85, and a plurality of contact assistants 81 and 82 formed of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the second drain electrode 175b through the contact hole 185b, respectively, and the connection member 85 is connected to the first drain electrode through the contact holes 185a and 184. 175a and the second gate electrode 124b are connected to each other.

The partition wall 360 is formed on the passivation layer 180 and the pixel electrode 190. The partition wall 360 surrounds the edge of the pixel electrode 190 like a bank to define an opening and is made of an organic insulating material or an inorganic insulating material.

An organic light emitting member 370 is formed on the pixel electrode 190, and the organic light emitting member 370 is trapped in an opening surrounded by the partition wall 360.

The organic light emitting member 370 may have a multilayer structure including an emitting layer (not shown) that emits light, and additional layers for improving the light emitting efficiency of the emitting layer. The secondary layer includes an electron transport layer (not shown) and a hole transport layer (not shown) to balance electrons and holes, and an electron injection layer to enhance injection of electrons and holes ( electron injecting layer (not shown) and hole injecting layer (not shown). Subsidiary layers may be omitted.

The common electrode 270 is formed on the partition wall 360 and the organic light emitting member 370. The common electrode 270 receives a common voltage and is made of a reflective metal including calcium (Ca), barium (Ba), chromium, aluminum, silver, or the like, or a transparent conductive material such as ITO or IZO.

The opaque pixel electrode 190 and the transparent common electrode 270 are applied to a top emission organic light emitting display device that displays an image in an upper direction of the display panel, and are in common with the transparent pixel electrode 190. The electrode 270 is applied to a bottom emission organic light emitting display device that displays an image in a downward direction of the display panel.

The pixel electrode 190, the organic light emitting member 370, and the common electrode 270 form the organic light emitting element LD illustrated in FIG. 1, the pixel electrode 190 becomes an anode, and the common electrode 270 has a cathode. do. However, on the contrary, the pixel electrode 190 may be a cathode and the common electrode 270 may be an anode. The organic light emitting element LD emits light of one of the primary colors according to the material of the organic light emitting member 370. Examples of the primary colors include three primary colors of red, green, and blue, and the desired color is represented by a spatial sum of these three primary colors.

As described above, when the semiconductor is formed by the chemical vapor deposition method, by varying the mixing ratio of the reaction gases, it is possible to provide a display panel including a high quality thin film transistor in which the gate insulating film is not damaged and the electrical characteristics of the thin film transistor are not degraded. have.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (15)

A first electrode formed on the substrate, A gate insulating film formed on the first electrode, A semiconductor overlapping the first electrode on the gate insulating layer and including first and second silicon layers having different densities of film quality; And a first electrode and a second electrode at least partially overlapping the semiconductor. In claim 1, And a resistive contact member between the first and second electrodes and the semiconductor. In claim 1, The film quality of the second silicon layer is denser than the film quality of the first silicon layer. In claim 1, And the first silicon layer is formed to a thickness of 100 kV. Board, A thin film transistor formed on the substrate, and A pixel electrode connected to the thin film transistor, The thin film transistor, A first electrode formed on the substrate, A gate insulating film formed on the first electrode, A semiconductor formed in a region overlapping the first electrode of the gate insulating film and having first and second silicon layers having different film qualities, A thin film transistor array panel including second and third electrodes at least partially overlapping the semiconductor. In claim 5, The thin film transistor array panel of claim 1, further comprising an ohmic contact between the first and second electrodes and the semiconductor. In claim 5, The film quality of the second silicon layer is denser than the film quality of the first silicon layer. In claim 5, And the first silicon layer is formed to a thickness of 100 GHz. In claim 5, The thin film transistor array panel of claim 1, further comprising a common electrode facing the pixel electrode. In claim 5, The thin film transistor array panel of claim 1, further comprising an organic light emitting member interposed between the pixel electrode and the common electrode. Forming a first electrode on the substrate, Forming a gate insulating film on the first electrode, Forming a semiconductor including first and second silicon layers having different film quality on the gate insulating layer; Forming second and third electrodes on the semiconductor, Forming a protective film on the semiconductor, and And forming a pixel electrode on the passivation layer. In claim 11, Forming the semiconductor is a method of manufacturing a thin film transistor array panel formed by varying the proportion of the reaction gas by chemical vapor deposition. In claim 12, And the reaction gas is a mixed gas of SiH ₂ and H ₂ . In claim 13, Forming the semiconductor, Forming a first silicon layer to increase the deposition rate of the H ₂ than the SiH _2, A method of manufacturing a thin film transistor array panel including forming a second silicon layer to be deposited by increasing the ratio of H ₂ . The method of claim 14, The first silicon layer is formed to a thickness of less than 100 GPa.

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