KR20060108663A - Method and structure for forming strained si for cmos devices - Google Patents

Method and structure for forming strained si for cmos devices Download PDF

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KR20060108663A
KR20060108663A KR1020067008867A KR20067008867A KR20060108663A KR 20060108663 A KR20060108663 A KR 20060108663A KR 1020067008867 A KR1020067008867 A KR 1020067008867A KR 20067008867 A KR20067008867 A KR 20067008867A KR 20060108663 A KR20060108663 A KR 20060108663A
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semiconductor substrate
gap
semiconductor
strained layer
layer
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KR1020067008867A
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Korean (ko)
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KR100866826B1 (en
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안 엘 스티겐
하이닝 에스 양
잉 장
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인터내셔널 비지네스 머신즈 코포레이션
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  • Recrystallisation Techniques (AREA)

Abstract

A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate (200) and forming a gap (219) in the semiconductor substrate (200) by removing at least a portion of the doped portion of the semiconductor substrate (200). The method further involves growing a strain layer (227) in at least a portion of the gap (219) in the semiconductor substrate (200). For the n-type device, the strain layer (227) is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Description

ＣＭＯＳ 디바이스를 위한 변형된 Ｓｉ를 형성하는 방법 및 구조{METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES}METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES

본 발명은 일반적으로 개선된 디바이스 성능을 갖는 반도체 디바이스를 제조하는 방법에 관한 것으로, 더욱 구체적으로 디바이스 제조 시 디바이스의 기판 내에 장력 및 압축 응력을 가하는 반도체 디바이스를 제조하는 방법에 관한 것이다.TECHNICAL FIELD The present invention generally relates to a method of manufacturing a semiconductor device having improved device performance, and more particularly, to a method of manufacturing a semiconductor device applying tension and compressive stress in a substrate of the device during device manufacturing.

일반적으로, 금속 산화물 반도체 트랜지스터는 실리콘과 같은 반도체 재료로 이루어진 기판을 포함한다. 트랜지스터는 전형적으로 기판 내에 소스 영역, 채널 영역 및 드레인 영역을 포함한다. 채널 영역은 소스 영역과 드레인 영역 사이에 위치한다. 도전성 재료, 게이트 산화물 층 및 측벽 스페이서(spacer)들을 통상 포함하는 게이트 적층체(gate stack)가 일반적으로 채널 영역 위에 제공된다. 더욱 구체적으로, 게이트 산화물 층은 전형적으로 채널 영역 위의 기판 상에 제공되는데, 게이트 도체는 통상적으로 게이트 산화물 층 위에 제공된다. 측벽 스페이서들은 게이트 도체의 측벽들의 보호를 돕는다.Generally, metal oxide semiconductor transistors include a substrate made of a semiconductor material such as silicon. Transistors typically include a source region, a channel region and a drain region in a substrate. The channel region is located between the source region and the drain region. A gate stack typically comprising a conductive material, a gate oxide layer and sidewall spacers is generally provided over the channel region. More specifically, a gate oxide layer is typically provided on a substrate over the channel region, with the gate conductor typically provided over the gate oxide layer. Sidewall spacers help protect the sidewalls of the gate conductor.

양단에 주어진 전계를 갖는 채널을 통해 흐르는 전류량은 일반적으로 채널 내의 캐리어의 이동도에 정비례한다는 것이 공지되어 있다. 그러므로, 채널 내의 캐리어의 이동도를 증가시킴으로써, 트랜지스터의 동작 속도가 증가될 수 있다.It is known that the amount of current flowing through a channel with a given electric field across it is generally directly proportional to the mobility of the carrier in the channel. Therefore, by increasing the mobility of carriers in the channel, the operating speed of the transistor can be increased.

반도체 디바이스 기판 내의 기계적 응력은, 예를 들어 반도체 디바이스 내의 캐리어의 이동도를 증가시킴으로써, 디바이스 성능을 조정할 수 있다는 것이 또한 공지되어 있다. 즉, 반도체 디바이스 내의 응력은 반도체 디바이스 특성을 향상시키는 것으로 알려져 있다. 그러므로, 반도체 디바이스의 특성을 개선시키기 위해, 장력 및/또는 압축 응력은 n형 디바이스(예를 들어, NFET) 및/또는 p형 디바이스(예를 들어, PFET)의 채널 내에 생성된다. 그러나, 동일한 응력 성분, 예를 들어 장력 또는 압축 응력은 한가지 유형의 디바이스(즉, n형 디바이스 또는 p형 디바이스)의 디바이스 특성을 개선시키는 반면, 다른 유형의 디바이스의 특성에는 다르게 영향을 미친다.It is also known that mechanical stress in a semiconductor device substrate can adjust device performance, for example by increasing the mobility of carriers in the semiconductor device. That is, stresses in semiconductor devices are known to improve semiconductor device characteristics. Therefore, to improve the properties of semiconductor devices, tension and / or compressive stresses are created in the channels of n-type devices (eg, NFETs) and / or p-type devices (eg, PFETs). However, the same stress component, for example tension or compressive stress, improves the device properties of one type of device (ie, n-type device or p-type device), while affecting the properties of other types of devices differently.

집적 회로(IC) 디바이스 내의 NFET 및 PFET 둘다의 성능을 최대화하기 위해, 응력 성분은 NFET 및 PFET에 대해 다르게 설계되어 적용되어야 한다. 그것은 NFET의 성능에 유리한 응력의 형태가 일반적으로 PFET의 성능에 불리하기 때문이다. 더욱 구체적으로, 디바이스가 (평면 디바이스 내의 전류 흐름 방향으로) 장력을 받을 때, NFET의 성능 특성은 향상되지만, PFET의 성능 특성은 감소된다. NFET 내에서의 장력 및 PFET 내에서의 압축 응력을 선택적으로 생성하기 위해, 차별적인 프로세스 및 상이한 재료 조합이 사용된다.To maximize the performance of both NFETs and PFETs in integrated circuit (IC) devices, stress components must be designed and applied differently for NFETs and PFETs. This is because the form of stress that favors the performance of the NFET is generally disadvantageous to the performance of the PFET. More specifically, when the device is tensioned (in the direction of current flow in the planar device), the performance characteristics of the NFET are improved, but the performance characteristics of the PFET are reduced. Differential processes and different material combinations are used to selectively create tension in NFETs and compressive stresses in PFETs.

예를 들어, 트렌치 분리 구조는 NFET 및 PFET 내에 적절한 응력을 각각 형성하기 위해 제안되었다. 이 방법이 사용될 때, NFET 디바이스를 위한 분리 영역은 세로 방향(전류 흐름에 평행한 방향) 및 가로 방향(전류 흐름에 수직인 방향)으로 NFET 디바이스 상에 제1 유형의 기계적 응력을 인가하는 제1 분리 재료를 포함한 다. 더구나, 제1 분리 영역 및 제2 분리 영역은 PFET에 제공되고, PFET 디바이스의 각각의 분리 영역은 가로 방향 및 세로 방향으로 PFET 디바이스 상에 유일한 기계적 응력을 인가한다.For example, trench isolation structures have been proposed to create appropriate stresses in NFETs and PFETs, respectively. When this method is used, the isolation region for the NFET device is a first that applies a first type of mechanical stress on the NFET device in the longitudinal direction (direction parallel to the current flow) and in the transverse direction (direction perpendicular to the current flow). Contains separation materials. Moreover, a first isolation region and a second isolation region are provided to the PFET, each isolation region of the PFET device applying a unique mechanical stress on the PFET device in the transverse and longitudinal directions.

다른 방법으로, 게이트 측벽 상의 라이너(liner)는 FET 디바이스의 채널 내에 적절한 변형을 선택적으로 유발시키기 위해 제안되었다(예를 들어, Ootsuka 등 저의 IEDM 2000, 575 페이지 참조). 라이너를 제공함으로써, 적절한 응력은 트렌치 분리 충전(fill) 기술의 결과로서 인가된 응력보다 디바이스에 더 가깝게 인가된다.Alternatively, a liner on the gate sidewalls has been proposed to selectively cause appropriate deformation in the channel of the FET device (see, eg, Otsuka et al., IEDM 2000, page 575). By providing the liner, the appropriate stress is applied closer to the device than the stress applied as a result of the trench isolation fill technique.

이들 방법은 NFET 디바이스에 인가되는 장력 및 PFET 디바이스의 세로 방향을 따라 인가되는 압축 응력을 갖는 구조를 제공하지만, 추가 재료 및/또는 더욱 복잡한 공정을 필요로 할 수 있으므로, 더욱 비싼 비용을 초래할 수 있다. 더구나, 이러한 상황들에서 인가될 수 있는 응력의 레벨은 전형적으로 완화된다(즉, MPa의 100s 정도). 그러므로, 채널 NFET 및 PFET 내에 각각 큰 장력 및 압축 응력을 생성하기 위한, 더욱 비용-효과적이고 단순화된 방법을 제공하는 것이 요구된다.These methods provide a structure with a tension applied to the NFET device and a compressive stress applied along the longitudinal direction of the PFET device, but may require additional materials and / or more complex processes, which may result in more expensive costs. . Moreover, the level of stress that can be applied in these situations is typically relaxed (ie, about 100s of MPa). Therefore, there is a need to provide a more cost-effective and simplified method for generating large tensile and compressive stresses in channel NFETs and PFETs, respectively.

본 발명의 제1 실시양상에서, 본 발명은 n형 디바이스 및 p형 디바이스를 포함하는 디바이스를 제조하는 방법을 제공한다. 이 방법은 반도체 기판의 일부분을 도핑하는 단계, 및 반도체 기판의 도핑된 부분의 적어도 일부분을 제거함으로써 반도체 기판 내에 갭을 형성하는 단계를 포함한다. 이 방법은 반도체 기판 내의 갭의 적어도 일부분 내에 변형층을 성장시키는 단계를 더 포함한다.In a first aspect of the invention, the invention provides a method of manufacturing a device comprising an n-type device and a p-type device. The method includes doping a portion of the semiconductor substrate, and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further includes growing a strained layer in at least a portion of the gap in the semiconductor substrate.

본 발명의 실시양상에서, n형 디바이스의 경우, 변형층은 n형 디바이스의 채널의 실질적으로 바로 아래에 있는 적어도 일부분 상에 성장된다. p형 디바이스의 경우, 변형층은 p형 디바이스의 소스 영역 또는 드레인 영역의 실질적으로 바로 아래 부분이지만, p형 디바이스의 채널의 실질적으로 바로 아래 부분이 아닌 적어도 일부분 상에 성장된다.In an aspect of the present invention, for an n-type device, the strained layer is grown on at least a portion that is substantially underneath the channel of the n-type device. In the case of a p-type device, the strained layer is grown on at least a portion of the source region or drain region of the p-type device, but not at the portion substantially below the channel of the p-type device.

본 발명의 다른 실시양상에서, 본 발명은 n형 디바이스 및 p형 디바이스를 포함하는 디바이스를 제조하는 방법을 제공한다. 이 방법은 반도체 기판 상에 변형층을 성장시키는 단계 및 변형층 위에 실리콘층을 성장시키는 단계를 포함한다. 갭은 반도체 기판의 위로부터 실리콘층 및 변형층의 적어도 일부분을 제거함으로써 반도체 기판과 실리콘층 사이에 형성되고, 변형층은 갭의 적어도 일부분 내에 성장된다. n형 디바이스의 경우에, 변형층은 n형 디바이스의 채널의 실질적으로 바로 아래에 있는 적어도 일부분 상에 성장된다. p형 디바이스의 경우에, 변형층은 p형 디바이스의 소스 영역 또는 드레인 영역의 실질적으로 바로 아래 부분이지만, p형 디바이스의 채널의 실질적으로 아래 부분이 아닌 적어도 일부분 상에 성장된다.In another aspect of the invention, the invention provides a method of manufacturing a device comprising an n-type device and a p-type device. The method includes growing a strained layer on a semiconductor substrate and growing a silicon layer over the strained layer. A gap is formed between the semiconductor substrate and the silicon layer by removing at least a portion of the silicon layer and the strain layer from over the semiconductor substrate, and the strain layer is grown in at least a portion of the gap. In the case of an n-type device, the strained layer is grown on at least a portion substantially below the channel of the n-type device. In the case of a p-type device, the strained layer is grown on at least a portion of the source region or drain region of the p-type device, but at least partially but not substantially below the channel of the p-type device.

본 발명은 적어도 하나의 갭을 갖는 반도체 기판을 갖고 있는 반도체 디바이스를 따로 제공하는데, 갭은 반도체 기판의 일부분 아래로 연장한다. 이 디바이스는 반도체 기판 상의 게이트 적층체, 및 갭의 적어도 일부분 내에 형성된 변형층을 포함하는데, 갭은 반도체 기판의 일부분을 도핑하고 반도체 기판의 도핑된 부분을 에칭함으로써 형성된다.The present invention separately provides a semiconductor device having a semiconductor substrate having at least one gap, the gap extending below a portion of the semiconductor substrate. The device includes a gate stack on a semiconductor substrate, and a strained layer formed in at least a portion of the gap, wherein the gap is formed by doping a portion of the semiconductor substrate and etching the doped portion of the semiconductor substrate.

본 발명의 다른 실시양상에서, 본 발명은 적어도 하나의 갭을 갖는 반도체 기판을 갖고 있는 반도체 디바이스를 제공하는데, 갭은 반도체 기판의 일부분 아래로 연장한다. 이 디바이스는 반도체 기판 상의 게이트 적층체, 및 반도체 기판의 소스 영역 및 드레인 영역의 적어도 일부분 아래에만 형성된 변형층을 포함한다.In another aspect of the invention, the invention provides a semiconductor device having a semiconductor substrate having at least one gap, the gap extending below a portion of the semiconductor substrate. The device includes a gate stack on a semiconductor substrate and a strained layer formed only below at least a portion of the source and drain regions of the semiconductor substrate.

도 1은 PFET 및 NFET에 대한 요구된 응력 상태를 도시한 도면.1 illustrates the required stress states for PFETs and NFETs.

도 2a 내지 2j는 본 발명에 따른 p형 트랜지스터를 형성하는 예시적인 공정을 도시한 도면.2A-2J illustrate an exemplary process for forming a p-type transistor in accordance with the present invention.

도 3a 내지 3d는 본 발명에 따른 n형 트랜지스터를 형성하는 예시적인 공정을 도시한 도면.3A-3D illustrate an exemplary process for forming an n-type transistor in accordance with the present invention.

도 4는 본 발명에 따른 트랜지스터의 하향도.4 is a top down view of a transistor according to the present invention.

도 5는 주사 전자 현미경을 사용한 본 발명에 따른 반도체 기판의 단면도.5 is a cross-sectional view of a semiconductor substrate according to the present invention using a scanning electron microscope.

본 발명은 개선된 성능 특성을 갖는 디바이스를 제조하는 방법을 제공한다. SiGe 층, Si3N4 층, SiO2 층 또는 SiOxNy 층과 같은 응력층이 실리콘 층 상에 에피택셜 성장될 때, 압축 응력은 SiGe 층 내에서 형성되고, 장력은 실리콘 층 내에서 형성된다. 본 발명의 한 실시양상에서, 실리콘 기판은 변형층이 성장되는 갭을 갖는다. 갭은 반도체 기판의 상부 부분과 반도체 기판의 하부 부분 사이에 있는 터널형 부분을 포함한다. 더욱 구체적으로, 상부 부분은 하부 표면을 갖고 있고, 하부 부분은 상부 표면을 갖고 있으며, 상부 부분의 하부 표면은 하부 부분의 상부 표면에 대면하고 있다. 채널의 실질적으로 아래에 변형층을 갖고/갖거나, 반도체 디바이스의 소스 영역 및/또는 드레인 영역의 실질적으로 아래의 반도체 기판 영역 내에 변형층을 가짐으로써, 응력은 트랜지스터의 채널 내에 형성된다. 본 발명의 실시양상에서, 실리콘 기판 내의 갭은 실리콘 기판을 선택적으로 에칭한 다음에 실리콘 기판 상에 SiGe를 에피택셜 성장시킴으로써 형성된다.The present invention provides a method of manufacturing a device having improved performance characteristics. When stress layers such as SiGe layers, Si 3 N 4 layers, SiO 2 layers, or SiO x N y layers are epitaxially grown on the silicon layer, compressive stress is formed in the SiGe layer, and tension is formed in the silicon layer. do. In one embodiment of the invention, the silicon substrate has a gap in which the strained layer is grown. The gap includes a tunneled portion between the upper portion of the semiconductor substrate and the lower portion of the semiconductor substrate. More specifically, the upper portion has a lower surface, the lower portion has an upper surface, and the lower surface of the upper portion faces the upper surface of the lower portion. By having a strained layer substantially below the channel, and / or having a strained layer in the semiconductor substrate region substantially below the source and / or drain regions of the semiconductor device, stress is formed in the channel of the transistor. In an embodiment of the invention, a gap in the silicon substrate is formed by selectively etching the silicon substrate and then epitaxially growing SiGe on the silicon substrate.

장력 및/또는 압축 응력은 트랜지스터의 채널에 대한 성장 SiGe의 근접도에 따라 다르게 트랜지스터의 채널 내에 제공될 수 있다. 트랜지스터 아래의 실리콘 층을 선택적으로 에칭하고, 실리콘 층의 에칭된 부분 상에 SiGe를 선택적으로 성장시킴으로써, 장력은 NFET의 채널 내에 제공될 수 있고, 압축 응력은 PFET의 채널 내에 제공될 수 있다. 더구나, SiGe를 성장시키기 전에 트랜지스터 아래의 실리콘의 일부분을 선택적으로 에칭하여 응력을 구현함으로써, 본 발명은 분리 기반의 또는 라이너 기반의 방식보다 훨씬 더 큰, 게이트(예를 들어, 채널 영역) 아래의 실리콘 내의 응력 레벨을 제공한다.Tensile and / or compressive stresses may be provided in the channel of the transistor depending on the proximity of the growth SiGe to the channel of the transistor. By selectively etching the silicon layer under the transistor and selectively growing SiGe on the etched portion of the silicon layer, tension can be provided in the channel of the NFET, and compressive stress can be provided in the channel of the PFET. Furthermore, by selectively etching a portion of the silicon under the transistor prior to growing SiGe to implement stress, the present invention provides a method under the gate (eg, the channel region), which is much larger than the isolation based or liner based approach. Provide the stress level in the silicon.

본 발명에서, SiGe 층과 같은 응력 층은 예를 들어, 반도체 디바이스의 채널 내에 응력을 형성하기 위해 사용된다. SiGe 층이 반도체 층 상에 성장될 때, 주위 반도체 재료는 장력을 받게 되지만, 성장된 SiGe 층은 압축 응력을 받게 된다. 특히, 반도체 디바이스의 일부분은 장력 아래에 놓이고, SiGe 층은 실리콘 층과 다른 격자 구조를 갖기 때문에 압축 응력을 받게 된다. 더구나, SiGe 응력 층으로부터 비롯된 응력 레벨은 비교적 높다(1-2 Gpa 정도).In the present invention, a stress layer, such as a SiGe layer, is used, for example, to create stress in the channel of the semiconductor device. When the SiGe layer is grown on the semiconductor layer, the surrounding semiconductor material is under tension, but the grown SiGe layer is subjected to compressive stress. In particular, a portion of the semiconductor device is under tension, and the SiGe layer is subject to compressive stress because it has a different lattice structure than the silicon layer. Moreover, the stress level resulting from the SiGe stress layer is relatively high (about 1-2 Gpa).

그러나, 상술된 바와 같이, 채널 영역 내의 장력은 NFET 구동 전류에 유익한 반면, 채널 영역 내의 압축 응력은 PFET 구동 전류에 유익하다. 특히, 장력은 PFET 구동 전류를 상당히 방해한다. 본 발명에서, PFET 내의 응력은 PFET의 성능을 개선하기 위해 장력보다는 압축 응력으로 이루어진다. 그러므로, 본 발명은 디바이스의 성능을 개선하기 위해, PFET의 채널을 따라서는 세로 압축 응력을 제공하고, NFET의 채널을 따라서는 장력을 제공하는 방법을 제공한다.However, as mentioned above, the tension in the channel region is beneficial for the NFET drive current, while the compressive stress in the channel region is beneficial for the PFET drive current. In particular, tension significantly interferes with the PFET drive current. In the present invention, the stress in the PFET is made of compressive stress rather than tension to improve the performance of the PFET. Therefore, the present invention provides a method of providing longitudinal compressive stress along the channel of a PFET and tension along the channel of the NFET to improve device performance.

도 1은 PFET 및 NFET의 성능을 개선하기 위해 요구된 응력 상태를 도시한 것이다(Wang 등의 IEEE Tran. Electron Dev., v.50, 529페이지(2003년) 참조). 도 1에서, NFET 및 PFET는 소스 영역, 게이트 영역 및 드레인 영역을 갖는 것으로 도시된다. NFET 및 PFET는 장력을 나타내기 위해 활성 영역에서 바깥쪽으로 향하는 화살표를 갖는 것으로 도시된다. PFET 쪽으로 안으로 향하는 화살표는 압축 응력을 나타낸다. 더욱 구체적으로, NFET로부터 뻗어가는 것을 도시한 바깥쪽으로 향하는 화살표는 디바이스의 가로 방향 및 세로 방향으로 요구되는 장력을 나타낸다. 한편, PFET와 관련하여 도시된 안쪽으로 향하는 화살표는 요구된 세로 압축 응력을 나타낸다.1 shows the stress states required to improve the performance of PFETs and NFETs (see Wang et al., IEEE Tran. Electron Dev., V. 50, page 529 (2003)). In FIG. 1, NFETs and PFETs are shown having a source region, a gate region and a drain region. NFETs and PFETs are shown with arrows pointing outwards in the active region to indicate tension. Arrows pointing inward toward the PFET indicate compressive stress. More specifically, outward pointing arrows showing stretching from the NFETs indicate the required tension in the transverse and longitudinal directions of the device. On the other hand, the inward pointing arrows shown in relation to the PFET indicate the required longitudinal compressive stress.

디바이스 구동 전류에 영향을 미치는데 필요한 응력의 범위는 수백 MPa 내지 수 Gpa 정도의 범위이다. 각 디바이스의 활성 영역의 폭 및 길이는 각각 "W" 및 "L"로 표시된다. 세로 또는 가로 응력 성분의 각각은 두개의 디바이스(즉, NFET 및 PFET)에 성능 향상을 제공하도록 개별적으로 맞춤화될 수 있다.The stress required to affect the device drive current ranges from a few hundred MPa to several Gpa. The width and length of the active area of each device are indicated by "W" and "L", respectively. Each of the longitudinal or transverse stress components can be individually customized to provide performance improvements for the two devices (ie, NFETs and PFETs).

도 2a 내지 2j는 본 발명에 따른 n형 디바이스를 형성하는 예시적인 공정을 도시한 것이다. 도 2a에 도시된 바와 같이, 패터닝된 포토-레지스터 층(205)은 실 리콘 기판(200) 위에 막형성되고, 실리콘 기판(200)의 노출된 부분은, 예를 들어 Ge, As, B, In 또는 Sb로 도핑된다. 예를 들어, Ge의 도핑 농도는, 예를 들어 약 1 x 1014 Ge/cm2 내지 1 x 1016 Ge/cm2일 수 있다. 도핑된 영역(207)은 반도체 기판(200) 내에 형성된다.2A-2J illustrate an exemplary process for forming an n-type device in accordance with the present invention. As shown in FIG. 2A, the patterned photo-resistor layer 205 is formed over the silicon substrate 200, and the exposed portion of the silicon substrate 200 is, for example, Ge, As, B, In. Or doped with Sb. For example, the doping concentration of Ge may be, for example, about 1 × 10 14 Ge / cm 2 to 1 × 10 16 Ge / cm 2 . The doped region 207 is formed in the semiconductor substrate 200.

그 다음, 도 2b에 도시된 바와 같이, 패터닝된 포토-레지스트 층(205)은 제거되고, 예를 들어 질화물로 이루어진 마스크(210)는 반도체 기판(200)의 표면 상에 막형성된다. 마스크(210)는 그 아래의 반도체 기판을 반응성 이온 에칭(RIE) 동안에 에칭되지 않게 보호한다. 일반적으로, 마스크(210)는 RIE를 통해 얕은 트렌치가 형성될 반도체 기판의 부분들을 노출시킨다.Then, as shown in FIG. 2B, the patterned photo-resist layer 205 is removed, for example a mask 210 made of nitride is formed on the surface of the semiconductor substrate 200. The mask 210 protects the semiconductor substrate below it from being etched during reactive ion etching (RIE). In general, the mask 210 exposes portions of the semiconductor substrate through which the shallow trenches will be formed.

도 2c에 도시된 바와 같이, RIE는 반도체 기판(200) 내에 그루브(groove)/트렌치(215)를 형성하기 위해 실행된다. RIE 단계의 결과로서, 도핑된 반도체 영역의 측벽 부분(217)이 형성된다. 특히, 형성된 그루브/트렌치의 위치는 그루브/트렌치(215)가 형성될 때, 도핑된 반도체 기판 영역이 노출되도록, 도핑된 반도체 영역(207)에 적어도 부분적으로 겹쳐진다. 더구나, 후술되는 바와 같이, 변형층이 형성된 후에, 반도체 기판(200) 상에서 서로 인접한 디바이스들이 서로 전기적으로 절연되도록, 산화물 재료가 트렌치를 채우기 위해 막형성된다.As shown in FIG. 2C, RIE is performed to form grooves / trench 215 in semiconductor substrate 200. As a result of the RIE step, sidewall portions 217 of the doped semiconductor region are formed. In particular, the location of the formed grooves / trench overlaps at least partially with the doped semiconductor region 207 such that when the groove / trench 215 is formed, the doped semiconductor substrate region is exposed. Moreover, as will be described later, after the strained layer is formed, an oxide material is filmed to fill the trenches so that devices adjacent to each other on the semiconductor substrate 200 are electrically insulated from each other.

그루브/트렌치(215)가 형성된 후, 습식 에칭 및/또는 건식 에칭은 도핑된 반도체(207)를 선택적으로 제거하기 위해 실행된다. 일반적으로, 트렌치의 깊이는 반도체 기판의 상부 표면(231)(도 2f)으로부터 약 1000 옹스트롬 내지 약 5000 옹스 트롬 정도일 것이고, 트랜지스터의 채널 영역의 두께는 전형적으로 약 30 옹스트롬 내지 약 200 옹스트롬이다.After the groove / trench 215 is formed, wet etching and / or dry etching is performed to selectively remove the doped semiconductor 207. In general, the depth of the trench will be on the order of about 1000 angstroms to about 5000 angstroms from the top surface 231 (FIG. 2F) of the semiconductor substrate, and the thickness of the channel region of the transistor is typically from about 30 angstroms to about 200 angstroms.

도 2d에 도시된 바와 같이, 에칭은 터널형 갭(219)이 반도체 기판(200)의 상부 부분(221)과 반도체 기판(200)의 하부 부분(223) 사이에 형성될 때까지 실행될 수 있다. 전형적으로, 약 300 옹스트롬 내지 약 5000 옹스트롬의 깊이를 갖는 부분은 반도체 기판(200)으로부터 에칭된다. n형 트랜지스터의 경우에는, 디바이스의 채널의 실질적으로 바로 아래 및/또는 바로 아래에 변형층을 형성하는 것이 요구된다. 그러므로, n형 트랜지스터의 경우에는, 디바이스의 채널 아래에 적어도 하나의 갭이 있다.As shown in FIG. 2D, etching may be performed until a tunneled gap 219 is formed between the upper portion 221 of the semiconductor substrate 200 and the lower portion 223 of the semiconductor substrate 200. Typically, portions having a depth of about 300 angstroms to about 5000 angstroms are etched from the semiconductor substrate 200. In the case of an n-type transistor, it is required to form a strained layer substantially directly below and / or just below the channel of the device. Therefore, in the case of an n-type transistor, there is at least one gap below the channel of the device.

다음에, 도 2e에 도시된 바와 같이, 스페이서 재료(225)는 반도체 기판(200) 위에 막형성된다. 스페이서 재료는 예를 들어, 실리콘 카바이드(SiC), 산질화물(oxynitride)과 같은 비등각 막, 또는 산화막 및 질화막과 같은 막 적층체(film stack)일 수 있다. 이 스페이서 재료(225)는 상부 부분(221) 아래의 반도체 기판 부분 이외의 반도체 기판(200)의 노출된 부분 상에 형성된다.Next, as shown in FIG. 2E, a spacer material 225 is formed over the semiconductor substrate 200. The spacer material may be, for example, silicon carbide (SiC), an isotropic film such as oxynitride, or a film stack such as oxide and nitride film. This spacer material 225 is formed on the exposed portion of the semiconductor substrate 200 other than the semiconductor substrate portion below the upper portion 221.

도 2f에 도시된 바와 같이, 변형층(227)은 반도체 기판(200)의 터널형 갭(219) 내에 에피택셜 성장된다. 도 2f에 도시된 바와 같이, 변형층(227)은 반도체 기판(200)의 상부 부분(221)과 하부 부분(223) 사이에 일반적으로 형성되는데, 반도체 기판(200)의 상부 부분(221)은 원래의 반도체 기판(즉, 제거/변동 및 막형성이 되지 않은) 부분이다. 즉, 변형층(227)은 반도체 기판(200)의 노출된 표면 상에 형성되도록, 일반적으로 선택적 막형성을 통해 형성된다. 더구나, 변형층(227) 이 터널형 갭 내에 형성되기 때문에, 상부 부분(221)의 상부 표면(231)은 변형되지 않고(즉, 원래대로 있고), 상당히 평탄하다.As shown in FIG. 2F, the strained layer 227 is epitaxially grown in the tunneled gap 219 of the semiconductor substrate 200. As shown in FIG. 2F, the strained layer 227 is generally formed between the upper portion 221 and the lower portion 223 of the semiconductor substrate 200, where the upper portion 221 of the semiconductor substrate 200 is formed. The original semiconductor substrate (i.e., no removal / change and film formation). That is, the strained layer 227 is generally formed through selective film formation so as to be formed on the exposed surface of the semiconductor substrate 200. Moreover, because the strained layer 227 is formed in the tunnel-like gap, the upper surface 231 of the upper portion 221 is undeformed (ie, intact) and fairly flat.

변형층은, 예를 들어 실리콘 게르마늄 또는 실리콘 카바이드일 수 있다. 변형층은 임의의 공지된 적절한 재료로 이루어질 수 있다는 것을 알기 바란다.The strained layer can be, for example, silicon germanium or silicon carbide. Note that the strained layer can be made of any known suitable material.

변형층(227)이 형성된 후, 스페이서 재료(225)는 습식 화학제품을 사용하여 제거된다. 임의의 공지된 적용가능한 방법이 스페이서 재료(225)를 제거하기 위해 사용될 수 있다는 것을 알기 바란다. 스페이서 재료가 없는 결과적으로 얻어진 디바이스는 도 2g에 도시된다.After the strained layer 227 is formed, the spacer material 225 is removed using wet chemicals. Note that any known applicable method can be used to remove the spacer material 225. The resulting device without spacer material is shown in FIG. 2G.

상술된 바와 같이, 그리고 도 2h에 도시된 바와 같이, 그 다음에 산화물 재료(233)는 트렌치를 채워서, 그 디바이스를 임의의 인접한 디바이스로부터 전기적으로 절연시키기 위해 막형성된다. 산화물 재료로 트렌치를 채운 후, 마스크(210)는 임의의 공지된 적절한 방법을 사용하여 제거된다. 마스크(210)가 제거된 후, 화학적 기계적 연마(CMP)는 반도체 기판(200)의 상부 표면(231)을 충분히 평탄하게 하기 위해 실행된다.As described above, and as shown in FIG. 2H, the oxide material 233 is then filmed to fill the trench and electrically insulate the device from any adjacent device. After filling the trench with the oxide material, the mask 210 is removed using any known suitable method. After the mask 210 is removed, chemical mechanical polishing (CMP) is performed to sufficiently level the top surface 231 of the semiconductor substrate 200.

다음에, 반도체 디바이스는 공지된 방법을 사용하여 더욱 제조된다. 예를 들어, 도 2i에 도시된 바와 같이, 게이트 산화물 층(235)은 반도체 기판(200)의 상부 표면(231) 상에 성장된다. 약 10 옹스트롬 내지 약 100 옹스트롬(Å)의 게이트 산화물 층(235)이 일반적으로 성장된다. 게이트 산화물 층(235) 상에서, 폴리실리콘 층(236)은 게이트 전극(237)을 형성하기 위해 일반적으로 화학 기상 막형성(CVD)을 사용하여 약 500 옹스트롬 내지 약 1500 옹스트롬의 두께로 막형성된다. 패터닝된 포토레지스트 층(도시되지 않음)은 게이트 전극을 정하기 위해 사용된다. 그 다음, 얇은 산화물 층(도시되지 않음)은 나머지 폴리실리콘 상에 성장된다. 나중에 제거되는 패터닝된 포토레지스트 층(도시되지 않음)은 n형 및 p형 트랜지스터를 연속적으로 팁(tip) 주입하기 위해(그리고 반대 도핑 주입물을 헤일로우(halo) 주입하기 위해) 사용된다. n형 트랜지스터의 경우, 예를 들어, 매우 얕고 낮은 도즈 주입물인 비소 이온은 p-팁을 형성하기 위해 사용될 수 있다(한편, 예를 들어 붕소 주입물은 헤일로용으로 사용될 수 있다). p형 트랜지스터의 경우, (도 3a-3d와 관련하여 후술되는 바와 같이), 예를 들어, 매우 얕고 낮은 도즈 주입물인 BF2 이온은 n-팁을 형성하기 위해 사용될 수 있다(한편, 예를 들어 비소 주입물은 헤일로용으로 사용될 수 있다).Next, the semiconductor device is further manufactured using a known method. For example, as shown in FIG. 2I, gate oxide layer 235 is grown on top surface 231 of semiconductor substrate 200. A gate oxide layer 235 of about 10 angstroms to about 100 angstroms is generally grown. On the gate oxide layer 235, the polysilicon layer 236 is generally formed to a thickness of about 500 angstroms to about 1500 angstroms using chemical vapor deposition (CVD) to form the gate electrode 237. A patterned photoresist layer (not shown) is used to define the gate electrode. A thin oxide layer (not shown) is then grown on the remaining polysilicon. A patterned photoresist layer (not shown) that is later removed is used to continuously inject n- and p-type transistors (and to halo inject opposite doping implants). For n-type transistors, for example, arsenic ions, which are very shallow and low dose implants, can be used to form p-tips (on the other hand, for example, boron implants can be used for halo). For p-type transistors (as described below in connection with FIGS. 3A-3D), for example, BF 2 ions, which are very shallow and low dose implants, can be used to form n-tips (on the other hand, for example Arsenic infusions can be used for halo).

다음에, 도 2j에 도시된 바와 같이, 스페이서(238)는 CVD를 사용하여 질화 실리콘 층(도시되지 않음)을 약 100 옹스트롬 내지 약 1000 옹스트롬의 두께로 막형성한 다음에, 게이트의 측벽들 이외의 영역들로부터 질화물을 에칭함으로써 형성될 수 있다. 게이트 산화물 층(235), 게이트 전극(237) 및 스페이서(238)의 조합은 게이트 적층체로 언급될 수 있다.Next, as shown in FIG. 2J, the spacer 238 is formed using a CVD to form a silicon nitride layer (not shown) to a thickness of about 100 angstroms to about 1000 angstroms, followed by the gate sidewalls. It can be formed by etching the nitride from the regions of. The combination of gate oxide layer 235, gate electrode 237 and spacer 238 may be referred to as a gate stack.

다음 공정 단계 이전에 제거되는 패터닝된 포토레지스터 층(도시되지 않음)은 트랜지스터의 소스/드레인 영역을 연속하여 생성하기 위해 사용된다. n형 트랜지스터의 경우, 예를 들어, 얕고 높은 도즈의 비소 이온은 소스/드레인 영역(240 및 241)을 형성하기 위해 사용될 수 있는 반면, p형 트랜지스터는 대응하는 포토레 지스트 층으로 피복될 수 있다. 상술된 바와 같이, 본 발명에 따른 방법에서, 소스 및 드레인 영역(240 및 241)은 반도체 기판(200)의 상부 부분 내에 형성된다(즉, 제거 및 재형성되지 않는다). p형 트랜지스터의 경우, (도 3a-3d와 관련하여 후술되는 바와 같이), 예를 들어, 얕고 높은 도즈의 BF2 이온은 소스/드레인 영역(30)을 형성하기 위해 사용될 수 있는 반면, p형 트랜지스터는 대응하는 포토레지스트 층으로 피복된다. 그 다음, 어닐닝은 주입물을 활성화하기 위해 사용된다. 그 다음, 구조물 상의 노출된 산화물은 트랜지스터의 소스, 게이트 및 드레인 영역 내의 베어(bare) 실리콘을 노출시키기 위해 HF 내에 구조물을 디핑(dipping)함으로써 스트립된다.A patterned photoresist layer (not shown) that is removed before the next process step is used to continuously create the source / drain regions of the transistor. For n-type transistors, for example, shallow and high dose arsenic ions can be used to form source / drain regions 240 and 241, while p-type transistors can be covered with corresponding photoresist layers. . As described above, in the method according to the present invention, the source and drain regions 240 and 241 are formed (ie, not removed and reformed) in the upper portion of the semiconductor substrate 200. For p-type transistors (as described below in connection with FIGS. 3A-3D), for example, shallow and high dose BF 2 ions can be used to form the source / drain region 30, while p-type The transistor is covered with a corresponding photoresist layer. Annealing is then used to activate the implant. The exposed oxide on the structure is then stripped by dipping the structure into HF to expose bare silicon in the source, gate and drain regions of the transistor.

여전히 도 2j를 참조하면, 금속은 실리사이드(242)를 형성하기 위해 웨이퍼 표면을 가로질러 약 30 옹스트롬 내지 약 200 옹스트롬의 두께로 막형성된다. 실리사이드는 Co, Hf, Mo, Ni, Pd2, Pt, Ta, Ti, W 및 Zr과 같은 임의의 막형성된 물질과 하부와의 반응으로부터 형성될 수 있다. 막형성된 금속이 실리콘과 접촉하는 소스, 드레인 및 게이트 영역과 같은 영역 내에서, 막형성된 금속은 실리콘과 반응하여 실리사이드를 형성한다. 다음에, 구조물은 막형성된 실리사이드 재료가 노출된 폴리실리콘 또는 실리콘과 반응할 수 있게 하기 위해 약 300℃ 내지 약 1000℃의 온도로 가열된다. 소결(sintering) 동안에, 실리사이드는 금속이 실리콘 또는 폴리실리콘과 직접 접촉하는 영역 내에만 형성된다. 그외 다른 영역(즉, 막형성된 금속이 실리콘과 접촉하지 않는 영역)에서, 막형성된 금속은 변하지 않고 그대로 있다. 이 공정은 실리사이드를 노출된 실리콘에 맞춰 정렬시키는데, 이 공정을 "자기-정렬 실리사이드" 또는 살리사이드(salicide)라 한다. 다음, 반응하지 않은 금속은 습식 에칭을 사용하여 제거되고, 형성된 실리사이드는 그대로 남는다.Still referring to FIG. 2J, metal is deposited to a thickness of about 30 angstroms to about 200 angstroms across the wafer surface to form silicide 242. The silicide may be formed from the reaction with any filmed material such as Co, Hf, Mo, Ni, Pd 2, Pt, Ta, Ti, W and Zr with the bottom. In regions such as source, drain, and gate regions where the filmed metal is in contact with silicon, the filmed metal reacts with silicon to form silicides. The structure is then heated to a temperature of about 300 ° C. to about 1000 ° C. to allow the filmed silicide material to react with the exposed polysilicon or silicon. During sintering, the silicide is formed only in the region where the metal is in direct contact with silicon or polysilicon. In other regions (ie, regions in which the filmed metal does not contact silicon), the filmed metal remains unchanged. This process aligns the silicide with the exposed silicon, which is referred to as "self-aligned silicide" or salicide. The unreacted metal is then removed using wet etching, and the silicide formed is left intact.

본 발명에 따른 방법에서는, 반도체 디바이스의 소스 및 드레인 영역이 변동되지 않는(즉, 에칭 및 재형성되지 않는) 반도체 기판의 부분 상에 형성되기 때문에, 표면은 코발트 실리사이드와 같은 코발트 실리사이드 생성에 더욱 유리하다. 더 나아가, 일반적으로 산화물 충전(도시되지 않음) 다음의 화학적 기계적 연마는 표면을 평탄화하기 위해 사용된다. 제조 공정은 설계 스펙에 따라 필요한 만큼 진행된다.In the method according to the invention, since the source and drain regions of the semiconductor device are formed on portions of the semiconductor substrate that are not varied (i.e., not etched and reformed), the surface is more advantageous for producing cobalt silicides such as cobalt silicides. Do. Furthermore, chemical mechanical polishing following oxide filling (not shown) is generally used to planarize the surface. The manufacturing process proceeds as needed according to the design specifications.

도 3a 내지 3d는 본 발명에 따른 p형 디바이스를 형성하는 예시적인 공정을 도시한 것이다. p형 디바이스를 형성하는 공정은 도 2a-2j와 관련하여 설명된, n형 디바이스를 형성하는 공정과 유시하므로, 다음 설명은 주로 두개의 공정의 차이점에 초점을 맞추겠다. 아래에 설명되지 않는 p형 디바이스를 형성하는 방법의 상세는 n형 디바이스를 형성하는 방법의 상기 설명에서 찾아볼 수 있다.3A-3D illustrate exemplary processes for forming a p-type device in accordance with the present invention. Since the process of forming the p-type device is similar to the process of forming the n-type device described with reference to Figs. 2A-2J, the following description will mainly focus on the differences between the two processes. Details of the method of forming the p-type device not described below can be found in the above description of the method of forming the n-type device.

도 3a에 도시된 바와 같이, 패터닝된 포토-레지스트 층(305)이 막형성된다. p형 디바이스의 경우, 반도체 디바이스의 채널 아래에 있게 될 반도체 기판(300)의 부분(307)은 또한 패터닝된 포토-레지스트 층(305)으로 피복된다. 그러므로, p형 디바이스의 경우, 도 3b에 도시된 바와 같이, 반도체 기판의 도핑된 영역이 갭(315)을 형성하기 위해 선택적으로 에칭될 때, 반도체 기판(300)의 부분(308)은 그대로 남아 있는다. 구조물이 형성된 후, 반도체 기판의 이 부분(308)은 실질적으 로 반도체 디바이스의 채널의 바로 아래이다.As shown in FIG. 3A, a patterned photo-resist layer 305 is formed. For the p-type device, the portion 307 of the semiconductor substrate 300 that will be under the channel of the semiconductor device is also covered with a patterned photo-resist layer 305. Therefore, for the p-type device, as shown in FIG. 3B, when the doped region of the semiconductor substrate is selectively etched to form the gap 315, the portion 308 of the semiconductor substrate 300 remains intact. There is. After the structure is formed, this portion 308 of the semiconductor substrate is substantially directly under the channel of the semiconductor device.

다음에, 도 3c에 도시된 바와 같이, 변형층(327)은 반도체 기판(300)의 남아있는 상부 부분(301)과 하부 부분(302) 사이의 갭 내에 성장된다. 그 다음, 도 3d에 도시된 바와 같이, 산화물 재료는 갭/트렌치(315)를 채우기 위해 막형성된다. n형 디바이스를 형성하는 공정과 유사하게, 게이트 산화물(335)은 반도체 기판의 상부 표면 상에 막형성되고, 게이트 전극(337), 스페이서(338), 소스/드레인 영역(340 및 341) 및 실리사이드 접촉부(342)가 형성된다.Next, as shown in FIG. 3C, the strained layer 327 is grown in the gap between the remaining upper portion 301 and the lower portion 302 of the semiconductor substrate 300. Next, as shown in FIG. 3D, an oxide material is formed to fill the gap / trench 315. Similar to the process of forming an n-type device, gate oxide 335 is formed on the upper surface of the semiconductor substrate, and the gate electrode 337, spacer 338, source / drain regions 340 and 341 and silicide A contact 342 is formed.

도 4는 본 발명에 따른 트랜지스터의 하향도를 도시한 것이다. 도 4의 라인 A-A를 따라 절취한 단면도는 도 2i에 도시된 구조이고, 도 4의 라인 B-B를 따라 절취한 단면도는 도 2j에 도시된 구조이다. 도 4에 도시된 바와 같이, 게이트 전극(242)은 스페이서(238)와 함께 반도체 기판(200) 위에 위치한다. 산화물 충전부(233)(즉, 얕은 트렌치 분리 구조)는 반도체 기판(200)의 소스 및 드레인 영역(240 및 241)을 분리시킨다.4 illustrates a top down view of a transistor according to the present invention. A cross-sectional view taken along line A-A of FIG. 4 is a structure shown in FIG. 2I, and a cross-sectional view taken along line B-B of FIG. 4 is a structure shown in FIG. 2J. As shown in FIG. 4, the gate electrode 242 is disposed on the semiconductor substrate 200 together with the spacer 238. An oxide charge part 233 (that is, a shallow trench isolation structure) separates the source and drain regions 240 and 241 of the semiconductor substrate 200.

도 5는 본 발명에 따른 반도체 기판의 단면을 도시한 것이다. 도 5에 도시된 반도체 기판의 표현은 주사 전자 현미경을 사용하여 얻어졌다. 특히, 도 5는 도핑된 실리콘이 반도체 기판 내에 터널형 갭(219)을 형성하기 위해 선택적으로 제거된 후의 실리콘 기판을 도시한 것이다. 도 5에 도시된 바와 같이, 반도체 기판의 상부 부분의 하부 표면, 및 반도체 기판의 하부 부분의 상부 표면은 반도체 기판 내의 갭의 일부분을 정한다. 반도체 기판 내의 갭은 반도체 기판의 상부 표면을 따르는 개구부를 포함할 수 있다.5 is a cross-sectional view of a semiconductor substrate according to the present invention. The representation of the semiconductor substrate shown in FIG. 5 was obtained using a scanning electron microscope. In particular, FIG. 5 illustrates a silicon substrate after the doped silicon has been selectively removed to form a tunneled gap 219 in the semiconductor substrate. As shown in FIG. 5, the lower surface of the upper portion of the semiconductor substrate, and the upper surface of the lower portion of the semiconductor substrate, define a portion of the gap in the semiconductor substrate. The gap in the semiconductor substrate may include an opening along the top surface of the semiconductor substrate.

본 발명에 따른 방법의 다른 실시예에서, 반도체 기판의 선택적 부분이 에칭을 통해 제거될 수 있도록, 예를 들어 Ge로 반도체 기판을 선택적으로 도핑하는 대신에, SiGe 층과 같은 층을 성장시킨 다음에 예를 들어 실리콘 에피택셜 층을 성장시킬 수 있다. 그 다음, 상술된 도핑 방법과 유사하게, SiGe의 측벽은 반도체 기판 내에 갭을 형성하기 위해 노출된 다음에 선택적으로 에칭될 수 있다.In another embodiment of the method according to the invention, instead of selectively doping the semiconductor substrate with, for example, Ge, such that a selective portion of the semiconductor substrate can be removed by etching, a layer such as a SiGe layer is then grown For example, a silicon epitaxial layer can be grown. Then, similar to the doping method described above, the sidewalls of the SiGe may be selectively etched after being exposed to form gaps in the semiconductor substrate.

도 1과 관련하여 상술된 바와 같이, PFET에서, 세로 압축 응력이 요구된다. 요구된 압축 응력/장력의 전형적인 범위는 수백 MPa 내지 수 GPa 정도이다. 예를 들어, 약 100 MPa 내지 약 2 또는 3 GPa의 응력이 일반적으로 요구된다. 본 발명은 PFET 및 NFET 디바이스의 채널 내에 각각 매우 높은 압축 응력 및 장력을 생성할 수 있다.As described above with respect to FIG. 1, in a PFET, longitudinal compressive stress is required. Typical ranges of compressive stress / tension required are on the order of several hundred MPa to several GPa. For example, a stress of about 100 MPa to about 2 or 3 GPa is generally required. The present invention can produce very high compressive stresses and tensions in the channels of PFET and NFET devices, respectively.

NFET의 채널에 장력을 제공하고, PFET의 채널에 압축 응력을 제공함으로써, 각 디바이스의 채널을 따르는 전하 이동도는 증대된다. 그러므로, 상술된 바와 같이, 본 발명은 반도체 디바이스의 채널의 실질적으로 바로 아래 또는 반도체 디바이스의 소스 및/또는 드레인 영역의 사싱살 바로 아래에 변형층을 제공함으로써 채널의 세로 방향을 따라 압축 응력을 제공하는 방법을 제공한다. 본 발명은 또한 변형층이 형성되는 갭의 위치 및/또는 깊이를 조정함으로써 트랜지스터 채널 내의 응력 레벨을 최적화하는 방법을 제공한다.By providing tension to the channel of the NFET and compressive stress to the channel of the PFET, the charge mobility along the channel of each device is increased. Therefore, as described above, the present invention provides compressive stress along the longitudinal direction of the channel by providing a strained layer substantially directly below the channel of the semiconductor device or just below the sashes of the source and / or drain regions of the semiconductor device. Provide a way to. The invention also provides a method of optimizing the stress level in the transistor channel by adjusting the position and / or depth of the gap in which the strained layer is formed.

본 발명은 실시예들과 관련하여 설명되었지만, 본 분야에 숙련된 기술자들은 본 발명이 첨부된 청구범위의 정신 및 범위 내에서 변형되어 실시될 수 있다는 것을 알 수 있을 것이다.While the invention has been described in connection with embodiments, those skilled in the art will recognize that the invention may be practiced with modifications within the spirit and scope of the appended claims.

Claims (36)

n형 디바이스 및 p형 디바이스를 포함하는 디바이스를 제조하는 방법으로서,A method of manufacturing a device comprising an n-type device and a p-type device, 반도체 기판의 일부분을 도핑하는 단계와;Doping a portion of the semiconductor substrate; 상기 반도체 기판의 도핑된 부분 중 적어도 일부분을 제거함으로써 상기 반도체 기판 내에 갭을 형성하는 단계와; Forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate; 상기 반도체 기판 내의 갭의 적어도 일부분에 변형층(strain layer)을 성장시키는 단계Growing a strain layer on at least a portion of the gap in the semiconductor substrate 를 포함하는 디바이스 제조 방법.Device manufacturing method comprising a. 제1항에 있어서, 상기 변형층은 상기 n형 디바이스의 채널의 실질적으로 바로 아래에 있는 적어도 일부분 상에 성장되는 것인 디바이스 제조 방법.The method of claim 1, wherein the strained layer is grown on at least a portion substantially below the channel of the n-type device. 제1항에 있어서, 상기 변형층은 상기 p형 디바이스의 소스 영역 또는 드레인 영역 중 적어도 한 영역의 실질적으로 바로 아래에 있는 적어도 일부분 상에 성장되는 것인 디바이스 제조 방법.The method of claim 1, wherein the strained layer is grown on at least a portion that is substantially directly below at least one of a source region or a drain region of the p-type device. 제3항에 있어서, 상기 변형층은 상기 p형 디바이스의 채널 아래에 성장되지 않는 것인 디바이스 제조 방법.The method of claim 3, wherein the strained layer is not grown under a channel of the p-type device. 제1항에 있어서, 상기 반도체 기판 상에 패터닝된 포토-레지스트 층을 막형성시키는 단계를 더 포함하고, 상기 막형성 단계는 상기 p형 디바이스의 채널 아래에 있는 상기 반도체 기판의 일부분을 피복하는 포토-레지스트 층을 막형성하는 단계를 포함하는 것인 디바이스 제조 방법.10. The method of claim 1, further comprising film forming a patterned photo-resist layer on the semiconductor substrate, the film forming step covering a portion of the semiconductor substrate under the channel of the p-type device. Forming a resist layer. 제5항에 있어서, 상기 포토-레지스트 층은 상기 n형 디바이스의 채널 아래에 있는 상기 반도체 기판의 일부분을 노출시키는 것인 디바이스 제조 방법.6. The method of claim 5, wherein the photo-resist layer exposes a portion of the semiconductor substrate under the channel of the n-type device. 제1항에 있어서, 상기 갭은 상기 n형 디바이스의 채널 아래에 형성된 터널인 것인 디바이스 제조 방법.The method of claim 1, wherein the gap is a tunnel formed below a channel of the n-type device. 제1항에 있어서, 상기 패터닝되어 막형성된 포토-레지스트 층을 제거하는 단계를 더 포함하는 디바이스 제조 방법.The method of claim 1, further comprising removing the patterned filmed photo-resist layer. 제8항에 있어서, 상기 반도체 기판 상에 마스크를 막형성하는 단계를 더 포함하는 디바이스 제조 방법.The method of claim 8, further comprising forming a mask on the semiconductor substrate. 제9항에 있어서, 상기 반도체 기판의 일부분이 피복되고, 상기 반도체 기판의 일부분이 노출되도록, 상기 막형성된 마스크를 패터닝하는 단계를 더 포함하는 디바이스 제조 방법.10. The method of claim 9, further comprising patterning the filmed mask such that a portion of the semiconductor substrate is covered and a portion of the semiconductor substrate is exposed. 제10항에 있어서, 상기 갭 형성 단계는 상기 반도체 기판의 노출된 부분을 에칭하여 상기 반도체 기판의 도핑 영역의 적어도 일부분의 측벽을 선택적으로 노출시키는 단계를 포함하는 디바이스 제조 방법.The method of claim 10, wherein forming the gap comprises etching exposed portions of the semiconductor substrate to selectively expose sidewalls of at least a portion of a doped region of the semiconductor substrate. 제11항에 있어서, 상기 반도체 기판 상에 스페이서 재료를 막형성하는 단계를 더 포함하는 디바이스 제조 방법.12. The method of claim 11, further comprising forming a spacer material on the semiconductor substrate. 제12항에 있어서, 상기 스페이서 재료의 막형성 단계는 상기 갭의 노출된 부분 상에 스페이서 재료를 막형성하는 단계를 포함하는 것인 디바이스 제조 방법.The method of claim 12, wherein forming the spacer material comprises forming a spacer material on the exposed portion of the gap. 제13항에 있어서, 상기 갭의 노출되지 않은 부분을 산화물 재료로 채우는 단계를 더 포함하는 디바이스 제조 방법.The method of claim 13, further comprising filling an unexposed portion of the gap with an oxide material. 제1항에 있어서, 상기 도핑 단계는 상기 반도체 기판을 Ge로 도핑하는 단계를 포함하는 것인 디바이스 제조 방법.The method of claim 1, wherein the doping comprises doping the semiconductor substrate with Ge. 제15항에 있어서, 상기 Ge의 도핑 농도는 약 1 x 1014 Ge/cm2 내지 약 1 x 1016 Ge/cm2인 것인 디바이스 제조 방법.The method of claim 15, wherein the doping concentration of Ge is about 1 × 10 14 Ge / cm 2 to about 1 × 10 16 Ge / cm 2 . 제1항에 있어서, 상기 도핑 단계는 상기 반도체 기판을 As, B, In 및 Sb 중의 적어도 하나로 도핑하는 단계를 포함하는 것인 디바이스 제조 방법.The method of claim 1, wherein the doping comprises doping the semiconductor substrate with at least one of As, B, In, and Sb. 제1항에 있어서, 상기 변형층의 성장 단계는 상기 반도체 기판의 갭의 적어도 일부분에 SiGe, Si3N4, SiO2 및 SioxNy 중 적어도 하나를 성장시키는 단계를 포함하는 것인 디바이스 제조 방법.The device of claim 1, wherein the growing of the strained layer comprises growing at least one of SiGe, Si 3 N 4 , SiO 2, and Sio x N y in at least a portion of the gap of the semiconductor substrate. Way. n형 디바이스 및 p형 디바이스를 포함하는 디바이스를 제조하는 방법으로서,A method of manufacturing a device comprising an n-type device and a p-type device, 반도체 기판 상에 변형층을 성장시키는 단계와;Growing a strained layer on the semiconductor substrate; 상기 변형층 상에 실리콘층을 성장시키는 단계와;Growing a silicon layer on the strained layer; 상기 반도체 기판 상으로부터 상기 실리콘층 및 상기 변형층의 적어도 일부분을 제거함으로써 상기 반도체 기판과 상기 실리콘층 사이에 갭을 형성하는 단계와;Forming a gap between the semiconductor substrate and the silicon layer by removing at least a portion of the silicon layer and the strain layer from the semiconductor substrate; 상기 갭 내에 변형층을 성장시키는 단계Growing a strained layer in the gap 를 포함하는 디바이스 제조 방법.Device manufacturing method comprising a. 제19항에 있어서, 상기 변형층은 상기 n형 디바이스의 채널의 실질적으로 바로 아래에 있는 적어도 일부분 상에 성장되는 것인 디바이스 제조 방법.20. The method of claim 19, wherein the strained layer is grown on at least a portion substantially below the channel of the n-type device. 제19항에 있어서, 상기 변형층은 상기 p형 디바이스의 소스 영역 또는 드레인 영역 중 적어도 한 영역의 실질적으로 바로 아래에 있는 적어도 일부분 상에 성장되는 것인 디바이스 제조 방법.20. The method of claim 19, wherein the strained layer is grown on at least a portion substantially immediately below at least one of a source region or a drain region of the p-type device. 제19항에 있어서, 상기 변형층은 상기 p형 디바이스의 채널 아래에 성장되지 않는 것인 디바이스 제조 방법.20. The method of claim 19, wherein the strained layer is not grown under a channel of the p-type device. 제19항에 있어서, 상기 변형층의 성장 단계는 상기 반도체 기판 상에 SiGe, Si3N4, SiO2 및 SioxNy 중 적어도 하나를 성장시키는 단계를 포함하는 것인 디바이스 제조 방법.The method of claim 19, wherein growing the strained layer comprises growing at least one of SiGe, Si 3 N 4 , SiO 2, and Sio x N y on the semiconductor substrate. 반도체 디바이스에 있어서,In a semiconductor device, 반도체 기판의 일부분 아래에서 연장하는 적어도 하나의 갭을 갖고 있는 반도체 기판과;A semiconductor substrate having at least one gap extending below a portion of the semiconductor substrate; 상기 반도체 기판 상의 게이트 적층체와;A gate stack on the semiconductor substrate; 상기 갭의 적어도 일부분에 형성된 변형층으로서, 상기 갭은 상기 반도체 기판의 일부분을 도핑한 다음 상기 반도체 기판의 도핑된 부분을 에칭하여 형성되는 것인 상기 변형층A strained layer formed on at least a portion of the gap, wherein the gap is formed by doping a portion of the semiconductor substrate and then etching a doped portion of the semiconductor substrate 을 포함하는 반도체 디바이스.Semiconductor device comprising a. 제24항에 있어서, 상기 갭은 상기 게이트 적층체를 형성하기 전에 형성되는 것인 반도체 디바이스.The semiconductor device of claim 24, wherein the gap is formed before forming the gate stack. 제24항에 있어서, 상기 반도체 디바이스는 Ge, As, B, In 및 Sb 중 적어도 하나로 도핑되는 것인 반도체 디바이스.The semiconductor device of claim 24, wherein the semiconductor device is doped with at least one of Ge, As, B, In, and Sb. 반도체 기판의 일부분 아래에서 연장되는 적어도 하나의 갭을 갖고 있는 반도체 기판과;A semiconductor substrate having at least one gap extending below a portion of the semiconductor substrate; 상기 반도체 기판 상의 게이트 적층체와;A gate stack on the semiconductor substrate; 하나의 갭의 적어도 일부분에 형성된 변형층으로서, 상기 반도체 디바이스의 소스 영역 및 드레인 영역 중 적어도 한 영역의 아래에만 형성되는 상기 변형층A strained layer formed on at least a portion of one gap, wherein the strained layer is formed only below at least one of a source region and a drain region of the semiconductor device 을 포함하는 반도체 디바이스.Semiconductor device comprising a. 제27항에 있어서, 상기 반도체 디바이스는 p형 디바이스인 것인 반도체 디바이스.28. The semiconductor device of claim 27, wherein the semiconductor device is a p-type device. 제27항에 있어서, 상기 변형층은 실리콘 게르마늄 및 실리콘 카바이드 중 적어도 하나로 형성되는 것인 반도체 디바이스.The semiconductor device of claim 27, wherein the strained layer is formed of at least one of silicon germanium and silicon carbide. 제27항에 있어서, 상기 변형층은 상기 반도체 기판의 하부 부분의 한 표면과, 상기 하부 부분의 한 표면에 대면하는 상기 반도체 기판의 상부 부분의 한 표면과의 사이에 있는 것인 반도체 디바이스.28. The semiconductor device of claim 27, wherein the strained layer is between one surface of a lower portion of the semiconductor substrate and one surface of an upper portion of the semiconductor substrate facing one surface of the lower portion. 제27항에 있어서, 상기 변형층은 약 1000 옹스트롬 내지 약 5000 옹스트롬의 두께를 갖는 것인 반도체 디바이스.The semiconductor device of claim 27, wherein the strained layer has a thickness of about 1000 angstroms to about 5000 angstroms. 제31항에 있어서, 채널의 두께는 약 30 옹스트롬 내지 약 200 옹스트롬인 것인 반도체 디바이스.The semiconductor device of claim 31, wherein the thickness of the channel is between about 30 angstroms and about 200 angstroms. 제27항에 있어서, 상기 변형층은 상기 반도체 디바이스의 소스 영역 및 드레인 영역 양쪽의 영역 아래에 형성되는 것인 반도체 디바이스.28. The semiconductor device of claim 27, wherein the strained layer is formed below a region of both a source region and a drain region of the semiconductor device. 제27항에 있어서, 상기 갭은 상기 반도체 기판의 상부 표면을 따르는 제1 폭, 및 상기 반도체 기판의 상부 표면 아래의 제2 폭을 갖는데, 상기 제2 폭은 상기 제1 폭보다 더 큰 것인 반도체 디바이스.28. The method of claim 27, wherein the gap has a first width along an upper surface of the semiconductor substrate and a second width below the upper surface of the semiconductor substrate, wherein the second width is greater than the first width. Semiconductor device. 제27항에 있어서, 약 100 MPa 내지 약 3 GPa의 압축 응력이 상기 디바이스의 채널 내에 존재하는 것인 반도체 디바이스.The semiconductor device of claim 27, wherein a compressive stress of about 100 MPa to about 3 GPa is present in the channel of the device. 제27항에 있어서, 상기 변형층은 SiGe, Si3N4, SiO2 및 SioxNy 중의 적어도 하나인 것인 반도체 디바이스.The semiconductor device of claim 27, wherein the strained layer is at least one of SiGe, Si 3 N 4 , SiO 2, and Sio x N y .
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