KR20060097808A - Method for manufacturing the semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can improve the gain characteristics and the operating frequency characteristics of parasitic BJTs formed parasitically during the formation of MOS transistors. Providing a semiconductor substrate defined by: forming a first well and a second well in the first region and a second region, respectively, and forming a gate electrode on the first well of the first region And an ion implantation process in the first well and the second well exposed to both sides of the gate electrode to form a source / drain region in the first well and separate the collectors in the second well. Forming a junction region, a base junction region and an emitter junction region, respectively, and contacting the second well exposed between the emitter junction region and a partial region so as to contact the emitter It provides a semiconductor device manufacturing method comprising the step of forming a metal silicide layer on the junction region and the second well.

MOS, BJT, Schottky diodes, base / emitter junction.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE}

1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 11 device isolation film

12a: P well 12b: first N well

12c: second N well 13: gate oxide film

14 polysilicon 15a: first gate electrode

15b: second gate electrode 16a, 16b: low concentration junction region

17: spacer 18a, 18b: high concentration junction region

19a, 19b: source / drain region 19c: collector junction region

19d: base junction region 19e: emitter junction region

20: silicide layer 21: interlayer insulating film

22: contact plug

23a to 23e: first to fifth metal wirings

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for simultaneously fabricating a bipolar junction transistor (BJT) and a metal oxide semiconductor (MOS) transistor on a single chip.

Generally, Bipolar Junction Transistors (hereinafter referred to as BJTs) are used in many semiconductor products because of the characteristics that Metal Oxide Semiconductors (hereinafter referred to as MOS) transistors do not have, such as amplification and thermal stability. . In this case, in order to manufacture the BJT and the MOS transistor on a single chip, the process for making the MOS transistor and the process for making the BJT must be separately performed. Therefore, the manufacturing process of the semiconductor device is complicated and the manufacturing cost increases.

In order to solve this problem, namely, to manufacture the BJT and the MOS transistor simultaneously on a single chip, conventionally, the parasitic BJT has been used through the process of forming the MOS transistor, but the parasitic BJT has a good gain characteristic. It is used for localized purposes.

Here, parasitic BJTs typically use PN junctions for emitter / base junctions, which have junctions with doped substrates with high forward turn-on voltages. Due to the high contact resistance, there is a problem that the gain characteristics are bad and the operating frequency is low.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device capable of improving the gain characteristics and operating frequency characteristics of parasitic BJTs formed parasitically during the formation of MOS transistors. Its purpose is to.

According to an aspect of the present invention, there is provided a semiconductor substrate including a first region and a second region, and a first well and a second well in the first region and the second region, respectively. Forming a gate electrode, forming a gate electrode on the first well of the first region, and performing an ion implantation process on the first well and the second well exposed to both sides of the gate electrode. Forming a source / drain region in the first well, and forming a collector junction region, a base junction region, and an emitter junction region respectively separated from each other in the second well; A method of manufacturing a semiconductor device includes forming a metal silicide layer on the emitter junction region and the second well such that a portion of the second well contacts the second well.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 5 are the same elements having the same function. Also, for convenience of description, a CMOS transistor consisting of NMOS and PMOS and a method of implementing a BJT on a single chip will be described.

First, as shown in FIG. 1, a P-type semiconductor substrate 10 having a plurality of device isolation layers 11 is provided. In this case, the device isolation layer 11 is formed through a shallow trench isolation (STI) process or a LOCal oxidation of silicon (LOCOS) process.

Subsequently, a mask process and a well ion implantation process are performed to form an NMOS region (NMOS), an PMOS region (PMOS) where a PMOS transistor is to be formed, and a BJT region (bjt) where a BJT is to be formed in the semiconductor substrate 10. define. For example, after forming a P well 12a (P-well) in an NMOS region (NMOS) by performing a mask process and a P well ion implantation process, a mask process and an N well ion implantation process are performed to perform a PMOS region (PMOS) and A first N well 12b (N-well) and a second N well 12c are formed in the BJT region bjt. At this time, the second N well 12c is formed by injecting N-type impurities having a concentration of 1.0E16 to 1.0E18 / cm 3, for example, As and Ph.

Next, as shown in FIG. 2, the second gate electrode 15b is formed in a predetermined region on the surface of the first N well 12b while the first gate electrode 15a is formed in the predetermined region on the surface of the P well 12a. Form. In this case, the first and second gate electrodes 15a and 15b are formed by depositing the gate oxide layer 13 and the polysilicon 14 on the entire surface of the semiconductor substrate 10 and then performing a dry etching process.

Subsequently, a low concentration impurity ion implantation process is performed to form a low concentration junction region in the P well 12a and the first N well 12b exposed to both sides of the first and second gate electrodes 15a and 15b. At this time, the low concentration junction region is formed of a low concentration N ⁻ junction region 16a and a low concentration P ⁻ junction region 16b.

Here, the N ⁻ junction region 16a is formed by performing an impurity ion implantation process using a photoresist pattern (not shown) having an open structure in which an NMOS region (NMOS) and a region in which the base of the BJT is to be formed are opened. In addition, the P ⁻ junction region 16b is an impurity ion implantation process using a photoresist pattern (not shown) having a structure in which a region of a PMOS region (PMOS) and a BJT collector and an emitter are formed. To form.

Subsequently, as shown in FIG. 3, after the insulating film is deposited along the steps of the upper portions of the entire structures on which the first and second gate electrodes 15a and 15b are formed, a dry etching process is performed to perform the first and second gate electrodes. Spacers 17 are formed on both side walls of 15a and 15b, respectively.

Subsequently, a high concentration impurity ion implantation process is performed to form high concentration junction regions in each of the N ^- junction regions 16a and P ^- junction regions 16b exposed to both sides of the spacer 17. At this time, the high concentration junction region forms a high concentration N ⁺ junction region 18a in the N ⁻ junction region 16a, and a high concentration P ⁺ junction region 18b in the P ⁻ junction region 16b. As a result, the first source / drain region 19a of the NMOS transistor and the second source / drain region 19b of the PMOS transistor are formed, and at the same time, the collector junction region 19c, the base junction region 19d, and the EJ of the BJT are formed. Contact region 19e is formed. At this time, the N ⁺ junction region 18a and P ⁺ junction region 18b of the BJT region BJT are formed at a high concentration of 1.0E20 / cm 3 or more.

4, the source / drain regions 19a and 19b exposed to silicon (Si), the collector junction region 19c of the BJT, and the base junction region 19d are subjected to a salicide process. ), The silicide layer 20 is formed on the emitter junction region 19e, the first gate electrode 15a, and the second gate electrode 15b. In this case, the silicide layer 20 may be formed using any one metal of Ti, Co, and Ni during the salicide process.

Here, the silicide layer 20 formed on the upper surface of the emitter junction region 19e serves as an anode of a Schottky diode, and the base junction formed in the same conductivity type as the second N well 12c. Region 19d serves as the cathode of the Schottky diode. In fact, the emitter junction region 19e is a region formed to prevent leakage current, and is formed by dividing it differently from the emitter region of BJT which is generally formed.

That is, the reason why the emitter junction region 19e is formed as a P type having a conductivity opposite to that of the second N well 12c is that when the reverse bias is applied to the emitter, the device isolation film ( This is to prevent leakage current flowing to 11).

As a result, according to a preferred embodiment of the present invention, the collector junction region 19c formed of P-type impurity ions functions as a collector, and the base junction region 19d formed of N-type impurity ions functions as a base. The metal silicide layer 20 on the junction region can form a parasitic BJT that functions as an emitter. As a result, a BJT having a P (collector) -N (base) -metal (emitter) structure is formed, so that the base-emitter has the same operating characteristics as a Schottky diode.

Hereinafter, the structure and characteristics of a general Schottky diode will be briefly described to help understand the description.

In general, a Schottky diode is a junction of a metal anode and a semiconductor cathode, that is, a diode using a Schottky junction. Since the conductive component is a large carrier, there is almost no injection of minority carriers. It is suitable for. In addition, since one side is a metal, not only the rise voltage is low and the series resistance is low for the same semiconductor substrate concentration, but also the heat conductivity of the metal is good, and the heat dissipation is also good. Accordingly, the contact resistance is lower than that of the PN junction diode, so the gain characteristics are excellent and the operating frequency is high.

By utilizing these characteristics, in the preferred embodiment of the present invention, the emitter / base junction of the parasitic BJT formed during the MOS transistor formation process is formed in the same manner as the Schottky junction, thereby improving the gain characteristics and operating frequency characteristics of the parasitic BJT. To help.

Subsequently, although not shown in the drawing, a wet etching process is performed to remove metals remaining unreacted in the salicide process.

Subsequently, as shown in FIG. 5, an interlayer insulating layer 21 is deposited on the resultant on which the silicide layer 20 is formed. In this case, the interlayer insulating layer 21 may be a high density plasma (HDP) oxide film, a boron phosphorus silicate glass (BPSG) film, a phosphorus silicate glass (PSG) film, a plasma enhanced tetra thyle ortho silicate (peteos) film, or an un-doped silicate (USG). It may be formed of any one of a glass (FSG) film, a Fluorinated Silicate Glass (FSG) film, a carbon doped oxide (CDO) film, and an organosilicate glass (OSG) film, or may be formed in a stacked structure of two or more thereof.

Subsequently, a mask process and an etching process are performed to perform the first gate electrode 15a, the second gate electrode 15b, the first and second source / drain regions 19a and 19b, the collector junction region 19c of the BJT, A plurality of contact holes (not shown) are formed to expose the base junction region 19d and the emitter junction region 19e, respectively.

Subsequently, after depositing a metal layer on the interlayer insulating film 21 including the contact hole, a mask process and an etching process are performed to form a plurality of contact plugs 22 filling the contact holes, and at the same time, the first to fifth metal wirings. 23a to 23e are formed. At this time, the first metal wiring 23a is electrically connected to the first source / drain region 19a and the first gate electrode 15a of the NMOS transistor via the contact plug 22, respectively, and the second metal wiring 23b is provided. ) Is electrically connected to the second source / drain region 19b and the second gate electrode 15b of the PMOS transistor via the contact plug 22, respectively.

In addition, the third metal wiring 23c is electrically connected to the collector junction region 19c of the BJT via the contact plug 22 to function as a collector electrode, and the fourth metal wiring 23d connects the contact plug 22. Electrically connected to the base junction region 19d of the BJT to function as a base electrode, and the fifth metal wire 23e is electrically connected to the emitter junction region 19e of the BJT via the contact plug 22 to It functions as a emitter electrode.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the emitter / base junction of the parasitic BJT formed during the MOS transistor formation process is formed in the same manner as the Schottky junction, so that the gain characteristics and operating frequency characteristics of the parasitic BJT can be improved. do. Therefore, the MOS transistor and the BJT can be efficiently manufactured on one chip at the same time, thereby manufacturing various types of semiconductor devices.

Claims (7)

Providing a semiconductor substrate defined by a first region and a second region; Forming a first well and a second well in the first region and the second region, respectively; Forming a gate electrode on the first well of the first region; An ion implantation process is performed on the first well and the second well exposed to both sides of the gate electrode to form a source / drain region in the first well, and the collector junction region separated from each other in the second well; Forming a base junction region and an emitter junction region, respectively; And Forming a metal silicide layer on the emitter junction region and the second well such that a portion of the second well exposed between the emitter junction region is in contact with the second well; Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the base junction region is formed of the same conductivity type impurity ions as the second well. The method according to claim 1 or 2, And the emitter junction region and the collector junction region are formed of a conductive impurity ion opposite to the second well. The method according to claim 1 or 2, The metal silicide layer is also formed on the gate electrode, the source / drain region, the collector junction region, and the base junction region. The method according to claim 1 or 2, And the junction region for the emitter is divided into two to be in contact with the metal silicide layer. The method of claim 5, wherein And the second well exposed between the bisegmented emitter junction regions is in contact with the metal silicide layer. The method according to claim 1 or 2, And the base junction region and the metal silicide layer operate as a Schottky diode.

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