KR20060090512A - Resource sharing and pipelining in coarse-grained reconfigurable architecture - Google Patents

Abstract

The present invention relates to resource sharing and pipelining in a reconfigurable arrangement. The present invention is designed to share the functional resources among the processing elements arranged in each row and / or column, instead of implementing the same functional resource for all processing elements in the array structure, thereby reducing the total number of resources needed in the design. In addition, the present invention relates to a reconfigurable arrangement having a resource sharing and pipelining configuration, which enables a more efficient design in terms of area and latency by further pipelining the shared resources.

The resource sharing and pipelining method of the present invention proposes a reconfigurable array structure optimized according to a specific application domain, improves performance, and reduces manufacturing costs by reducing the total number of resources. .

Resource sharing, pipelining, reconfigurable array structure

Description

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture}             

1 illustrates a processing element (PE) and a cache having a 4 × 4 arrangement.

FIG. 2 shows a configuration in which the processing elements shown in FIG. 1 are connected by a data bus.

3 shows a spatial time table of the SIMD model to which the matrix product of Equation 1 is applied.

4 illustrates a spatial time table of a loop pipelined model to which the matrix product of Equation 1 is applied.

FIG. 5 shows a snapshot of the operating procedure in the fifth cycle in the spatial time table of the SIMD model of FIG. 3.

FIG. 6 shows a snapshot of the course of operation in the fifth cycle in the spatial timetable of the loop pipelining model of FIG. 4.

Figure 7 illustrates processing elements with a 4x4 arrangement that shares a multiplier in accordance with the present invention.

FIG. 8 illustrates the connection relationship between the processing element and the shared multiplier in detail in the arrangement of FIG. 7.

9 shows the configuration of a typical processing element that is not pipelined.

10 shows the configuration of a pipelined processing element.

11 shows an arrangement of processing elements to which only resource sharing is applied and a space time table thereof.

12 shows an arrangement of processing elements to which resource sharing and pipelining are applied together and their spatial timetables.

13A-13D illustrate four models of resource sharing (RS) or resource sharing and pipelining (RSP) arrangements.

FIG. 14 is a table showing area and delay time characteristics for the basic arrangement structure, resource sharing structure, resource sharing and pipelining structure in the arrangement of 8x8 processing elements.

15 is a table showing evaluation results of applying kernels in the Livermore loop benchmark to the arrangement of resource sharing and pipelining of the present invention.

FIG. 16 is a table showing evaluation results of applying specific applications including 2D-FDCT, SAD, MVM and FET to the arrangement of resource sharing and pipelining of the present invention.

The present invention relates to resource sharing and pipelining in a reconfigurable arrangement. The present invention is designed to share the functional resources among the processing elements arranged in each row and / or column, instead of implementing the same functional resource for all processing elements in the array structure, thereby reducing the total number of resources needed in the design. In addition, the present invention relates to a reconfigurable arrangement having a resource sharing and pipelining configuration, which enables a more efficient design in terms of area and latency by further pipelining the shared resources.

As the demand for high quality multimedia services increases, techniques for efficient application for audio and / or video data processing, especially in portable systems, are developing. Such applications are generally characterized by performing complex data intensive computations, which can be implemented in two different ways.

One is a software implementation (SI) that runs on a general purpose processor, and the other is a hardware implementation (HI) in the form of an Application-S Processing Element (Cific Integrated Circuit). Software implementations are flexible enough to support a variety of applications, but lack the ability to cope with the complexity of the applications. Hardware implementations, on the other hand, can be optimized for both power and performance, but are limited to specific applications.

A Coarse-Grained Reconfigurable Architecture (hereinafter referred to as "CGRA") compensates for the drawbacks of both implementations. That is, it provides higher performance than a software implementation and has greater flexibility than a hardware implementation.

CGRA is distinguished from a field programmable gate array (hereinafter referred to as "FPGA"). Although both are identical in terms of reconfigurable hardware, compared to FPGAs having logic blocks that can adjust bit data, CGRA provides data such as an Arithmetic Logic Unit (ALU) that can process word data. Have path blocks

Reconfiguration allows CGRA to adapt to the different characteristics of each application, and to improve performance by adopting specific hardware engines. For this reason, many sophisticated CGRAs have been proposed. Most of these consist of a fixed structure of specialized processing elements and fabrics between them. At runtime, each processing element and its interconnect operations can be controlled at runtime, allowing for dynamic reconfiguration.

Various CGRAs are currently proposed, among which two-dimensional mesh structures have abundant communication resources in terms of parallelism.

For example, Morphosys consists of an 8x8 array of Reconfigurable Cells connected to a Tiny_RISC processor. The array structure performs 16-bit operations such as addition, multiplication, etc. under a single instruction multiple data (SIMD) scheme. It shows good performance in terms of regular code segments in areas that require many mathematical operations, but has the disadvantage of high hardware costs.

The XPP reconfiguration system-on-chip architecture is another example with abundant communication resources. The XPP has a 4x4 or 8x8 reconfiguration array and also has a LEON processor configured with an AMBA bus structure. The Processing Element (PE) of the XPP is composed of one arithmetic logic unit (ALU) and several registers. Since the processing element only has primitive resources, the total cost of the hardware is not high, but the applicable application area is limited.

As such, most CGRAs have an array of regular structures for parallel execution of multiple operations and flexible operational scheduling. These constant structures require many hardware resources, ignoring the characteristics of the application area, and the increase in the number of resources inevitably results in an increase in the size of the array structure and an increase in the design cost. The fixed configuration of the processing elements also limits the optimization of the application area consisting of various programs.

Accordingly, in order to overcome this problem, a domain-specific optimization method through defining a template of a reconfigurable structure and design space exploration has been proposed. However, most of the design space exploration techniques proposed so far only consider what functional resources to add within each processing element. For example, the main object of research was to distribute functional resources such as a multiplier, an adder, a shifter, and the like to each processing element in the arrangement of the processing elements.

However, such a configuration in which a resource is fixed within a processing element, although generally high performance can be obtained, the manufacturing cost also increases. This is because for high performance efficiency, even basic design elements must have basic functional resources.

Therefore, there is a demand for the development of a reconfigurable array structure that can reduce the number of total resources and reduce manufacturing costs by efficiently using functional resources on an array of processing elements while performing appropriate functions according to each application area. .

In order to solve the above problem, the present invention provides a reduced size reconfigurable arrangement by sharing functional resources occupying a maximum area within a processing element between processing elements arranged in each row and / or each column. The purpose.                         

Another object of the present invention is to provide a reconfigurable arrangement structure in which size and maximum delay are reduced by pipelining the shared resources.

In order to achieve the above object, the present invention provides a reconfigurable arrangement that is processed in a loop pipeline manner, comprising: processing elements for receiving operands from a memory bus or other processing element; A bus switch for receiving operands one-to-one from the processing element; A shared resource shared by the two or more processing elements, the shared resource being coupled to the bus switch via a data bus to receive and operate the operands from the bus switch; And a configuration cache configured to control to which shared resources the bus switch transmits operands, when the shared resources are more than one. to provide.

In general, coarse-grained reconfigurable arrangements are designed to be suitable for embedded systems. This is because it satisfies both flexibility and high performance. Most reconfigurable array structures use a regular structure for parallel execution of multiple operations and flexible operational scheduling. However, such fixed structures require a lot of hardware resources, ignoring the nature of the application area.

To overcome this limitation, the present invention provides a new reconfigurable array template. It divides functional resources into two groups: primitive resources and shared / pipelined resources. A resource that occupies a maximum area or has a maximum latency within one processing element is selected to be shared by the processing elements. In the present invention, basic resources are located inside all processing elements and shared resources are shared on an array structure outside the processing elements. In this case, you can link the resource to all processing elements that are arranged in the same row or column so that they are shared.

The number of shared resources may vary depending on the application area. The shared resources can be pipelined to reduce the overall maximum critical path. This pipeline processing increases the clock frequency throughout the structure. In this way, the reconfigurable arrangement template of the present invention can be used for an optimized configuration for a particular application area while maintaining regularity.

It will be seen that the resource sharing and pipelining structures of the present invention can significantly reduce area and maximum latency compared to the basic arrangement structure. And, it will be shown that the performance efficiency of several applications is greatly increased in resource sharing and pipelining arrangement.

It is assumed that the resource sharing and pipelining method according to the present invention is not based on a single instruction multiple data (SIMD) implementation but is based on a loop pipelining implementation. Execution such as SIMD, although efficient for data parallel computation and regular execution of data storage in storing configurations, is independent of each processing element. There is no flexibility in that it cannot work.

In contrast, loop pipelining requires more storage to control each pipeline stage, but is more flexible in choosing the operation of processing elements. In addition, the performance can be improved over the SIMD scheme because it reduces the synchronization overhead to perform the same operations simultaneously.

First, the performance efficiency of the SIMD scheme and the loop pipelining scheme is compared. SIMD and loop pipelining can be considered as a method for executing instruction loops on a coarse grain reconfigurable array structure. An example of matrix multiplication illustrates the difference between the two models. We first look at a coarse-grained reconstruction array of processing elements, based on a general-purpose mesh connection structure.

1 illustrates a processing element (PE) and a cache having a 4 × 4 arrangement. Each processing element 2 in FIG. 1 comprises one arithmetic logic unit (ALU), one array multiplier and the like, and is controlled by a configuration cache 4.

FIG. 2 shows a configuration in which the processing elements shown in FIG. 1 are connected to a data bus. As shown, the processing elements 2 of each row share two read buses 5, 6 and one write buses 8.

To compare the operational differences between the loop pipelining SIMD model and the loop pipelining model, we propose the following determinant.

Considering the matrix product of two N-order square matrices X and Y, the output matrix Z can be expressed as follows.

Where i, j = 0,1, ... N and C is a constant value contained in the configuration cache.

3 shows a spatial time table of the SIMD model to which the matrix product of Equation 1 is applied, and FIG. 4 shows a spatial time table of a loop pipelined model to which the matrix product of Equation 1 is applied. The spatial time table of FIGS. 3 and 4 shows the execution on the arrangement of the processing elements shown in FIG. 1 when N = 4 in Equation 1, respectively. In the spatial time table of FIG. 2, the first row represents the cycle order from the beginning of the loop, and the first column represents the column number in the processing element arrangement.

As shown in FIG. 3, the SIMD model performs operations over 12 cycles, and in processing elements of all columns col # 1, col # 2, col # 3, col # 4 in the fifth and eighth cycles. Multiplication operation is performed. For the SIMD model, the load operation runs on all rows until the fourth cycle. Processing elements in the same row are then configured identically in the row direction to perform the same operation.

In contrast, the loop pipelining model performs calculations over nine cycles, as shown in FIG. 4, and the first column col # 1 and the fourth column col5 in the fifth and eighth cycles. Multiplication is performed on the processing elements arranged in # 4).

In the loop pipelining model, all the processing elements in the first column load the operands in the first cycle. The second cycle then performs a multiplication operation. In the following third and fourth cycles, the processing elements of the first column perform addition while the processing elements of the next column perform multiplication to obtain the sum of the multiplied values. Then in the fifth cycle, multiplication is performed on the processing elements of the first column, during which the first multiplication is performed on the fourth column.

As such, in the SIMD model, the process of transferring data and the process of performing arithmetic operations are separated in time, and thus, processing elements are not effectively utilized. However, in the pipelined instruction loop model, processing elements can be efficiently utilized in that the data to be computed next is loaded continuously while the operation operation by the resource is performed.

The loop pipelining in the above example reduced three cycles compared to SIMD. However, if there are many memory operations in the loop, the pipelining performance will be further improved.

This will be described in more detail as follows. FIG. 5 shows a snapshot of the operating process at the fifth cycle in the spatial time table of the SIMD model of FIG. 3, and FIG. 6 is at the fifth cycle in the spatial time table of the loop pipelining model of FIG. A snapshot of the process is shown. 5 and 6, it is possible to compare multiplier utilization in the SIMD model and the loop pipelining model.

As discussed earlier, in the loop pipelining model, the same computational operations are distributed to each processing element for several cycles, so there is no need for all processing elements to have the same functional resources at the same time.

In the spatial timetables of FIGS. 5 and 6, the multiplication operation is performed on all columns in the SIMD model for the fifth cycle, but only the processing elements of the second and fourth columns perform the multiplication in the loop pipeline model.

Thus, in the case of the SIMD model, the processing elements of all the columns are required to have a multiplier, thereby increasing the area and the implementation cost of the entire array structure. On the other hand, in the loop pipeline model, it is possible for processing elements in the same column or the same row to share area-critical resources.

In the example of 4 × 4 matrix multiplication, such as Equation 1, multipliers occupy a maximum area within one processing element, so they can be classified as shared resources and other resources as primitive resources. Can be.

Figure 7 illustrates processing elements with a 4x4 arrangement that shares a multiplier in accordance with the present invention. As shown, four processing elements 12 and two shared multipliers 14 are arranged in each row. In the conventional SIMD model, since all processing elements each have a multiplier, the multiplier has 16 multipliers in the case of a 4 × 4 processing element array. In contrast, in the embodiment according to the invention of FIG. 7, a total of eight multipliers 14 are shared by sixteen processing elements 12.

In addition, the shared multipliers 14 are located outside of the processing element, taking the configuration indirectly connected to the processing element 12 and the bus switch 16. The shared multipliers 14 perform arithmetic functions in accordance with the operation of the bus switch 16.

In the embodiment of FIG. 7, each processing element 12 is connected one-to-one with a bus switch 16 via a data bus, which is connected with a shared multiplier 14 via another data bus. do. Control of the bus switch is achieved through a configuration cache in the processing element.

In order to easily allocate resources on an array structure, it is necessary to form a regular structure of shared resources. In one embodiment, the shared resources may be located in the same line with the rows and / or columns of the reconstruction structure.

The connection buses shown in FIG. 7 represent only buses related to resource sharing. In this example, a 4 × 4 two-dimensional array structure is described, but the resource sharing connection structure can be applied to other square structures and one-dimensional array structures.

FIG. 8 illustrates in detail the connection relationship between the processing element and the shared multiplier in the arrangement of FIG. 7. As shown, between the processing element 12 and the bus switch 16, two n-bit databuses 21 and 22 to which an operand is transmitted and one 2n-bit databus to which an operation result value is transmitted. 23 is comprised. In the same manner as above, two n-bit data buses 24 and 25 and one 2n-bit data bus 26 are formed between the bus switch 16 and each shared multiplier 14.

On the other hand, the component cache 18 allocated to each processing element 12 controls the bus switch by being directly connected to the bus switch 16 through the control line 17. Dynamic mapping of shared multiplier 14 and processing element 12 is determined at compile time, and the information is included in configuration instructions stored in configuration cache 18.

Referring to FIG. 8, a process of performing an operation using a shared resource is as follows. First, the processing element 12 which receives an operand from a read bus (not shown) is configured to share a shared resource 14 with a configuration instruction received from the configuration cache 18. If the operation used is included, the operand is first sent to the bus switch 16 for that operation.

On the other hand, the configuration cache 18 transmits a control signal for selecting any one of the plurality of shared resources 14 to the bus switch 16, the bus switch 16 received from the processing element 12 The operand is transmitted to the corresponding shared multiplier according to the control signal. The shared multiplier 14 performs a multiplication operation on the received operand and then sends it to the bus switch 16 via a 2n bit bus 26, the bus switch 16 sending the result value to the original processing element. To send.

As can be seen from the embodiment of the present invention shown in FIG. 7, instead of implementing a multiplier for each processing element, by sharing two multipliers for each processing element in each row, The same operation can be performed in a shorter time using only half the number (eight) resources compared to the number (16).

On the other hand, in addition to sharing a multiplier as described above, the multiplier can be used more efficiently by pipeline processing each multiplier. If some resources have both maximum area and maximum latency in the processing element ('multiplier' in the embodiment of the present invention), resource sharing and resource pipelining can be applied simultaneously. If these two techniques are combined, the conditions for resource sharing are relaxed, so that the resources can be utilized more efficiently.

Here's a quick look at the pipelined processing of resources: 9 shows the configuration of a general pipelined processing element and FIG. 10 shows the configuration of a pipelined processing element.

In FIG. 9, data (an operand) is input from an output register 42 of a neighboring processing element 50, and the input operand is operated by a threshold resource 54 or other functional resource 56 having a maximum delay time. And then temporarily stored in the output register 52. Since moving data from one output register 42 to another register 52 corresponds to one cycle, if the maximum delay time of the critical resource 54 is long, the cycle of the processing element 60 becomes long. As a result, the processing speed of the entire array becomes slow.

To compensate for this problem, pipeline processing is performed by inserting registers into the critical resource having the maximum latency. As shown in FIG. 10, the one-cycle operation method was changed to the two-cycle operation method by inserting a register 72 into the critical resource 74 to pipeline. In a typical reconfigurable array structure, the program execution time is fixed by its critical path, but in an array structure of pipelined processing elements of the present invention, multi-cycle operations are allowed, and thus the execution thereof. The time can vary depending on the operation of the operation. This is because the system clock frequency is increased.

FIG. 11 shows an arrangement of the processing elements 14 to which only resource sharing is applied and its spatial time table. FIG. 12 shows an arrangement of the processing elements 114 to which resource sharing and pipelining are applied together and its space time table. . As can be seen from the comparison between FIG. 11 and FIG. 12, the configuration in which resource sharing and pipelining are applied together performs the same operation as the configuration in which resource sharing only is applied, without any interruption to the calculation process, while the number of multipliers is increased. It can be reduced from eight to four.

This is because two processing elements sharing one pipelined multiplier can perform two multiplications at the same time using different pipeline stages.

The efficiency improvement of the reconfigurable array structure due to the application of resource sharing and pipeline techniques will be described. For convenience of description, the array structure of 8 x 8 processing elements is divided into three cases, a basic array structure, a resource sharing (RS) structure, a resource sharing and a pipelining (RSP) structure, and compared with each other.

First, as a form of resource sharing (RS), as shown in FIG. 13, processing elements and resources may be arranged. 13A to 13D are diagrams illustrating four models of a resource sharing (RS) or resource sharing and pipelining (RSP) arrangement, specifically as follows.

FIG. 13A shows an arrangement of processing elements in which each multiplier is shared or shared and pipelined by eight processing elements. FIG. 13B shows an arrangement of processing elements in which each multiplier is shared or shared and pipelined by eight processing elements. 13C shows an arrangement of processing elements in which two multipliers are shared or shared and pipelined by eight processing elements in each row, and one multiplier is shared or shared and pipelined by eight processing elements in each column. Indicates. FIG. 13D illustrates an arrangement of processing elements in which two multipliers are shared or shared and pipelined by eight processing elements in each row, and two multipliers are shared or shared and pipelined by eight processing elements in each column. Indicates.

In the arrangement of 8 × 8 processing elements, the characteristics of the basic array structure (structure that is neither shared nor piped), resource sharing (RS) structure, resource sharing and pipelining (RSP) structure are characterized by area and delay. It is shown in the table of FIG. 14 in terms of time.

As shown in the table of FIG. 14, the structure having shared resources (RS #) or the structure having both shared and pipelined resources (RSP #) has an area as compared to the base array structure (Base) having nothing at all. And it can be seen that the delay time is greatly reduced.

Especially for configurations where one multiplier is shared by eight processing elements in each row (RS # 1), the area is reduced by 42.8% in area compared to the basic array structure, and one multiplier is applied to eight processing elements in each row. If shared by both pipelines (RSP # 1), the latency is reduced to 34.69%.

As can be seen from the table of FIG. 14, the arrangement configuration to which the resource sharing and pipelining method according to the present invention is applied is more efficient than the original basic arrangement structure in terms of area and delay time. It can also be seen that, rather than relying solely on resource sharing, pipelined shared resources can provide an array structure with less area and lower latency.

On the other hand, when designing for sharing resources, the number of operations to be executed by the shared resources should be counted, which should be compared with the number of shared resources required in every cycle. If in one cycle, the number of operations using shared resources is greater than the number of shared resources, it means that the number of shared resources is insufficient in that cycle. In this case, several stall cycles can be inserted as a way to avoid resource conflicts. This is referred to as the RS stall.

In addition, in the case of resource pipelining (RP), the operations to be executed on those pipelined resources have multiple cycles. Therefore, operations that depend on pipelined resources must be stopped together. This is referred to as the RP stall. Therefore, the RS stop and RP stop cycles can be used to approximate the total number of stop cycles.

Configuration information codes of initial resource sharing and pipelining (RSP) are relocated according to resource sharing (RS) and resource pipelining (RP). There are two rules about the relocation. First, in designing for resource sharing, shared resources are assigned to processing elements in the order of loop iteration. Therefore, if shared resources are lacking, operations in later loop iterations are moved to the next cycle.

Second, when designing for a resource pipeline, because operations between pipelined resources have multiple cycles, other operations that depend on the output of the pipelined resources must be stopped together. Furthermore, for successive pipelined operations, overlapped cycles between those operations should be eliminated. In the case of RSP, the above two laws apply to the initial configuration information codes.

Meanwhile, in the resource sharing and pipeline design according to the present invention, the type of shared resources, the type of pipelined resources, the number of pipeline stages of pipelined resources, the number of rows of shared resources, Consider the number of columns of the shared resources.

The resource sharing and pipelining method for optimizing a particular application area according to the present invention is applicable to any square array structure (n × n) of processing elements. Thus, it can be applied to a universal array structure template that includes many existing Coles-Grain reconstruction arrays.

The effect of resource sharing and pipelining according to the present invention is applied to various kernels of, for example, Livermore loops benchmark, or to various applications including 2D-FDCT, SAD, MVM and FET. This can be confirmed by.

Hereinafter, the result of resource sharing and pipelining application according to the present invention will be described in detail. Various kernels and specific applications of the Livermore loops benchmark apply to resource sharing (RS) and resource sharing pipelining (RSP) structures.

The table in FIG. 15 evaluates the results of applying the kernels in the Livermore loop benchmark to the arrangement of resource sharing and pipelining of the present invention. In the table of FIG. 15, ET (ns), DR (%), and stall have the following meanings, respectively.

ET (ns) = Execution Time = Cycle × Maximum Delay Time

DR (%) = reduction of delay time compared to basic array structure

stall = number of stall operations due to lack of resources

As can be seen from the table of FIG. 15, as a result of applying the resource sharing and pipelining configuration of the present invention to three kernels (Hydro, ICCG, Tri-diagonal), compared to the basic array structure without resource sharing and pipelining The delay time was reduced to 15.92% in RSP # 2, 32.12% in RSP # 1 and 31.91% in RSP # 1, respectively.

FIG. 16 is a table showing evaluation results of applying specific applications including 2D-FDCT, SAD, MVM and FET to the arrangement of resource sharing and pipelining of the present invention. In FIG. 16, "MVM" means Matrix Vector Multiplication. In the table of FIG. 16, as a result of applying the resource sharing and pipelining configuration of the present invention to four kernels (2D-FDCT, SAD, MVM, and FET), the delay time is RSP # 2, respectively, compared to the basic array structure. In 17.01%, 35.7% in RSP # 1, 32.31% in RSP # 1 and 22.07% in RSP # 2.

In the table of FIG. 16, RSP structure 2 (RSP # 2) supports all selected kernels of Livermore loops without operational stall and is indicated as having the best performance. 15 and 16, it can be seen that the optimal arrangement without deterioration is RSP # 1 or RSP # 2.

As such, the performance improvement rate obtained by applying the resource sharing and pipelining method according to the present invention may vary depending on the executed application program. For example, when 2D-FDCT requiring multiplication and SAD function without multiplication are applied to an array structure having the same resource sharing and pipelining structure, as shown in the table of FIG. In this case, the improved performance can be achieved by applying the SAD function. This is because the clock frequency is increased by pipelining the multiplier. In general, it is not possible to get more speedup of kernels with a large number of multiplications because multiplications lead to multiple cycles within RSP structures.

When the reconfigurable arrangement having the resource sharing and pipe lining configuration according to the present invention described above is implemented on the hardware, the total number of resources can be reduced, thereby reducing the size and manufacturing cost of the hardware.

While specific embodiments of the present invention have been described above, the present invention may be variously modified by those skilled in the art without departing from the spirit of the present invention. Such modified embodiments should be construed as being included in the scope of the claims of the present invention without departing from the spirit of the present invention.

As described above, the reconfigurable array structure having the resource sharing and pipelining configuration according to the present invention is required for constructing the array structure by sharing resources for performing arithmetic operations among processing elements arranged in the same row and / or column. The total number of resources can be reduced, and further, by pipelining the resources shared among the processing elements, a more efficient arrangement structure in terms of area and latency can be realized.

In addition, through the reconfigurable array structure having resource sharing and pipe lining configuration according to the present invention, an array structure optimized for a specific application area can be obtained, and the realization cost of hardware can be reduced without degrading performance.

Claims (10)

A reconfigurable array of loop pipelined processing elements Two or more processing elements for receiving operands from a memory bus or other processing element; A bus switch connected one-to-one with the processing element to receive an operand from the processing element; A shared resource shared by the two or more processing elements, the shared resource being coupled to the bus switch via a data bus to receive and operate the operands from the bus switch; And And a configuration cache configured to control to which shared resources the bus switch transmits operands when there are two or more shared resources. The method of claim 1, The shared resource is a reconfigurable arrangement having a resource sharing and pipelining configuration, characterized in that the register is inserted into the resource pipeline processing. The method of claim 1, And wherein said shared resource is a multiplier. The method of claim 1, And the configuration cache controls which shared resource the operable bus switch transmits operands to via a control line directly connected to the bus switch. The method of claim 1, Wherein said configuration cache and said processing element are one-to-one connected. The method of claim 1, A reconfigurable array structure with resource sharing and pipelining further comprising data memory having multiple read / write data buses. The method of claim 1, A reconfigurable arrangement having a resource sharing and pipelining configuration, wherein the same resources are shared per processing element arranged in the same row or in the same column. The method of claim 1, And a data bus connecting said processing element and said bus switch comprises two n-bit buses and one 2n-bit bus. The method of claim 1, And a data bus connecting the bus switch and the shared resource includes two n-bit buses and one 2n-bit bus. 10. A hardware device comprising any one of the arrangements of claims 1-9.

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