KR20060088968A - Self refresh plus generation apparatus and semiconductor memory device including the same - Google Patents

Abstract

Disclosed are a self refresh pulse generator and a semiconductor memory device having the same. The self refresh pulse generation device includes a standard self refresh pulse generator for generating a standard self refresh pulse for performing self refresh of N banks included in a semiconductor memory device; And receiving the generated standard self refresh pulses, converting the periods of the input standard self refresh pulses according to the self refresh periods of each bank to generate N bank self refresh pulses, and then generating the respective bank self And a bank-specific self refresh signal generator for transmitting a refresh pulse to a corresponding bank side. Therefore, a bank self refresh pulse corresponding to each bank according to the self refresh cycle characteristics of each bank can be generated, and self refresh according to the cycle can be performed.

Description

Self-refreshing pulse generating device and semiconductor memory device having the same {SELF REFRESH PLUS GENERATION APPARATUS AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME}             

Fig. 1 is a block diagram showing the structure of a conventional semiconductor memory device, and schematically shows a portion related to self refresh.

FIG. 2 is a block diagram illustrating a static refresh period of each bank shown in FIG. 1.

3 is a block diagram showing a configuration of a semiconductor memory device according to a preferred embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a bank-specific self refresh pulse generator shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

100: standard self refresh pulse generator

110: basic pulse generator

120: self refresh counter

130: standard self refresh pulse generator

200: self-refresh pulse generator for each bank

310, 320, 330, 340: row address counter

410, 420, 430, 440: row decoder

510, 520, 530, 540: first bank, second bank, third bank, fourth bank

The present invention relates to a self refresh pulse generation device capable of generating respective self refresh pulses according to a self refresh cycle characteristic of a bank, and a semiconductor memory device having the same.

In general, a semiconductor memory device such as a dynamic random access memory (DRAM) or the like is composed of a collection of unit cells composed of a transistor and a capacitor, and stores data in the capacitor.

However, since the capacitor formed on the semiconductor substrate cannot be completely electrically separated from the surroundings, leakage current occurs and data stored in the capacitor, that is, the charge is discharged over time, and thus the data stored in the cell disappears. do.

Therefore, in order to prevent such a phenomenon, the semiconductor memory device continuously performs an operation of rewriting information stored in a cell at a predetermined cycle, which is called self refresh.

The self refresh is performed by selecting a word line at least once within a retention time of each cell existing in a memory cell array of a memory, sensing the data, and then amplifying the data. At this time, the retention time means a time after which data is recorded in the cell and the data can be maintained in the cell without refreshing.

That is, when the self-refresh operation command is input, the row address is sequentially increased at regular intervals, and the row address is sequentially increased to select the word line of the memory cell. At this time, the charge stored in the capacitor corresponding to the word line is amplified by the sense amplifying means and stored in the capacitor again. Through this series of self refresh processes, the stored data is preserved intact.

Fig. 1 is a block diagram showing the structure of a conventional semiconductor memory device, and schematically shows a portion related to self refresh.

Referring to FIG. 1, a conventional semiconductor memory device includes a basic pulse generator 10 generating a basic pulse generator, a self refresh counter 20 performing a count according to a self refresh cycle, a basic pulse generator 10, The self refresh pulse generator 30 outputs a self refresh pulse having a predetermined period using the self refresh counter 20, and the self refresh pulses output from the self refresh pulse generator 30 are counted to count each bank 61. And a row address counter 40 for outputting a signal for row address selection of the channels 62, 63, and 64, and a signal transmitted from the row address counter 40 to decode the corresponding banks 61, 62, 63, and 64. Four row decoders 51, 52, 63, 54 for selecting a row, and four memory banks 61, 62, 63, for performing self refresh according to the selection of the row decoders 51, 52, 63, 54, Consists of 64) do.

In this case, since the self refresh periods of the memory banks 61, 62, 63, and 64 are different from each other, the periods of the self refresh pulses are set in four banks 61, 62, 63, to prepare for the worst case considering the process. In the 64), the self refresh characteristic is generated in accordance with the self refresh period of the bank having the shortest period.

FIG. 2 is a block diagram illustrating a static refresh period of each bank 61, 62, 63, and 64 shown in FIG. 1.

2, bank A 61, bank B 62, bank C 63 and bank D 64 each have a static refresh period of 128 ms, 192 ms, 256 ms and 320 ms. Therefore, in the above-described conventional case, the self-refresh pulse period must be 128 ms to satisfy all four banks 61, 62, 63, and 64.

In this case, however, the bank A 61 performs the self refresh in accordance with the required self refresh period, but the bank B 62 performs the self refresh more than 50% more than the required period. In the same concept, the bank C 63 and the bank D 64 may be self refreshing 100% and 150% more than the required period.

Therefore, the banks B 62, C 63 and D 64 consume more current than necessary due to excessive self refresh, which results in lowering the economic efficiency of the semiconductor memory device. do.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a first object of the present invention is to provide a self refresh pulse generation apparatus capable of generating self refresh pulses according to the self refresh cycle characteristics of each bank.

Another object of the present invention is to provide a semiconductor memory device capable of preventing current consumption due to excessive self refresh by providing the self refresh pulse generation device.

The self-refresh pulse generating device according to the present invention for achieving the first object of the present invention, generating a standard self refresh pulse for performing a self-refresh of the N banks provided in the semiconductor memory device part; And receiving the generated standard self refresh pulses, converting the periods of the input standard self refresh pulses according to the self refresh periods of each bank to generate N bank self refresh pulses, and then generating the respective bank self And a bank-specific self refresh signal generator for transmitting a refresh pulse to a corresponding bank side.

In this case, the standard self-refresh pulse generator may include a basic pulse generator configured to generate a basic pulse; A self refresh counter for counting the generated basic pulse according to a period of the standard self refresh pulse; And a standard self refresh pulse generator configured to control the reference pulse generator and the self refresh counter to generate the standard self refresh pulse.

The bank-specific self refresh pulse generation unit converts the input standard self refresh pulses to the self refresh period of any one of the N banks to generate the bank self refresh pulses. N bank self-refresh pulse generators are transmitted.

The bank self refresh pulse generation unit may include a period selector configured to apply the input standard self refresh pulse and select a period of the bank self refresh pulse according to a refresh period of a corresponding bank; And a converter for converting the applied standard self refresh pulse to the selected period to output the bank self refresh pulse. The bank self refresh pulse generator may further include a multiplexer configured to multiplex and output a bank self refresh pulse output from the converter.

The conversion unit increases or decreases the period of the standard self refresh pulse by an integer multiple. That is, the bank self refresh pulse is generated by converting the period of the standard self refresh pulse to 1, 2, 4, 1/2, and 1/4 times so as to match the period of the corresponding bank. In this case, the conversion unit includes a plurality of period counters for converting the period of the standard self refresh pulse to a multiple.

On the other hand, a semiconductor memory device for achieving the second object of the present invention, N banks having a plurality of memory cells, each having a unique self refresh period; A standard self refresh pulse generator for generating a standard self refresh pulse for performing self refresh; And receiving the generated standard self refresh pulses, converting the periods of the input standard self refresh pulses according to the self refresh periods of each bank to generate N bank self refresh pulses, and outputting the banks to the corresponding bank side. Each self refresh signal generator is composed.

The semiconductor device includes N row address counters corresponding to the respective banks and counting the bank self refresh pulses output by the bank self refresh signal generators to output row address signals to the corresponding banks; And N row decoders respectively disposed corresponding to the respective banks and specifying rows of corresponding banks according to row address signals output from the row address counts.

In this case, the standard self-refresh pulse generator may include a basic pulse generator configured to generate a basic pulse; A self refresh counter for counting the generated basic pulse according to a period of the standard self refresh pulse; And a standard self refresh pulse generator configured to control the reference pulse generator and the self refresh counter to generate the standard self refresh pulse.

The bank-specific self-refresh pulse generator converts the input standard self-refresh pulse to be equal to the self-refresh period of any one of the N banks to generate the bank self-refresh pulse. N bank self-refresh pulse generators are sent to the bank.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

3 is a block diagram showing a configuration of a semiconductor memory device according to a preferred embodiment of the present invention.

Referring to FIG. 3, a semiconductor memory device according to an exemplary embodiment of the present invention may include four banks, that is, a first bank 510, a second bank 520, a third bank 530, and a fourth bank 540. Each bank 510, 520, 530, 540 has a row decoder 410, 420, 430, 440 and a row address counter 310, 320, 330, 340, respectively. Although not shown, the banks 510, 520, 530, and 540 are provided with a plurality of memory cells arranged in rows and columns, and the row decoders 410, 420, 430, and 440 are connected to a row address counter. Signals from (310, 320, 330, 340) are received to specify the rows of the banks (510, 520, 530, 540).

In addition, in the present embodiment, the self refresh periods of the first bank 510 and the third bank 530 are the same, and the second bank 520 has a self refresh period twice as long as that of the first bank 510. It is assumed that the fourth bank 540 has a self refresh period four times longer than the first bank 510. However, the number of banks provided and the self refresh period may vary depending on the implementation environment.

As illustrated in FIG. 3, the semiconductor memory device may perform a standard self refresh pulse generator 100 and a self refresh pulse for each bank so as to perform self refresh of the four banks 510, 520, 530, and 540. The generator 200 is provided.

The standard self refresh pulse generator 100 generates a standard self refresh pulse, which is a standard signal for performing self refresh of the banks 510, 520, 530, and 540, and outputs the standard self refresh pulse to the self refresh pulse generator 200 for each bank. It performs the function.

The standard self refresh pulse generator 100 includes a basic pulse generator 110 for generating a basic pulse, a self refresh counter 120 and a reference pulse generator for counting the basic pulses according to a cycle of the standard self refresh pulse. And a standard self refresh pulse generator 130 for controlling the self refresh counter 120 to generate a standard self refresh pulse.

The self refresh pulse generator 200 for each bank receives the standard self refresh pulses generated by the standard self refresh pulse generator 100, and performs a standard self refresh according to the refresh cycles of the respective banks 510, 520, 530, and 540. After generating the bank self refresh pulses corresponding to the respective banks 510, 520, 530, and 540 by converting the periods of the refresh pulses, the bank row address counters 310 and 320 of the corresponding banks 510, 520, 530, and 540. , 330, 340.

That is, the first bank 510 corresponding to the self refresh periods of the first bank 510, the second bank 520, the third bank 530, and the fourth bank 540 is received by receiving the standard self refresh pulse. The bank self refresh pulses of the second bank 520, the bank self refresh pulses of the second bank 520, the bank self refresh pulses of the third bank 530, and the bank self refresh pulses of the fourth bank 540, respectively. Transmission to the row address counters 310, 320, 330, and 340 corresponding to 520, 530, and 540, respectively.

FIG. 4 is a block diagram illustrating a configuration of the self refresh pulse generator 200 for each bank illustrated in FIG. 3.

3 and 4, each bank self refresh pulse generator 200 generates four bank self refresh pulses to generate bank self refresh pulses corresponding to each bank 510, 520, 530, and 540. That is, the first bank self refresh pulse generator 210, the second bank self refresh pulse generator 220, the third bank self refresh pulse generator 230, and the fourth bank self refresh pulse generator 240 are described. It consists of.

At this time, each of the bank self refresh pulse generators 210, 220, 230, and 240 applies an input standard self refresh pulse, and according to the self refresh periods of the banks 510, 520, 530, and 540, the bank self refresh pulses. The periods of the standard self refresh pulses are selected according to the periods selected by the period selectors 211, 221, 231, and 241 and the periods selected by the period selectors 211, 221, 231, and 241. Converters 213, 223, 233, and 243 for outputting the bank self refresh pulses by converting them in the same manner as the refresh cycles of the memory cells 530, 540, and the banks 510, 520, 530, The multiplexers 215, 225, 235, and 245 output to the row address counters 310, 320, 330, and 340 of the 540.

The converting units 213, 223, 233, and 243 may include a first converting unit (a) for outputting a standard self refresh signal as it is, and a second converting unit (b) for converting and outputting a double cycle of the standard self refresh signal. And a third converter c for converting the period of the standard self refresh signal four times and outputting the same.

In this case, in order to perform the above process, the second converter b and the third converter c are provided with a period counter k for converting the period of the input pulse twice. The first converting unit a outputs the standard self refresh signal as it is, and the second converting unit b outputs the standard self refresh signal by doubling the period through the period counter k. Is a pulse signal having four times the period by receiving the standard self refresh signal and the pulse signal converted twice by the period counter k of the second converter b, and converting the period of the converted pulse signal twice. Outputs

Therefore, the output of the bank self refresh pulses having cycles of 1, 2 and 4 times the standard self refresh pulse period is possible. At this time, the output is one of the three outputs by the control of the period selection unit 211, 221, 231, 241 described above.

Referring to the operation of each of the bank self refresh pulse generators 210, 220, 230, and 240, the period selector 211 of the first bank self refresh pulse generator 210 is self-self from the first bank 510. Since the refresh cycle is the same as that of the standard self refresh pulse, the standard self refresh pulse is output as it is through the first converter a of the converter 213, and the output bank self refresh pulse is multiplexed by the multiplexer 215. Transmit to the row address counter 310 of the first bank 510.

The period selector 221 of the second bank refresh pulse generator 220 may include the second converter of the converter 223 because the self refresh period of the second bank 520 is twice the standard self refresh pulse period. Through b), the period of the standard self refresh signal is doubled to output the converted bank self refresh pulse. The output bank self refresh pulse of the second bank 520 is multiplexed by the multiplexer 225 of the second bank self refresh pulse generator 220 and transmitted to the row address counter 320 of the second bank 520. .

The period selector 231 of the third bank refresh pulse generator 230 may include the first converter of the converter 233 because the self refresh period of the third bank 530 is the same as that of the standard self refresh pulse. Through a), the standard self refresh pulse is output as it is, the output bank self refresh pulse is multiplexed by the multiplexer 235, and transmitted to the row address counter 330 of the third bank 530.

The period selector 241 of the fourth bank refresh pulse generator 240 may include the third converter of the converter 243 because the self refresh period of the fourth bank 540 is four times the standard self refresh pulse period. Through c), the period of the standard self refresh signal is converted four times to output the converted bank self refresh pulses. The output bank self refresh pulses of the fourth bank 540 are multiplexed by the multiplexer 245 of the fourth bank self refresh pulse generator 240 and transmitted to the row address counter 340 of the fourth bank 540. .

Meanwhile, the row address counters 310, 320, 330, and 340 output from the respective bank self refresh pulse generators 210, 220, 230, and 240 are transmitted to the corresponding row address counters 310, 320, 330, and 340. ) Outputs a selection signal for selecting a row of the corresponding banks 510, 520, 530, and 540 in synchronization with the transmitted bank self refresh pulses to the low decoders 410, 420, 430, and 440 of the corresponding bank. .

Accordingly, each row decoder 410, 420, 430, 440 selects a row of the banks 510, 520, 530, 540 corresponding to a period corresponding to the corresponding bank self refresh pulse, and selects each bank 510, 520, 530. , 540 is to perform a self refresh operation.

That is, the first bank 510 performs self refresh by the first bank self refresh pulse having the same period as the standard self refresh pulse, and the second bank 520 performs twice the period of the standard self refresh pulse period. The self refresh is performed by the second bank self refresh pulse, and the third bank 530 performs the self refresh by the third bank self refresh pulse having the same period as the standard self refresh pulse, and the fourth bank 540. Performs a self refresh by the fourth bank self refresh pulse having a period four times the standard self refresh pulse period.

Therefore, conventionally, all banks must perform self refresh in accordance with the self refresh period of the bank having the fastest self refresh period regardless of the self refresh cycle characteristics of each bank. However, in the above-described embodiment, each bank has a different self refresh period. Since the banks perform self refresh according to the bank self refresh pulses generated corresponding to their self refresh periods, it is possible to prevent unnecessary current consumption.

Although the present invention has been described above with reference to its preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And it will be understood that changes can be made.

In particular, the foregoing embodiment has described a semiconductor memory device and a self-refreshing device having four banks, but the number of banks may vary depending on the implementation environment, and the self-refresh cycles of each bank are not only 1, 2, and 4 times. It may be applied as 1/2, 1/4, 8, or 16 times.

That is, a predetermined standard self refresh pulse may be generated, and the period may be changed according to the characteristics of each bank to generate and provide a bank self refresh pulse suitable for the period of each bank.

Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, according to the self-refresh pulse generating device and the semiconductor memory device having the same according to the present invention, the bank self-refresh pulse corresponding to each bank according to the self-refresh cycle characteristics of each bank is generated, Since the self refresh can be performed, it is possible to prevent unnecessary current consumption during the self refresh that has occurred in the past.

Claims (19)

A standard self refresh pulse generator configured to generate a standard self refresh pulse for performing self refresh of N banks provided in the semiconductor memory device; And After receiving the generated standard self refresh pulse, the period of the input standard self refresh pulse is converted according to the self refresh period of each bank to generate N bank self refresh pulses, and then each of the generated bank self refresh pulses. And a self refresh signal generator for each bank for transmitting a pulse to a corresponding bank side. The method of claim 1, wherein the standard self refresh pulse generator, A basic pulse generator for generating a basic pulse; A self refresh counter for counting the generated basic pulse according to a period of the standard self refresh pulse; And And a standard self refresh pulse generator for controlling the reference pulse generator and the self refresh counter to generate the standard self refresh pulses. The method of claim 1, wherein the self-refresh pulse generator for each bank, N bank self refresh pulse generators which convert the input standard self refresh pulses into the same self refresh periods of any one of the N banks, generate the bank self refresh pulses, and then transfer the bank self refresh pulses to the corresponding banks. Self-refreshing pulse generator, characterized in that provided. The method of claim 3, wherein the bank self refresh pulse generator, A period selecting unit applying the input standard self refresh pulse and selecting a period of the bank self refresh pulse according to a refresh period of a corresponding bank; And And a converting unit converting the applied standard self refresh pulses into the selected period to output the bank self refresh pulses. The apparatus of claim 4, wherein the bank self refresh pulse generator further comprises a multiplexer configured to multiplex and output a bank self refresh pulse output from the converter. 5. The self-refresh pulse generator of claim 4, wherein the converter increases or decreases the period of the standard self-refresh pulse by an integer multiple. The method of claim 6, wherein the conversion unit converts the period of the standard self refresh pulse to any one of 1, 2, 4, 1/2 and 1/4 times to generate the bank self refresh pulse. Self-refresh pulse generator. The apparatus of claim 4, wherein the conversion unit comprises a plurality of period counters for converting the periods of the standard self refresh pulses into multiples. 2. The self-refresh pulse generator as claimed in claim 1, wherein N is four. N banks having a plurality of memory cells, each bank having a unique self refresh period; A standard self refresh pulse generator for generating a standard self refresh pulse for performing self refresh; And The bank receives the generated standard self refresh pulses, converts the periods of the input standard self refresh pulses according to the self refresh periods of the respective banks, generates N bank self refresh pulses, and outputs the banks to corresponding banks. And a self refresh signal generator. The N row address counter of claim 10, further comprising N row address counters corresponding to the respective banks and counting the bank self refresh pulses output by the bank self refresh signal generators to output row address signals to the corresponding banks. ; And And N row decoders respectively disposed corresponding to each of the banks and specifying rows of corresponding banks according to row address signals output from the row address counts. The method of claim 10, wherein the standard self refresh pulse generator, A basic pulse generator for generating a basic pulse; A self refresh counter for counting the generated basic pulse according to a period of the standard self refresh pulse; And And a standard self refresh pulse generator configured to control the reference pulse generator and the self refresh counter to generate the standard self refresh pulses. The method of claim 10, wherein the self-refresh pulse generator for each bank, N bank self refresh pulse generators which convert the input standard self refresh pulses into the same self refresh periods of any one of the N banks, generate the bank self refresh pulses, and then transfer the bank self refresh pulses to the corresponding banks. A semiconductor memory device, characterized in that provided. The method of claim 13, wherein the bank self refresh pulse generator, A period selecting unit applying the input standard self refresh pulse and selecting a period of the bank self refresh pulse according to a refresh period of a corresponding bank; And And a converter configured to convert the applied standard self refresh pulse to the selected period to output the bank self refresh pulse. The semiconductor memory device of claim 14, wherein the bank self refresh pulse generator further comprises a multiplexer configured to multiplex and output a bank self refresh pulse output from the converter. 15. The semiconductor memory device according to claim 14, wherein the converter increases or decreases the period of the standard self refresh pulse by an integer multiple. 15. The method of claim 14, wherein the conversion unit converts the period of the standard self refresh pulse to any one of 1, 2, 4, 1/2 and 1/4 times to generate the bank self refresh pulse. A semiconductor memory device. 15. The semiconductor memory device according to claim 14, wherein the conversion unit includes a plurality of period counters for converting the period of the standard self refresh pulse to a multiple. 11. The semiconductor memory device of claim 10, wherein N is four.

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