KR20060082671A - Multilayer chip capacitor - Google Patents

Abstract

The present invention relates to a multilayer chip capacitor having excellent mechanical reliability, comprising: a capacitor body having a plurality of dielectric layers stacked thereon and having at least one pair of first and second internal electrodes disposed to face each other with a dielectric layer interposed therebetween; In a stacked chip capacitor comprising a first and a second external electrode formed on opposite end surfaces of the capacitor body to be connected to the first and second internal electrodes, respectively, wherein the thickness of the external electrode is t (㎛), When the height of the capacitor body is H (mm) and the breakdown strength of the dielectric layer is Y (Mpa), the correlation between the thickness of the external electrode and the height of the capacitor body with respect to the breakdown strength of the dielectric layer is Y ≧ 154.91. A stacked chip capacitor is provided that satisfies + 1.487t-89H.

Multilayer Chip Capacitors, External Electrodes, Cracks

Description

Multilayer Chip Capacitors {MULTILAYER CHIP CAPACITOR}

Fig. 1A is a sectional view showing a conventional stacked chip capacitor structure.

1B is a cross-sectional view illustrating a state in which the stacked chip capacitor of FIG. 1A is mounted on a printed circuit board.

2 is a photograph of a stacked chip capacitor in which cracks are generated due to thermal shock.

3 is a graph showing a failure rate of a stacked chip capacitor according to the number of thermal shocks.

4 is a schematic diagram for explaining the conditions for improving the mechanical reliability of the stacked chip capacitor according to the present invention.

6 is a graph for explaining the thermal shock test employed in the present invention.

7 is a schematic diagram for explaining the flexural strength test employed in the present invention.

<Code Description of Main Parts of Drawing>

10: stacked chip capacitor 11,51: capacitor body

12a and 12b: first and second internal electrodes 55a and 55b: first and second external electrodes

55a ', 55b': Band portion 21,61: Printed circuit board

The present invention relates to a multilayer chip capacitor, and more particularly to a multilayer chip capacitor having excellent mechanical reliability in terms of thermal shock and bending strength.

In general, a multilayer chip capacitor (hereinafter referred to as MLCC) has a structure in which internal electrodes are inserted between a plurality of dielectric layers. These MLCCs are widely used as mobile communication device components such as computers, PDAs, and mobile phones because of their small size, high capacity, and easy mounting.

1A is a cross-sectional view showing a conventional stacked chip capacitor. As shown in FIG. 1A, the stacked chip capacitor 10 includes a capacitor body 11 formed by stacking a plurality of dielectric layers. The capacitor body 11 includes at least one pair of first and second internal electrodes 12a and 12b disposed to face each other with one dielectric layer interposed therebetween. In addition, first and second external electrodes 15a and 15b are formed at opposite end surfaces of the capacitor body 11 so as to be connected to the first and second internal electrodes 12a and 12b, respectively.

The multilayer chip capacitor 10 is mounted on the conductive lands 25a and 25b of the printed circuit board 21 as shown in FIG. 1B, and the first and second external electrodes are formed by solders 27a and 27b. 15a and 15b and the respective conductive lands 25a and 25b are mechanically and electrically connected to each other.

Since the stacked chip capacitor 10 is mainly used around a power source and is used at high temperature conditions and is mounted on the flexible printed circuit board 21, it may be easily exposed to mechanical shock due to heat or warpage. In fact, such a mechanical shock may cause cracks in the dielectric layer of the stacked chip capacitor as shown in FIG. 2, and in a severe case, a short may cause a problem in that the device function is lost.

In addition, defects caused by mechanical shock are more seriously generated as the chip thickness is thinner, which causes a problem in thinning the chip size. Referring to FIG. 3, it can be seen that a MLCC having a thickness of 0.65 mm has a high failure rate of seven times when ten thermal shocks are applied to a MLCC having a thickness of 1.25 mm.

Therefore, the multilayer chip capacitor in the thinning direction is required to have a better mechanical reliability, that is, improved thermal shock and flexural strength reliability in consideration of poor use environment.

In order to solve this problem, according to US Patent No. 6,350,759 (Auditor: TDK, registered date: October 30, 2001), when mounting the external electrode of the stacked chip capacitor on the conductive land of the printed circuit board, a separate metal terminal Although a method of mitigating stress generation by using the same has been disclosed, since it uses an additional structure of a metal terminal, the ease of the mounting process is reduced and there is a need to manufacture a separate structure.                         

Therefore, there is a strong demand in the art for a method for improving mechanical reliability by improving a structure of a stacked chip capacitor itself.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, without using additional structures, by finding the factors of the stacked chip capacitor itself related to mechanical reliability, and by improving the structure of the stacked chip capacitor in accordance with the correlation between these factors SUMMARY To provide a stacked chip capacitor having excellent mechanical reliability.

In order to achieve the above technical problem, one embodiment of the present invention provides a

A capacitor body having a plurality of dielectric layers stacked thereon and having at least one pair of first and second internal electrodes disposed to face each other with one dielectric layer interposed therebetween, and the capacitor body being connected to the first and second internal electrodes, respectively; In a stacked chip capacitor including first and second external electrodes formed on opposite opposing surfaces, the thickness of the external electrode is t (µm), the height of the capacitor body is H (mm), and the thickness of the dielectric layer When the breakdown strength is Y (Mpa), the correlation between the thickness of the external electrode and the height of the capacitor body with respect to the breakdown strength of the dielectric layer is

Y ≥154.91 + 1.487t-89H

It provides a stacked chip capacitor, characterized in that to satisfy.                     

Preferably, when the dielectric layer is made of a dielectric material having B characteristics, the thickness of the external electrode may be 4% or less of the thickness of the capacitor body, and the thickness of the external electrode may be a plating material when forming a plating layer. At least 13 µm is preferable so as not to penetrate into the dielectric layer and deteriorate capacitor characteristics.

Furthermore, another aspect of the present invention is a capacitor body formed by stacking a plurality of dielectric layers and having at least one pair of first and second internal electrodes disposed to face each other with a dielectric layer interposed therebetween, and the first and second internal parts. In a stacked chip capacitor including first and second external electrodes respectively formed on opposite end surfaces of the capacitor main body so as to be connected to electrodes, respectively, wherein the first and second external electrodes extend to upper and lower surfaces of the capacitor main body. Where the width of the band portion is w (µm), the thickness of the external electrode is t (µm), and the breaking strength of the dielectric layer is Y (Mpa), the band portion with respect to the breaking strength of the dielectric layer The correlation between the width and the thickness of the external electrode

Y ≥121.03-0.0475w + 1.075t

It provides a stacked chip capacitor, characterized in that to satisfy.

Preferably, the width of the band portion is preferably 650 μm or less in order to prevent short between two other external electrodes.

One embodiment of the present invention described above is derived as a way to improve the reliability of the thermal shock, the other form is derived as a way to improve the reliability due to the bending phenomenon. These two types may be considered separately in order to manufacture a stacked chip capacitor having excellent mechanical reliability, but more preferably, considering both aspects, the external electrode thickness and the bandwidth of the stacked chip capacitor, and the chip height Can be reflected in the design.

Hereinafter, with reference to the accompanying drawings, it will be described in more detail the factors and the correlation of the stacked chip capacitor considered in order to improve the mechanical reliability in the present invention.

In general, factors that significantly affect the mechanical reliability of stacked chip capacitors are known as thermal shock and flexural impact. In consideration of this, the present inventor derives a design factor of a stacked chip capacitor having a high correlation with mechanical reliability due to thermal shock and flexural impact.

4 is a schematic diagram illustrating design factors of a stacked chip capacitor that can be considered for improving mechanical reliability according to the present invention.

As shown in FIG. 4, the thickness of the external electrodes 55a and 55b, the widths of the bands 55a ′ and 55b ′, and the height of the capacitor body 51 may be considered as main design factors of the stacked chip capacitor 50. . The band portions 55a 'and 55b' are portions of the external electrodes 55a and 55b that extend from both side portions to other surfaces. Here, the band portions 55a 'and 55b' are shown to be located only on the upper and lower surfaces of the capacitor 51, but may also be understood to be located on other surfaces (front and rear) that are not shown.

Further, as factors to be considered during mounting, the height Hs of the solders 67a and 67b, the gap d between the conductive lands 65a and 65b, and the thickness ts of the solder 67a and 67b at the bottom of the chip may be considered. However, since the matter is not related to the structure of the stacked chip capacitor 50 itself, it has not been considered in the present invention for changing the stacked chip capacitor structure.

Experiment on Thermal Shock Reliability

In order to derive the design factors and the correlations between thermal shock reliability, a stacked chip capacitor (size: 20 x 12 (mm)) was prepared as described in Table 1 below, and the printed circuit board (material: FR4).

Here, the stacked chip capacitor 50 is mounted so as to be symmetrical with respect to the center point between the conductive lands 65a and 65b. Conventional examples can be understood as a conventional stacked chip capacitor, Experimental Examples 1 to 3 are applied to the other design factors in the same manner as the conventional example, the thickness (t) of the external electrodes (55a, 55b), the capacitor body, respectively The height H of 51 and the width w of the band portions 55a 'and 55b' were applied differently.

The thermal shock test was done about four samples provided in this way. Thermal shock conditions were applied as shown in the graph shown in FIG. In other words, the thermal shock test was carried out at -55 ° C for 15 minutes, then raised to 125 ° C within 10 seconds and held for another 15 minutes. After measuring the maximum principal stress applied to the stacked chip capacitor by the thermal shock test, the maximum principal stress difference between the conventional example and each experimental example was calculated. Table 2 below shows the results.

As shown in Table 2 above, it can be seen that in the Experimental Example 1 and Experimental Example 2, a larger stress difference is generated in Experimental Example 3. Through the above experimental results, when the thickness t of the external electrode and the height of the capacitor body H are changed (Experimental Examples 1 and 2), the stress due to thermal shock can be changed greatly, and the two design factors are thermal shock. It can be set as an important factor that can be considered in the reliability of.

Based on this experiment, the regression equation of the maximum principal stress (Ysa, unit: MPa) applied to the stacked chip capacitor based on the thickness t of the external electrode and the height H of the capacitor body was derived as follows.

Ysa = 154.91 + 1.487t-89H ------------------------------------ Formula (1)

Based on Equation 1, the thickness t of the external electrode and the height H of the capacitor body, provided that the maximum principal stress Ysa does not exceed the breaking strength (Y, unit: MPa) of the dielectric layer constituting the body. Can be defined as

Y ≥ 154.91 + 1.487t-89H ------------------------------------ Formula (2)

In general, since the thickness (H) of the capacitor body considering the chip size and the dielectric material used in the stacked chip capacitor is specified, the upper limit of the thickness of the external electrode can be derived based on Equation (2). Therefore, according to the conditions of the present invention, it is possible to design a stacked chip capacitor so that thermal shock reliability is improved.

For example, in the case of manufacturing a stacked chip capacitor using a dielectric layer having a B characteristic, the breakdown strength of the B characteristic dielectric layer is 102 Mpa. Therefore, the thickness of the external electrode is 4 times the thickness of the capacitor body in consideration of Equation (2). It is desirable to design below%. In addition, in another aspect, when the plating layer is formed, the plating material may penetrate into the dielectric layer so that the capacitor characteristics may be deteriorated. In order to prevent this, the thickness of the external electrode is preferably at least 13 μm.

Experiment on Flexural Strength Reliability

In the experiment on the flexural strength reliability, four samples were prepared and the flexural strength test was measured as in the thermal shock reliability test described above. In this flexural strength test, as shown in Fig. 6, fixtures are placed on both ends of a printed circuit board approximately 45 mm (± 1) from the center position where the stacked chip capacitors are mounted, and 50 × The maximum principal stress applied to the stacked chip capacitor when applying a pressure with a punch having a curved surface (R = 340) of 20 mm was obtained through stress analysis. (The bending limit value in Fig. 6 represents the bending length in which fracture occurs as the bending strength. )

As a result of analyzing the difference between the maximum principal stress of each experimental example measured and the maximum principal stress of the conventional example, the width (w) of the external electrode band portion and the thickness (t) of the external electrode could be set as important design factors.

Based on this experiment, the regression equation of the maximum principal stress (Ysb, unit: MPa) applied to the stacked chip capacitor based on the thickness t and the band width w of the external electrode was derived as follows.

Ysb ≥121.03-0.0475w + 1.075t -------------------------------- Formula (3)

Based on Equation 3, the thickness t of the external electrode and the width of the band portion w of the external electrode provided that the maximum principal stress Ysb does not exceed the breaking strength (Y, unit: MPa) of the dielectric layer constituting the main body. Correlation can be defined as

Y ≥121.03-0.0475w + 1.075t ---------------------------------- Formula (4)

In general, since the dielectric material used for the stacked chip capacitor is specified, the upper limit of the thickness of the external electrode with respect to the band width w or the lower limit of the width of the band width w with respect to the external electrode thickness is based on Equation (4). Can be derived. In addition, in another aspect, in order to prevent a short due to excessive extension of the external electrode band portion, the thickness (w) of the band portion is preferably designed to be 650 μm or less.

In addition, by designing a stacked chip capacitor using Equation (4) together with Equation (2) obtained in the thermal shock reliability test, it is possible to manufacture a stacked chip capacitor having better mechanical reliability. For example, based on Equation (2), in the case where the size of the stacked chip capacitor and the dielectric material are specified, an appropriate thickness (w) range of the external electrode for the size (i.e. the capacitor body height) is derived, In consideration of this, the band portion of the appropriate external electrode may be applied in a manner of designing an appropriate width range.

Hereinafter, the effect of the present invention through the embodiments of the present invention will be described in more detail.

(Example)

First, a conventional stacked chip capacitor (comparative example) and a stacked chip capacitor (invention example) satisfying the conditions of the present invention were simulated under the conditions shown in Table 3 below.

division Comparative example Inventive Example Average Scatter Average Scatter Band part width (㎛) 590 50 590 32.5 External electrode thickness (㎛) 24.4 2.49 13 2.49 Body height (mm) 0.834 0.00647 0.88 0.00647

After mounting each stacked chip capacitor according to the comparative example and the invention example on a printed circuit board (material: FR4) under the conditions shown in Table 1, the thermal shock test (see FIG. 5) and the bending strength test (see FIG. 6). Corresponding simulations were performed.

As a result, the thermal shock reliability of the comparative example and the invention example is shown in Table 4 below.

division Comparative example Inventive Example Spec / Average Defective rate (σ) Spec / Average Defective rate (σ) Thermal shock 1000 (spec) 2.0 1000 (spec) 6.0 Flexural strength (mm) 2 (average) 2.17 4.3 (average) 5.4

As shown in Table 4 above, the inventive example significantly reduced the failure rate from 2 sigma level to 6 sigma level when applying 1000 thermal shocks before failure, and the flexural strength not only increased about 2.3 (mm) but also the failure rate. It was confirmed that the defective rate was reduced to about 3 sigma. As such, in the multilayer chip capacitor according to the present invention, a greatly improved mechanical reliability can be expected.

The present invention is not limited to the above-described embodiment and the accompanying drawings, and various forms of substitution by those skilled in the art without departing from the technical spirit of the present invention described in the claims, Modifications and variations will be possible and will also be within the scope of this invention.

As described above, according to the present invention, the thickness of the external electrode and the width of the band portion are appropriately designed and manufactured in consideration of the height of the capacitor body, which is highly related to thermal shock and / or bending strength, thereby greatly improving the mechanical reliability of the multilayer chip capacitor. Can be. Therefore, the stacking chip capacitor having excellent mechanical reliability can be manufactured in a simpler manufacturing process by appropriately changing the design factor of the stacking chip capacitor itself without adding a separate structure as in the prior art.

Claims (6)

A capacitor body having a plurality of dielectric layers stacked thereon and having at least one pair of first and second internal electrodes disposed to face each other with one dielectric layer interposed therebetween, and the capacitor body being connected to the first and second internal electrodes, respectively; In the stacked chip capacitor including a first and a second external electrode formed on opposite opposing surfaces, respectively, When the thickness of the external electrode is t (µm), the height of the capacitor body is H (mm), and the breaking strength of the dielectric layer is Y (Mpa), the thickness of the external electrode with respect to the breaking strength of the dielectric layer And the height of the capacitor body Y ≥154.91 + 1.487t-89H Stacked chip capacitors, characterized in that to satisfy. The method of claim 1, The dielectric layer is made of a dielectric material having a B characteristic, The thickness of the external electrode is a stacked chip capacitor, characterized in that less than 4% of the thickness of the capacitor body. The method of claim 1, The thickness of the external electrode is a stacked chip capacitor, characterized in that at least 13㎛. The method of claim 1, The first and second external electrodes have a band portion extending to the upper and lower surfaces of the capacitor body, and when the width of the band portion is w (µm), the width of the band portion and the external electrode relative to the breaking strength of the dielectric layer are determined. Thickness correlation Y ≥121.03-0.0475w + 1.075t Stacked chip capacitors, characterized in that to satisfy. The method of claim 1, Stacked chip capacitors, characterized in that the width of the band portion is less than 650㎛. A capacitor body having a plurality of dielectric layers stacked thereon and having at least one pair of first and second internal electrodes disposed to face each other with one dielectric layer interposed therebetween, and the capacitor body being connected to the first and second internal electrodes, respectively; In the stacked chip capacitor including a first and a second external electrode formed on opposite opposing surfaces, respectively, The first and second external electrodes have a band portion extending to the upper and lower surfaces of the capacitor body, the width of the band portion is w (μm), the thickness of the external electrode is t (μm), and the breakdown strength of the dielectric layer is In the case of Y (Mpa), the correlation between the width of the band portion and the thickness of the external electrode with respect to the breaking strength of the dielectric layer is Y ≥121.03-0.0475w + 1.075t Stacked chip capacitors, characterized in that to satisfy.

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