KR20060080423A - Memory device controlling power line of distributed internal dc generator - Google Patents

Abstract

A memory device in which a power line of a distributed internal constant voltage generator is controlled is disclosed. A memory device according to an embodiment of the present invention includes a plurality of circuit groups, a voltage pad, and a plurality of switches. The plurality of circuit groups are arranged in a distributed manner. The voltage pad receives a predetermined test voltage from the outside to monitor a voltage level of a predetermined constant voltage generated in each of the plurality of circuit groups and to test the plurality of circuit groups. A plurality of switches control the connection of the plurality of circuit groups and the voltage pad in response to a predetermined control signal. Each of the plurality of circuit groups includes a constant voltage generator configured to generate the predetermined constant voltage therein and provide the predetermined constant voltage to each of the plurality of circuit groups. The memory device according to the present invention can reduce the number of voltage pads included in the memory device by controlling the connection between the distributed internal constant voltage generators and the single voltage pad using a switch operating in response to a predetermined control signal. There is an advantage, thereby reducing the size of the memory device.

Distributed arrangement, constant voltage generator

Description

Memory device controlled power line of distributed internal DC generator

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a conventional memory device having a single constant voltage generator.

2 is a block diagram of a conventional memory device having a distributed constant voltage generator.

3 is a block diagram of a memory device according to an exemplary embodiment of the present invention having a distributed constant voltage generator.

4 is a block diagram of a memory device according to an exemplary embodiment of the present invention having a distributed constant voltage generator generating two constant voltages.

5 is a circuit diagram of a switch used in an embodiment of the present invention.

The present invention relates to a memory device in which a power line of a distributed internal constant voltage generator is controlled. In particular, a connection between the distributed internal constant voltage generators and a single voltage pad in a memory device having a plurality of memory banks responds to a predetermined control signal. The present invention relates to a memory device controlled by using a switch that operates.

Generally, a small size memory device includes one single constant voltage generator that generates a predetermined constant voltage necessary for the operation of a circuit. For example, a bit line voltage generator for generating a voltage for selecting a bit line, a reference voltage generator for generating a predetermined reference voltage, and the like are disposed one by one in a small memory device.

However, as the size of the memory device increases, the arrangement of circuits to be powered by the constant voltage generator is distributed. In a memory device in which circuits are arranged in a distributed manner, when a single constant voltage generator is used, skew occurs at a power level according to the distance from the single constant voltage generator to the circuits, and the response speed of the circuit is reduced.

1 is a block diagram of a conventional memory device having a single constant voltage generator.

The memory device 100 includes a plurality of memory banks (bank A, bank B, ...) and peripheral circuits. The peripheral circuit includes a single constant voltage generator 110, a first peripheral circuit unit 120, a second peripheral circuit unit 130, and a voltage pad 140.

For convenience of description, only one constant voltage generator 110 and one voltage pad 140 are shown in FIG. 1, but the memory device 100 generates a plurality of constant voltages required for the operation of the memory device 100. Constant voltage generators, and a plurality of voltage pads connected to the respective constant voltage generators.

Referring back to FIG. 1, the constant voltage generator 110 generates a predetermined constant voltage necessary for the operation of the memory device 100. The generated predetermined constant voltage is provided to the plurality of memory banks (bank 1, bank 2,...) And the first and second peripheral circuit units 120 and 130 through a power line connected to the constant voltage generator 110.

On the other hand, most memory devices have a power pad. The power pad includes an external power voltage pad to which a power voltage from the outside is applied and an internal constant voltage pad connected to an internal constant voltage generator.

The internal constant voltage pad is used when the internal constant voltage generation unit malfunctions or when a voltage is forcibly applied when testing the semiconductor device, such as a burn-in test. In addition, the internal constant voltage pad is also used when monitoring the level of the constant voltage generated by the constant voltage generator. The voltage pad 140 shown in FIG. 1 is an internal constant voltage pad.

As shown in FIG. 1, since the constant voltage generator 110 needs to supply a predetermined constant voltage to the entire memory device, the driving size increases and the level feedback operation is degraded.

In addition, since the entire memory device is wired with a single power line connected to the constant voltage generator 100, the load of the power line is increased. In addition, there is a problem that skew occurs at the voltage level according to the distance from the constant voltage generator 100 to the banks.

In addition, since a single power line is connected to the plurality of constant voltage generators, skew occurs in power levels between the constant voltage generators. In addition, since the constant voltage generators feed back in response to the skew of the power levels generated between the constant voltage generators, there is a problem in that the standby current is increased due to the continuous operation of the constant voltage generators.

In order to overcome this problem, a method of distributing the constant voltage generator according to the distributed circuit arrangement has been proposed.

2 is a block diagram of a conventional memory device having a distributed constant voltage generator.

The memory device may include a portion I including a first bank group (bank 1, bank 2,...), A first constant voltage generator 211, a first peripheral circuit unit 213, and a first voltage pad 215. And a second bank group (bank A, bank B, ...), a second constant voltage generator 231, a second peripheral circuit 233, and a second voltage pad 235.

As shown in FIG. 2, the memory device 200 is distributed in a portion I which is supplied with a constant voltage by the first constant voltage generator 211 and a portion II which is supplied with a constant voltage by the second constant voltage generator.

The memory device 200 of FIG. 2 has the simplest connection type between the distributed constant voltage generator and the voltage pad. That is, the first voltage pad 215 and the second voltage pad 235 are connected to the first constant voltage generator 211 and the second constant voltage generator 231 arranged in a distributed manner.

However, as the number of pads increases, the size of the memory device increases, so in the case of distributing circuits, arrangement of voltage pads with respect to distributed constant voltage generators is important.

Currently, the size of the memory device is increasing at a rapid speed, and accordingly, the electrostatic pressure generators are also distributed in a plurality. In general, as the number of pads increases, the size of the memory device increases. Accordingly, there is a need to minimize the number of voltage pads connected to the constant voltage generator of the memory device.

SUMMARY OF THE INVENTION The present invention provides a memory device for controlling a connection between distributed internal constant voltage generators and a single voltage pad in a memory device having a plurality of memory banks using a switch operating in response to a predetermined control signal. To provide.

In accordance with another aspect of the present invention, a memory device includes a plurality of circuit groups, a voltage pad, and a plurality of switches. The plurality of circuit groups are arranged in a distributed manner. The voltage pad receives a predetermined test voltage from the outside to monitor a voltage level of a predetermined constant voltage generated in each of the plurality of circuit groups and to test the plurality of circuit groups. A plurality of switches control the connection of the plurality of circuit groups and the voltage pad in response to a predetermined control signal. Each of the plurality of circuit groups includes a constant voltage generator configured to generate the predetermined constant voltage therein and provide the predetermined constant voltage to each of the plurality of circuit groups.

The plurality of switches are turned off in a normal operation mode to allow each of the plurality of circuit groups to operate independently, turned on in a pad test mode to apply the test voltage to each of the plurality of circuit groups, and in a monitoring mode. Only the switch connected to the constant voltage generator to be monitored is turned on to monitor the voltage level of the predetermined constant voltage generated from the constant voltage generator to be monitored.

The predetermined control signal may be a mode register set (MRS) of the memory device.

In accordance with another aspect of the present invention, a memory device includes a first circuit group and a second circuit group, and a voltage pad, a first switch, and a second switch. The voltage pad receives a predetermined test voltage from the outside to monitor a voltage level of a predetermined constant voltage generated in the first and second circuit groups and to test the first and second circuit groups. The first switch controls the connection of the first group of circuits to the voltage pad in response to a predetermined control signal. The second switch controls the connection of the first group of circuits to the voltage pad in response to a predetermined control signal. The first circuit group includes a first constant voltage generator that generates the predetermined constant voltage and provides the first circuit group, and the second circuit group generates the predetermined constant voltage and provides the second constant voltage to the second circuit group. And a second constant voltage generator.

In accordance with still another aspect of the present invention, a memory device includes a plurality of circuit groups and a switch. The switch controls the connection between the plurality of circuit groups in response to a predetermined control signal. Each of the plurality of circuit groups includes a constant voltage generator and a voltage pad. The constant voltage generator generates two predetermined constant voltages having different levels and provides them to each of the plurality of circuit groups. The voltage pad receives a predetermined test voltage from outside to monitor the voltage level of the predetermined constant voltage and test the plurality of circuit groups.

The switch is turned off when the memory device operates in the normal operation mode and the monitoring mode, and is turned on when the memory device operates in the pad test mode.

According to another aspect of the present invention, there is provided a memory device including a first circuit group, a second circuit group, and a switch. The switch controls the connection between the first circuit group and the second circuit group in response to a predetermined control signal. The first circuit group includes a first constant voltage generator and a first voltage pad. The first constant voltage generator generates a predetermined first constant voltage and a second constant voltage having different levels and provides them to the first circuit group. The first voltage pad receives a predetermined first test voltage from the outside to monitor the voltage level of the first constant voltage and test the plurality of circuit groups. The second circuit group includes a second constant voltage generator and a second voltage pad. The second constant voltage generator generates a predetermined first constant voltage and a second constant voltage having different levels and provides them to the second circuit group. The second voltage pad receives a predetermined second test voltage from the outside to monitor the voltage level of the second constant voltage and test the plurality of circuit groups.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram of a memory device according to an exemplary embodiment of the present invention.

The memory device 300 according to an exemplary embodiment of the present invention is configured to supply a portion I to which a predetermined constant voltage generated by the first constant voltage generator 311 and a predetermined constant voltage generated by the second constant voltage generator 331 are supplied. It is arrange | positioned in part II. The I and II parts are connected to the voltage pad 350 through first and second switches operating in response to a predetermined control signal.

The part I includes a first bank group (bank 1, bank 2, ...), a first constant voltage generator 311, a first peripheral circuit 313, and a first switch 315. The part II includes a second bank group (bank A, bank B, ...), a second constant voltage generator 331, a second peripheral circuit 333, and a second switch 335.

The memory device 300 according to an embodiment of the present invention operates in three modes: a normal operation mode, a normal operation mode, a pad test mode, and a monitoring mode. The monitoring mode is a mode for monitoring a level of a predetermined constant voltage generated by the constant voltage generator.

The pad test mode is a mode in which a memory device is tested by forcibly applying a voltage level to a voltage pad or a burn-in test is performed in a case where the constant voltage generator malfunctions.                     

In each mode of operation, the first and second switches 315 and 335 control the connection between the voltage pad 350 and the I and / or II portions in response to a predetermined control signal CTRL.

Hereinafter, the operation of the switch according to each operation mode will be described.

First, initial states of the first and second switches are on and off states, respectively. Even in the normal operation mode, the first switch 315 is in an ON state, and the second switch 335 is in an OFF state. That is, part I and part II of the memory device 300 are separated from each other and operate independently of each other.

Therefore, in part I, the first constant voltage generator 311 generates a predetermined constant voltage, and the first bank group (bank 1, bank 2, ...) and the first peripheral circuit 313 respond to the predetermined constant voltage. To work.

In addition, in part II, the second constant voltage generator 331 generates a predetermined constant voltage, and the second bank group (bank A, bank A, ...) and the second peripheral circuit 333 respond to the predetermined constant voltage. To work.

In the pad test mode, the first and second voltage generators are kept off, and predetermined constant voltages are supplied to the I and II parts through the voltage pads. That is, both the I part and the II part operate by a predetermined constant voltage applied to the voltage pad.

Thus, in the pad test mode both the first and second switches are on.

Meanwhile, since the initial state of the first switch 315 is on, the voltage level generated by the first constant voltage generator 311 may always be monitored through the voltage pad 350.                     

Therefore, in the monitoring mode, the voltage level generated by the second constant voltage generator 331 is monitored through the voltage pad 350 by turning off the first switch 315 and turning on the second switch 335. .

As described above, unlike the conventional memory device 200 illustrated in FIG. 2, the memory device according to the embodiment of the present invention includes only one voltage pad 350. Therefore, the size of the memory device can be reduced compared to the conventional memory device 200.

4 is a block diagram of a memory device according to another exemplary embodiment of the present invention.

The constant voltage generators 411 and 431 shown in FIG. 4 generate two constant voltages VBL0 and VBL1 having different levels. As shown in FIG. 4, the constant voltage generator for generating two constant voltages having different levels includes a voltage pad.

The memory device 400 according to an exemplary embodiment of the present invention includes a portion I supplied with predetermined constant voltages VBL0 and VBL1 generated by the first constant voltage generator 411 and a predetermined portion generated by the second constant voltage generator 431. The constant voltages VBL0 and VBL1 are distributed in a portion II supplied thereto. Part I and part II are connected to each other via a switch 450 that operates in response to a predetermined control signal CTRL.

The part I includes a first bank group (bank 1, bank 2,...), A first constant voltage generator 311, and a first voltage pad switch 313. The part II includes a second bank group (bank A, bank B, ...), a second constant voltage generator 331, and a second voltage pad 333.

As shown in FIG. 4, the constant voltage VBL0 of the first level among the two constant voltages VBL0 and VBL1 generated by the first constant voltage generator 411 is displayed on the first voltage pad. In addition, of the two constant voltages VBL0 and VBL1 generated by the second constant voltage generator 411, the constant voltage VBL1 of the second level is displayed on the second voltage pad.

Hereinafter, the operation of the switch according to each operation mode will be described.

In the normal operation mode, part I and part II of the memory device 400 are separated from each other and operate independently of each other. Accordingly, the switch 450 is in an OFF state so that the I and II portions of the memory device 300 are separated from each other and operate independently of each other.

Accordingly, in part I, the first constant voltage generator 411 generates predetermined constant voltages VBL0 and VBL1, and the first bank group Bank1, bank2, ... is applied to the predetermined constant voltages VBL0 and VBL1. In response to).

On the other hand, in part II, the second constant voltage generator 431 generates predetermined constant voltages VBL0 and VBL1, and the second bank group Bank A, bank A, ... is provided with predetermined constant voltages VBL0 and VBL1. Operate in response to

On the other hand, when the switch is in the off state, the first voltage pad 413 shows the first level constant voltage VBL0, and the second voltage pad 433 shows the second level constant voltage VBL1.

When the switch is in the OFF state, the predetermined constant voltages VBL0 and VBL1 generated by the first and second constant voltage generators 411 and 431 by monitoring the voltages of the first voltage pad 413 and the second voltage pad 433. ) Level can be monitored.

That is, the switch is turned off in the monitoring mode as in the normal operation mode.                     

In the pad test mode, the first and second voltage generators 411 and 431 are kept in an off state, and predetermined portions of the first and second voltage generators 411 and 431 are supplied through voltage pads. That is, both the I part and the II part operate by a predetermined constant voltage applied to the voltage pad.

In the pad test mode, a voltage of the first level VBL0 is applied to the first voltage pad 413 and a voltage of the second level VBL1 is applied to the second voltage pad 433.

Meanwhile, since the constant voltages of the first level VBL0 and the second level VBL1 are to be applied to the parts I and II, the switch is turned on to the first voltage pad 413 and the second voltage pad 433. Ensure that the applied voltage is applied to both I and II parts.

As described above, since the first and second constant voltage generators 411 and 431 of the memory device 400 according to the embodiment of the present invention have voltage pads, separate switches are used in the normal operation mode and the monitoring mode. I don't need it.

However, in the pad test mode, each of the constant voltages VBL0 and VBL1 supplied to the voltage pads 413 and 433 is provided with a switch to supply both the I part and the II part. Separate parts and and part II. In pad test mode, connect parts I and II.

5 is a circuit diagram of a switch used in an embodiment of the present invention.

The switch 500 includes an inversion unit INV, a PMOS transistor P1, and an NMOS transistor N1. The switch is controlled in response to the predetermined control signal EN.

The control signal EN is input to the gate of the NMOS transistor N1, and the inverted control signal is input to the gate of the PMOS transistor P1. When the high level control signal EN is inputted, the NOMS transistor and the PMOS transistor are turned on and the switch is turned on.

In addition, when the low-level control signal EN is input, the NMOS transistor N1 and the PMOS transistor P1 are turned off, and the switch is turned off.

In an embodiment of the invention, the control signal (EN) for controlling the operation of the switch may be generated by an external control unit (not shown), using a mode register set of the memory device or by using a fuse May occur.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the memory device according to the present invention controls the connection between the distributed internal constant voltage generators and the single voltage pad by using a switch operating in response to a predetermined control signal to control the number of voltage pads included in the memory device. There is an advantage that can be reduced, thereby reducing the size of the memory device.

Claims (14)

A plurality of circuit groups arranged in a distributed manner; A voltage pad for monitoring a voltage level of a predetermined constant voltage generated in each of the plurality of circuit groups and receiving a predetermined test voltage from an external source for testing the plurality of circuit groups; And A plurality of switches for controlling a connection between the plurality of circuit groups and the voltage pad in response to a predetermined control signal, Each of the plurality of circuit groups may include a constant voltage generator configured to generate the predetermined constant voltage therein and provide the predetermined voltage to each of the plurality of circuit groups. The method of claim 1, wherein the plurality of switches, Off in the normal operation mode to allow each of the plurality of circuit groups to operate independently; Turned on in a pad test mode to cause the test voltage to be applied to each of the plurality of circuit groups, And a switch connected to the constant voltage generator to be monitored in the monitoring mode to monitor the voltage level of the predetermined constant voltage generated by the constant voltage generator to be monitored. The method of claim 1, And the predetermined control signal is a mode register set (MRS) of the memory device. A memory device having a first circuit group and a second circuit group arranged in a distributed manner, the memory device comprising: A voltage pad for monitoring a voltage level of a predetermined constant voltage generated in the first and second circuit groups and receiving a predetermined test voltage from an outside to test the first and second circuit groups; A first switch controlling a connection between the first circuit group and the voltage pad in response to a predetermined control signal; And A second switch controlling a connection between the first circuit group and the voltage pad in response to a predetermined control signal, The first circuit group includes a first constant voltage generator that generates the predetermined constant voltage and provides the first circuit group to the first circuit group. And the second circuit group includes a second constant voltage generator which generates the predetermined constant voltage and provides the second circuit group to the second circuit group. The method of claim 4, wherein the first and second switches, Control the connection to operate independently of the first and second groups of circuits in normal operation mode, Control the connection such that the test voltage is applied to the first and second circuit groups in a pad test mode, And controlling the connection such that the voltage pad is connected to the constant voltage generator to be monitored among the first and second constant voltage generators in the monitoring mode. The method of claim 4, wherein In the normal operation mode, the first switch and the second switch are both off, In the pad test mode, both the first switch and the second switch are on, And a switch connected to the constant voltage generator to be monitored among the first switch and the second switch in the monitoring mode is on and the other switch is off. The method of claim 4, wherein And the predetermined control signal is a mode register set (MRS) of the memory device. A memory device having a plurality of circuit groups arranged in a distributed manner, A switch for controlling a connection between the plurality of circuit groups in response to a predetermined control signal, Each of the plurality of circuit groups, A constant voltage generator which generates two predetermined constant voltages having different levels and provides them to each of the plurality of circuit groups; And And a voltage pad for monitoring a voltage level of the predetermined constant voltage and receiving a predetermined test voltage from an external source for testing the plurality of circuit groups. The method of claim 8, wherein the switch, When the memory device operates in the normal operation mode and the monitoring mode, On when the memory device operates in a pad test mode. The method of claim 8, And the predetermined control signal is a mode register set (MRS) of the memory device. A memory device having a first circuit group and a second circuit group arranged in a distributed manner, the memory device comprising: A switch controlling a connection between the first circuit group and the second circuit group in response to a predetermined control signal, The first circuit group, A first constant voltage generator for generating a first constant voltage and a second constant voltage having different levels and providing the first constant voltage to the first circuit group; And A first voltage pad for monitoring a voltage level of the first constant voltage and receiving a predetermined first test voltage from an external source for testing the plurality of circuit groups, The second circuit group, A second constant voltage generator configured to generate predetermined first constant voltages and second constant voltages having different levels, and provide them to the second circuit group; And And a second voltage pad configured to receive a second predetermined test voltage from the outside to monitor the voltage level of the second constant voltage and to test the plurality of circuit groups. The method of claim 11, wherein the switch, In the normal operation mode, the connection is controlled such that the first and second circuit groups operate independently of each other In the monitoring mode, the connection is controlled such that the voltage level of the first constant voltage is monitored at the first voltage pad and the voltage level of the second constant voltage is monitored at the second voltage pad, In the pad test mode, the first test voltage is applied to the first voltage pad and the second test voltage is applied to the second voltage pad, so that first and second test voltages are applied to the first and second circuit groups. And control the connection so that it is provided. The method of claim 11, wherein the switch, Off in the normal operation mode and the monitoring mode, Memory device characterized in that it is turned on in a pad test mode. The method of claim 10, And the predetermined control signal is a mode register set (MRS) of the memory device.

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