KR20060074183A - Focus inspecting mask and method for inspecting focus of exposing apparatus using the same - Google Patents

Abstract

According to a focus inspection method that can effectively detect and set whether or not the exposure apparatus is larger than a focal length, the focus inspection mask having the focus mask patterns formed at different depths is irradiated with light so that the focus mask patterns on the wafer may have different focal lengths. To be projected. The wafer is developed to form predetermined focus test patterns, and the formed focus test patterns are inspected to select one pattern that meets a predetermined standard. The focus of the exposure apparatus is adjusted based on the focal length corresponding to the selected one pattern. The focus inspection mask can be used to easily detect the optimum focal length of the exposure apparatus. Therefore, not only can the semiconductor pattern be accurately formed on the wafer, but also the time and financial losses required to adjust the focus of the exposure apparatus can be greatly reduced.

Description

FOCUS INSPECTING MASK AND METHOD FOR INSPECTING FOCUS OF EXPOSING APPARATUS USING THE SAME}

1 is a first cross-sectional view for describing a focus test mask according to an exemplary embodiment of the present invention.

FIG. 2 is a second cross-sectional view of the focus inspection mask illustrated in FIG. 1.

FIG. 3 is a flowchart for describing a method of inspecting a focal length of an exposure apparatus using the focus inspection mask illustrated in FIG. 1.

FIG. 4 is a conceptual diagram illustrating a step of projecting the focus mask patterns of FIG. 3 to different focal points.

FIG. 5 is a schematic graph for explaining a phase of light irradiated onto a wafer in the exposure step of FIG. 3.

<Description of the symbols for the main parts of the drawings>

100: Focus inspection mask 110: Mask board

120: focus mask pattern 121: first focus mask pattern

122: second focus mask pattern 123: third focus mask pattern

130: circuit mask pattern 141: first focusing position                 

142: Second focus position 143: Third focus position

151: First phase graph 152: Second phase graph

153: Third phase graph

The present invention relates to a focus inspection method of an exposure apparatus and a focus inspection mask for performing the same. More particularly, the present invention relates to a focus inspection method of an exposure apparatus used in a photolithography process among wafer processing processes and a focus inspection mask for performing the same.

In general, a semiconductor device is manufactured through a number of processes such as an ion implantation process, a deposition process, a diffusion process, a photolithography process, and the like. Among these processes, a photolithography process is performed to form a predetermined circuit pattern on the wafer.

The photolithography process includes a coating process for forming a photoresist composition layer on a wafer, a baking process for curing the coated photoresist solution into a photoresist film, and an exposure process for transferring a pattern formed on a mask to the photoresist film. And a developing step for forming the mask pattern transferred to the wafer into the photoresist pattern.

An apparatus for performing an exposure process in a photolithography process may include a light source, an illumination unit for converting point light emitted from the light source into surface light, condensing a predetermined size, a mask stage for supporting a mask, And a projection optical unit for irradiating the projection light passing through the mask onto the wafer, a wafer stage for supporting the wafer, and the like. Examples of such exposure apparatuses are disclosed in US Pat. No. 6,331,885 issued to Nishi and US Pat. No. 6,538,719 issued to Takahashi et al.

Illumination light generated from the light source is irradiated onto the mask through the illumination unit during the exposure process to the dead regions, and projection light passed through the mask is irradiated onto the wafer through the projection optical unit. In this case, a mask pattern is formed in the mask corresponding to the image to be transferred to the plurality of yarn regions set on the wafer. A mask stage for supporting the mask is disposed above the projection optical unit, and a wafer stage for supporting a wafer is disposed below the projection optical unit.

In order to accurately transfer the mask pattern to the shot region of the wafer, it is important to focus the light passing through the projection optical unit on the wafer upper surface. The position where light passing through the projection optical unit with respect to the wafer upper surface is formed is called a depth of focus (DoF).

As the miniaturization of current circuit patterns is accelerated, design rules continue to decrease, and in order to comply with them, the margin of error of the depth of focus continues to decrease. In other words, efforts have been made to ensure that the focus of the light passing through the projection optical unit is exactly as accurate as possible on the wafer upper surface.                         

When light collects at a position that is too low from the top surface of the wafer, the pattern is formed lower than the target and thicker. On the contrary, when light is collected at a position that is too high from the upper surface of the wafer, the pattern is formed higher and thinner than the target value. Therefore, it is important to collect light as close to the top surface of the wafer as possible.

However, according to the focus inspection method of the current exposure apparatus, one wafer is selected from among the wafers on which the exposure and development processes are performed, the pattern formed on the selected wafer is visually inspected, and then analyzed to change the setting of the exposure apparatus. . This not only makes it impossible to accurately set the exposure apparatus, but also generates considerable time and financial losses. Therefore, there is an urgent need for alternatives.

The present invention has been made to solve the above-described problems of the prior art, an object of the present invention is to provide a focus inspection method of the exposure apparatus that can effectively inspect and set the focus abnormality of the exposure apparatus.

Another object of the present invention is to provide a focus inspection mask for performing a focus inspection method of the exposure apparatus.

In order to achieve the above object of the present invention, a focus inspection mask according to a preferred embodiment of the present invention is formed to have a different depth on the mask substrate and the mask substrate, the mask pattern is projected at different focal lengths on the wafer Include them. In this case, the upper surfaces of the mask patterns have the same height, and the upper surface of the mask substrate is partially etched such that the mask patterns have different depths.

According to another preferred embodiment of the present invention, a focus inspection method of an exposure apparatus according to another embodiment of the present invention is directed to irradiating light onto a focus inspection mask in which mask patterns are formed at different depths so that each of the focus mask patterns on the wafer is different. Try to project at different focal lengths. The semiconductor substrate is developed to form predetermined focus inspection patterns, and the size of the formed patterns is inspected to select one pattern that meets a predetermined standard. The focus of the exposure apparatus is adjusted based on the focal length corresponding to the selected one pattern.

According to the present invention, it is possible to easily detect the optimum focal length of the exposure apparatus by using the focus inspection mask to effectively perform abnormality detection and setting of the focal length. Therefore, not only can the semiconductor pattern be accurately formed on the semiconductor substrate, but also the time and financial losses required to adjust the focus of the exposure apparatus can be greatly reduced.

Hereinafter, a focus inspection method and a focus inspection mask of an exposure apparatus according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited or limited by the following embodiments.

1 is a first cross-sectional view illustrating a focus test mask according to an exemplary embodiment of the present invention, and FIG. 2 is a second cross-sectional view of the focus test mask illustrated in FIG. 1. 1 is a cross-sectional view of a focus inspection mask taken along focus mask patterns, and FIG. 2 is a cross-sectional view taken along circuit mask patterns.                     

1 and 2, the focus inspection mask 100 is an apparatus for forming a predetermined focus inspection pattern on a wafer, and includes a mask substrate 110 and focus mask patterns 120.

The mask substrate 110 is preferably made of a glass substrate (quartz). Focus mask patterns 120 are formed on the mask substrate 110 corresponding to a predetermined focus inspection pattern to be formed on the wafer.

The focus mask patterns 120 may be manufactured at the same scale or reduced scale as the focus check pattern. In the present embodiment, the focus mask patterns 120 manufactured at a reduced scale will be described.

The focus mask patterns 120 are formed to have different depths on the mask substrate 110. In more detail, a mask layer is formed on the mask substrate 110. In this case, the mask layer is preferably made of chromium (Cr). In addition, the chromium (Cr) layer is preferably formed to a thickness of about 1000 to 1300 kPa.

Next, a photoresist film whose characteristics are changed by specific light is formed on the mask layer. In this case, the photoresist film is formed to a thickness of about 3000 to 4000 GPa. The photoresist film is exposed to correspond to the shape of the focus mask patterns 120 and then a development process is performed to form the focus mask patterns 120.

Subsequently, a photoresist film is formed on the focus mask patterns 120 formed through the development process, and only a portion of the mask patterns are exposed to be exposed, and then the development process is performed. Next, an etching process is performed. In this case, the mask substrate 110 between the focus mask patterns 120 is also partially etched.

As described above, the focus mask patterns 120 having different depths are formed on the mask substrate 110 while repeatedly performing the deposition, exposure, development, and etching processes. The difference in depth of the focus mask patterns 120 may be within a few to several tens of microseconds. Thus, the top surfaces of the focus mask patterns 120 have the same height, but have different depths.

When the focus mask patterns 120 have different depths, the phase of the light passing through the mask substrate 110 is inverted or shifted. A phase difference between light passing through the etched portion of the mask substrate and light passing through the unetched portion occurs. In addition, the phase difference of the transmitted light also occurs depending on the degree of etching.

It is preferable to adjust the depths of the focus mask patterns 120 such that the optical phase differences of the focus mask patterns 120 are 占 15 degrees apart based on 180 degrees. In further development, the focus mask patterns 120 may be formed at the peripheral portion of the mask substrate 110, and the circuit mask patterns corresponding to a predetermined circuit pattern to be formed on the wafer at the center of the mask substrate 110 ( 130). That is, the circuit mask patterns 130 are exposed on the wafer and the focus mask patterns 120 are simultaneously exposed. In this case, the focus mask patterns 120 are projected on the scribe lane of the wafer, and the circuit mask patterns 130 are projected on the cell region.

The focus inspection mask 100 according to the present exemplary embodiment may form the focus mask patterns 120 at various focal lengths by partially etching the mask substrate 110 without forming a phase inversion film on the mask substrate 110. Can be. In addition, by forming the focus mask patterns 120 on the peripheral portion of the mask substrate 110, the focus mask patterns 120 and the circuit mask patterns 130 may be simultaneously exposed.

FIG. 3 is a flowchart illustrating a method of inspecting a focus of an exposure apparatus using the focus inspection mask illustrated in FIG. 1, and FIG. 4 is a step of projecting the focus mask patterns of FIG. 3 to different focal points. FIG. 5 is a schematic diagram illustrating the phase of light projected onto a wafer. FIG.

1 to 5, first, a focus inspection mask 100 in which focus mask patterns are formed at different depths is prepared (S110). The focus test mask 100 has been described in the above embodiment, and thus duplicated description thereof will be omitted.

Subsequently, the focus inspection mask 100 is irradiated with light to expose the focus mask patterns on the wafer W at different focal lengths (S120). In this case, on the wafer W, a photoresist film whose characteristics are changed by specific light is formed. In this case, it is preferable to use an electron beam having a wavelength of about 0.12 GHz. This is because when the photoresist film is exposed using an electron beam, the process margin is relatively increased as compared with the case of using lamp light, and the uniformity of the pattern is lowered due to the interference between the photoresist film and the lower film light or the standing wave effect. Because it can improve. However, lamp light or laser light may also be used in some cases.

The light transmitted through the focus inspection mask 100 is projected on the wafer W at different focal lengths. In more detail, as shown in FIG. 4, light transmitted through the mask substrate 100 on one side of the first focus mask pattern 121 is collected at the first focus position 141 from the upper surface of the wafer W. . In this case, the mask substrate 100 on one side of the first focus mask pattern 121 is not etched, and the first phase graph 151 at this time is a reference.

The light transmitted through the mask substrate 100 on one side of the second focus mask pattern 122 is collected at the second focus position 142 from the upper surface of the wafer W. In this case, the mask substrate 100 on one side of the second focus mask pattern 122 is etched by several tens to hundreds of microseconds, and the second focus position 142 is lower than the first focus position 141. In addition, the second phase graph 152 at this time is shifted upward than the first phase graph 151.

The light transmitted through the mask substrate 100 on one side of the third focus mask pattern 123 is collected at the third focus position 143 from the upper surface of the wafer W. In this case, the mask substrate 100 on one side of the third focus mask pattern 123 is etched by several hundreds to thousands of microseconds, and the third focus position 143 is higher than the first focus position 141. In addition, the third phase graph 153 at this time is shifted down than the first phase graph 151.

As shown in FIG. 4, when the first focus position 141 is positioned above the upper surface of the wafer W, the second focus position 142 may be positioned on the upper surface of the wafer W, and the third The focus position 143 may be located far above the top surface of the wafer W. As shown in FIG. Naturally, in the case of the second focus mask pattern 122 which focuses on the upper surface of the wafer W, a circuit pattern may be formed accurately.

As described above, after the exposure process is performed at various focal lengths based on the focus inspection mask 100 (S120), the exposed wafer W is developed (S130). As a result, predetermined focus inspection patterns are formed on the wafer W. As shown in FIG.

Subsequently, the size of the focus inspection pattern is inspected to select a focus inspection pattern that meets a predetermined standard (S140), and the focus of the exposure apparatus is adjusted based on the focal length corresponding to the selected focus inspection pattern (S150).

The inspection criterion of the focus inspection patterns is set from information on the focus inspection pattern exposed at the optimum focus as a reference for the height, width, coordinates, etc. of the focus inspection pattern. Techniques for setting the inspection criteria of the focus inspection patterns are already known in many publications, and can be set differently for each manufacturer, so a detailed description thereof will be omitted. However, those skilled in the art will readily understand this.

The method of focusing an exposure apparatus means disposing a regular mask (not shown) in which circuit mask patterns are formed or adjusting optical fixtures so as to correspond to a focal length corresponding to a focus inspection pattern. The regular mask is a mask in which only the circuit mask patterns 130 are formed without the focus mask patterns 120 and is a mask used under the assumption that the focus of the exposure apparatus is set correctly. Since the method of adjusting the focus of the exposure apparatus is substantially the same as in the related art, description thereof will be omitted, but it will be readily understood by those skilled in the art.

In further development, the focus mask patterns 120 are formed at the peripheral portion of the mask substrate 110, and a circuit mask corresponding to a predetermined circuit pattern to be formed on the wafer W at the center of the mask substrate 110. Patterns 130 are formed. That is, the focus mask patterns 120 may be exposed at the same time as the circuit mask patterns 130 are exposed on the wafer W, thereby forming an effective focus check pattern and a circuit pattern at the same time.

As described above, according to the focus inspection mask and the focus inspection method of the exposure apparatus according to the present invention, it is possible to accurately adjust the focus of the exposure apparatus by forming a focus inspection pattern on the wafer. In addition, since the circuit pattern is formed and the focus check pattern can be formed at the same time, no additional time or financial loss is generated, and even when the focus check mask is formed, a phase inversion film is not required, so that the focus check mask can be easily manufactured. .

As described above, although described with reference to the preferred embodiments of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the present invention described in the claims below You will understand that it can be changed.

Claims (5)

A mask substrate; And And a mask pattern formed on the mask substrate to have different depths and projected onto the semiconductor substrate at different focal lengths. The focus inspection mask of claim 1, wherein the upper surfaces of the mask patterns have the same height, and the upper surface of the mask substrate is partially etched such that the mask patterns have different depths. Preparing a focus inspection mask having mask patterns formed at different depths; Loading the focus audit mask into an exposure apparatus of a semiconductor substrate; Irradiating the focus inspection mask with light to project the mask patterns onto the semiconductor substrate at different focal lengths; Developing the semiconductor substrate; And Inspecting the sizes of the patterns formed on the semiconductor substrate to select one pattern that meets a predetermined criterion, and adjusting the focus of the exposure apparatus based on a focal length corresponding to the selected one pattern. Focus inspection method of the exposure apparatus. The method of claim 3, wherein the preparing of the focus inspection mask comprises forming upper surfaces of the mask patterns on the mask substrate to have the same height, and partially etching the mask substrate so that the mask patterns have different depths. The focus inspection method of the exposure apparatus characterized by the above-mentioned. The method of claim 3, wherein the projecting of the projection pattern comprises projecting the mask patterns onto a scribe lane on the semiconductor substrate.

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