KR20060065452A - Reed-solomon decoder and circuits of the modified euclid's algorithm - Google Patents

Abstract

The present invention relates to a low-power by reducing the size of the calculation circuit and simplifying the circuit configuration of the Euclidean computational cell, particularly in a Reed-Solomon decoder for digital multimedia broadcasting (DMB). The present invention provides an efficient Reed-Solomon decoding device and a modified Euclidean algorithm calculation circuit.

The modified Euclidean algorithm according to the present invention uses the order of R (x) and Q (x) as variables so that the calculation is performed according to the condition without directly calculating from the polynomial, thereby stopping the modified Euclidean algorithm. Instead of disappearing the condition, loop 2 * t times to make control easier.

Digital multimedia broadcasting (DMB), Reed-Solomon decoder, syndrome calculation circuit, Euclidean algorithm calculation cell, error location and error value

Description

Reed-Solomon decoder and circuits of the modified Euclid's algorithm

1 is a block diagram showing a general Reed-Solomon (RS) decoding apparatus.

2 is a diagram illustrating a syndrome calculation circuit structure of a syndrome polynomial calculation unit provided in a general Reed-Solomon decoding device.

3 is a diagram illustrating an arithmetic circuit structure of a chain search unit and a pony algorithm calculation unit included in a general Reed-Solmomon decoding device.

4 is a flowchart illustrating a method of calculating a modified Euclidean algorithm calculation unit applied to a Reed-Solomon decoding apparatus according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a hardware configuration of a modified Euclidean algorithm calculation unit applied to a Reed-Solomon decoding apparatus according to an embodiment of the present invention. FIG.

6 is a diagram illustrating a change in a register value according to the polynomial exchange of FIG. 4.

FIG. 7 is a view illustrating a change in register values according to R (x), U (x), and R _deg operations of FIG. 4. FIG.

FIG. 8 is a view illustrating a change in register values according to Q (x), V (x), and Q _deg operations of FIG. 4. FIG.

FIG. 9 is a diagram illustrating an operation circuit structure of a modified Euclidean algorithm calculation unit applied to a Reed-Solomon decoding apparatus according to an embodiment of the present invention. FIG.

FIG. 10 is a diagram illustrating an arithmetic cell structure of a modified Euclidean algorithm calculation unit applied to a Reed-Solomon decoding apparatus according to an embodiment of the present invention. FIG.

<Description of Symbols for Main Parts of Drawings>

      100: syndrome polynomial calculator 102: modified Euclidean algorithm calculator

      104: chain search unit 106: Pony algorithm operation unit

      108: first-in, first-out 110

      500: register / memory section 502: processing section

      504 control unit 506 register exchange unit

      508: shift calculation unit 510: finite field multiplication unit

      512: finite field addition unit 514: subtraction operation unit

      900: multiplexer 902: register

      904: Modified Euclidean Algorithm Cell

      906: controller

The present invention relates to a Reed-Solomon decoding device for digital multimedia broadcasting (DMB) and a modified Euclidean algorithm calculation circuit.

Currently, digital communication systems use Forward Error Correction (FEC) as a means for correcting signal errors caused by noise on channels. Among these FEC techniques, Reed-Solomon (RS) codes are widely used and used as an effective correction method for linking errors.

Reed-Solomon codes are used in many applications because of their high code rate (R) and excellent correction capability. Typical CD players, compact audio tape recorders, and digital video cassette recorders Digital VCR), Digital Video Broadcasting-Terrestrial (DVB-T), Digital Multimedia Broadcasting (DMB).

Reed-Solomon codes are coded and decoded in a special number system called a Galois Field. In arithmetic operations in finite bodies, the calculation method is different from that in the general number system, and efficient circuit structure is continuously studied.

The Reed-Solomon code is represented by (N, K), where N means the number of code blocks output from the encoder, and K means the number of message blocks input to the encoder. N-K means an additionally inserted block, which determines the number of blocks t that the Reed-Solomon code can correct. In general, the number of blocks t is calculated as (N-K) / 2.

Reed-Solomon encoders can be easily circuited using a divider, but decoders require relatively complex algorithms and computational circuits. Therefore, a number of algorithms that can simplify and facilitate decoding have been studied. A representative method is a method using a mesh feedback feedback register (FSR) of Bellekamp's iterative algorithm. , Euclid algorithm and modified Euclid algorithm. Among them, a modified Euclidean algorithm that does not require polynomial division is frequently used.

The main function of the Reed-Solomon decoder is to correct the error of the input signal and to correct the error symbol within the given correction capability range. In addition, after correcting and checking the error again, the next block is notified of the error, and the frequency of error occurrence or the number of error bits can be known to calculate the bit error rate (BER).

1 is a block diagram showing a general Reed-Solomon (RS) decoding apparatus. Referring to FIG. 1, the Reed-Solomon decoding apparatus includes a syndrome polynomial calculation unit 100, a modified Euclidean algorithm calculation unit 102, a chain search calculation unit 104, a pony algorithm operation unit 106, and a first-in first-out unit (FIFO, First). In First Out) 108 and the controller 110.

When the data input signal and the frame synchronization signal are received, the syndrome polynomial calculating unit 100 performs syndrome calculation. The syndrome calculation is performed to determine the presence or absence of an error of a Reed-Solomon code and to calculate an error location polynomial and an error evaluation polynomial. It is used as a clue. This is because the value of the syndrome itself consists of the error location and error value.

Next, the modified Euclidean algorithm calculating unit 102 calculates an error location polynomial and an error evaluation polynomial using the syndrome polynomial value. This is the most complex part of the Reed-Solomon decoder, and it requires a lot of computation.

When the Euclidean algorithm operation is completed, the chain search operation unit 104 calculates an error position and an error evaluation value using the error position and the evaluation polynomial, and the pony algorithm operation unit 106 calculates an error value to start error correction. . The corrected Reed-Solomon frame is used to perform the syndrome operation again and check whether the error has been corrected successfully. If there is an error, it indicates that decoding has failed.

On the other hand, the first-in, first-out unit 108 is a kind of buffer that serves to wait until the first data processing, the control unit 110 is a syndrome polynomial operation unit 100, the modified Euclidean algorithm operation unit 102, the chain search unit ( 104) and the Pony algorithm calculation unit 108 to control the overall Reed-Solomon decoder.

FIG. 2 is a diagram illustrating a syndrome calculation circuit structure of a syndrome polynomial calculation unit included in a general Reed-Solomon decoding device, and FIG. 3 illustrates a calculation circuit structure of a chain search unit and a pony algorithm calculation unit included in a general Reed-Solomon decoding device. The figure shown.

Referring to FIG. 2, the syndrome polynomial calculating unit 100 includes a plurality of flip-flops FF, a plurality of multiplexers MUX, a plurality of adders, and a multiplier. When the Reed-Solomon frame synchronization signal is ON in the syndrome polynomial calculating unit 100, the register is initialized and the data input signal is input to the register. That is, the register is initialized while the Reed-Solomon frame sync signal is '1' and the data input signal is input to the register.

From this point on, loop operation is performed until all Reed-Solomon frame data is input. The data stored in the register is stored in the register after each constant multiplication operation. The operation is completed, and 16 syndrome data (S ₀ to S ₁₅ ) are output at once in parallel. The output of 16 coefficients is defined by the syndrome polynomial S (x).

On the other hand, the modified Euclidean algorithm determines the initial value as shown in Equation 1 in order to obtain the error position and error magnitude polynomial by eliminating the highest order term and repeatedly decreasing the order.

R _O (x) = x ^2t , Q _O (x) = S (x)

U _O (x) = 0, V _O (x) = 1

Equation 2 is a relation between polynomials R _{i + 1} (x), Q _{i + 1} (x), U _{i + 1} (x) and V _{i + 1} (x) when i + 1 iteration operation is performed, respectively. . a _i and b _i represent the highest order coefficients of R _i (x) and Q _i (x), respectively, and l _i and σ _i are determined according to the order of the polynomials R (x) and Q (x). d (R _i ) and d (Q _i ) represent the degrees of the polynomials R _i (x) and Q _i (x), respectively.

R_i+1(x)=[σ_ib_iR_i(x)+a_iQ_i(x)]-[σ_ib_iQ_i(x)+b_iR_i(x)]

R _{i + 1} (x) = [σ _i b _i R _i (x) + a _i Q _i (x)]-[σ _i b _i Q _i (x) + b _i R _i (x)]

R_i(x)Q _{i + 1} (x) = σ _i Q _i (x) +

R _i (x)

a_iV_i(x)]-

[σ_ia_iV_i(x)+

b_iU_i(x)]U _{i + 1} (x) = [σ _i b _i U _i (x) +

a _i V _i (x)]-

(σ _i a _i V _i (x) +

b _i U _i (x)]

U_i(x)V _{i + 1} (x) = σ _i V _i (x) +

U _i (x)

l _i = d (R _i ) -d (Q _i )

if l _i ≥0 then σ _i = 1

if l _i 〈0 then σ _i = 0

When d (R _i ) ≦ d (U _i ), the iterative operation is stopped, and R _i (x) and U _i (x) become the error magnitude polynomial and the error position polynomial, respectively. That is, the modified Euclidean algorithm operation unit 102 is for calculating the polynomials of Equations 1 to 3 above.

Referring to FIG. 3, there are usually two chain search units 104. The first chain search unit 300 receives an error position polynomial coefficient as an input, and an error position value near the error position value and the differentiated error position polynomial. The second chain search unit 302 is a circuit that receives an error evaluation polynomial coefficient as an input and calculates an error evaluation value.

The error position value calculated by the first chain search unit 300 is input to an error correction block 304 in the pony algorithm calculation unit 106, and the differential error position value is an inverse value obtained through the inverse calculation circuit unit 306. And an error value calculated by multiplying the error evaluation value calculated by the second chain search unit 302 is input to the error correction block 304.

The error correction block 304 performs error correction using the calculated error position and the error value, and the received data and the exclusive OAL delayed by the first-in-first-out unit 108 at the corresponding error position. Operation is performed.

The modified Euclidean algorithm calculation circuit provided in the general Reed-Solomon decoding device has a problem in that the calculation circuit becomes large because a plurality of Euclidean calculation cells are used for algorithm calculation.

In addition, since the circuit configuration of the Euclidean operation cell is complicated, it is not easy to control and a lot of power is consumed.

An object of the present invention is to design a Reed-Solomon decoder using a single Euclidean algorithm calculation cell, and to reduce the size of the calculation circuit and simplify the circuit configuration of the Euclidean calculation cell, the Reed-Solomon decoding device designed for low power operation And a modified Euclidean algorithm computation circuit.

A modified Euclidean algorithm computation circuit is provided in accordance with an aspect of the present invention. The circuit is a Euclidean algorithm calculation circuit for obtaining an error evaluation polynomial (ω (x)) and an error position polynomial (σ (x)) using a syndrome polynomial S (x), wherein the polynomial R _i (x) , Q _i (x), U _i (x) and V _i (x), the coefficient of (here, 0≤i≤2t, t is error correctable block numbers) as four registers for storing, respectively, R ₀ ( four registers each initialized with x) = x ^2t , Q ₀ (x) = S (x), U ₀ (x) = 0 and V ₀ (x) = 1; The polynomial a degree (Q_deg _i) of R _i (x) order (R_deg _i) and polynomial Q _i (x) of a second memory unit for storing, respectively, R_deg ₀ = 2 * t and Q_deg ₀ = 2 * t Memory units each initialized to -1; Two control signals are generated by performing a comparison operation between the orders R_deg _i and Q_deg _i stored in the two memory units and a value of t and the orders, and according to the control signals, R _{i + 1} (x), the coefficients of Q _{i + 1} (x), U _{i + 1} (x) and V _{i + 1} (x) and the order of the R _{i + 1} (x) and Q _{i + 1} (x) (R_deg a Euclidean arithmetic cell for repeating the operation of calculating _{i + 1} and Q_deg _{i + 1} ) and storing the result in the corresponding register and memory unit, respectively 2 * t times; and a control unit for outputting the polynomial R (x) as an error evaluation polynomial (ω (x)) after repeating t times and outputting the polynomial U (x) as an error position polynomial (σ (x)). . The Euclidean arithmetic cell includes an order calculating unit for calculating the orders R_deg _{i + 1} and Q_deg _{i + 1 of} the R _{i + 1} (x) and Q _{i + 1} (x), and a polynomial R _{i + 1} (x ), Q _{i + 1} (x), U _{i + 1} (x) and V _{i + 1} (x), the coefficient calculating unit for calculating the coefficients of the independent. The degree calculating section, a first a first control signal if the determining if less than the value of the order value (Q_deg _i) of order value (R_deg _i) and Q _i (x) of the R _i (x) t, and less First control signal setting means for setting, when the first control signal value is 0 and R_deg _i is greater than or equal to Q_deg _i , and when the first control signal value is 1 and R_deg _i is smaller than Q_deg _i Second control for setting the second control signal to one; When the signal setting means, and the value and the second control signal is 1 R_deg _i and Q_deg _i a b represents the highest order term coefficient of the means and the first control signal value is 0, and Q _i (x) for exchanging _i If non-zero, R_deg _{i + 1} = R_deg _i - to set to 1 when the means for setting to 1 and a value of the first control signal is 0, and b _i is 0, Q_deg _{i + 1} = Q_deg _i It comprises a means for. The coefficient calculating unit, means for exchanging R _i (x) and Q _i (x) stored in the register when the second control signal value is 1 and exchanging U _i (x) and V _i (x). And a _i, b _i , R _i (x), Q _i (x), U _i representing the highest order coefficient of R _i (x) when the first control signal value is zero and b _i is not zero. first computing means for calculating R _{i + 1} (x) and U _{i + 1} (x) by performing finite field multiplication, finite field addition, and shift operations on (x), V _i (x), and 1 Q _{i + 1} (x) and V _{i + 1} (x) are calculated by performing shift operations on Q _i (x) and V _i (x) when the control signal value is 0 and b _i is 0. And second calculating means. The first control signal is a stop signal, and the second control signal is σ _i .

And a polynomial synchronizing signal register for storing a polynomial synchronizing signal for indicating a position of the highest order term of the polynomials, wherein the register is initialized to a "000 ... 01" bit string.

Each of the four registers for storing the coefficients of the polynomials R _i (x), Q _i (x), U _i (x) and V _i (x) respectively stores a total of 2t + 1 coefficients, and each coefficient Is characterized in that it consists of m bits representing the number of symbol bits in the fin.

According to another feature of the invention, a Reed-Solomon decoding device is provided. The apparatus comprises an error evaluation polynomial (ω (x)) and an error position polynomial (σ () a Euclidean algorithm arithmetic circuit according to any one of claims 1 to 7 for obtaining x)); A chain search circuit for calculating an error position and an error evaluation value using the error evaluation polynomial (ω (x)) and error location polynomial (σ (x)) calculated by the Euclidean algorithm calculation circuit; And a pony algorithm calculation circuit configured to perform error correction by calculating an error value using the error position and the error evaluation value calculated by the chain search circuit.

On the basis of the present invention will be described in detail a preferred embodiment of the present invention with reference to the accompanying drawings.

4 is a flowchart illustrating an operation method of a modified Euclidean algorithm calculation unit applied to a Reed-Solomon decoding apparatus according to an embodiment of the present invention. Referring to FIG. 4, first, the operation of the modified Euclidean algorithm according to the present invention is R (x) = x ^2t , Q (x) = S (x), U (x) = 0, V (x) = 1 and starting with the same initial value, and defines a Q _deg represents the order of the value R (x) R _deg and Q (x) represents the value of the order here. Each initial value is set to 2 * t and 2 * t-1 (S400).

Where t is the number of blocks that the Reed-Solomon code can correct, and is generally calculated as (N-K) / 2. N means the number of code blocks output from the encoder, and K means the number of message blocks input to the encoder. That is, N-K means additionally inserted blocks. For example, if N = 15 and K = 9, the number of blocks that the Reed-Solomon code can correct is 3. In addition, i is a variable that controls the total number of loop operations and goes up by 1 each time an operation is performed once.

Determines Solomon code to greater than or equal to the block number t, which can correct - after execution of the step (S400), R (x) the order values is Q _deg indicating the order values of R _deg and Q (x) leads indicating the (S402).

A result of the determination, R (x) the order values is Q _deg indicating the order values of R _deg and Q (x) leads indicating the-Solomon code can correct greater than or equal to the block number t, which, Q _deg a R _deg the more greater judgment (S404), Q _deg is greater than R _deg, perform polynomial exchange and determine if (S406) Q (x) up to order term coefficient, b is 0, and (S408), Q _deg is not greater than R _deg If not, it is determined whether b, which is the highest order term coefficient of Q (x), is zero without the polynomial exchange process (S408).

Wherein the polynomial exchange includes the exchange of R (x) and Q (x) polynomials, the exchange of U (x) and V (x) polynomials, and the exchange of R _deg and Q _deg .

As a result of the determination in step S408, if b, which is the highest order coefficient of Q (x), is 0, Q (x) = xQ (x), V (x) = xV (x), and Q _deg = Q _deg −1 (S410), which is a sequential block constituting a buffer corresponding to each of R (x), Q (x), U (x), and V (x), and R (x) and U (x) change. Without shifting only Q (x) and V (x) by one block and subtracting 1 from the Q _deg value.

As a result of the determination, if b, which is the highest order coefficient of Q (x), is not 0, R (x) = x (b * R (x) + a * Q (x)), U (x) = x (b * U (x) + a * V (x)), R _deg = R _deg -1 operation (S412), which is applied to each of R (x), Q (x), U (x), and V (x) A sequential block constituting the corresponding buffer shifts only one block R (x) and U (x) by one block without changing Q (x) and V (x), and subtracts one from R _deg. Indicates that an operation is performed. Here, the '*' and '+' operations are multiplication and addition operations in the finite field, not the ordinary multiplication and addition operations.

On the other hand, if the Q _deg indicating the order values of R _deg and Q (x) represents the order of the value of R (x) in step (S402) the lead-case having a value less than the number of blocks that have Solomon code can correct t is , It is determined whether R _deg is smaller than Q _deg (S414).

As a result of the determination, if R _deg is not less than Q _deg , the exchange of R (x) and Q (x) polynomials, the exchange of U (x) and V (x) polynomials, and the same as the operation performed in step S406 and A polynomial exchange including an exchange of R _deg and Q _deg is performed (S416). If R _deg is smaller than Q _deg , the polynomial exchange process is omitted.

When one of the steps (S410) to (S416) is completed according to the condition of the calculation, one operation is completed. Therefore, by adding 1 to i (S418), i is expressed by i = 2 * t. It is determined whether it is satisfied (S420). As a result of the determination, if the i = 2 * t expression is not satisfied, the operation is performed again from step S402 until the expression is satisfied, and if the expression is satisfied, the operation according to the present invention is terminated.

In other words, the modified Euclidean algorithm according to the present invention sets a variable i to repeat 2 * t times in order to control the total number of loop operations, and stops the operation when i becomes 2 * t. Complete the algorithm. When all operations are complete, the R (x) polynomial becomes the error evaluation polynomial V (x) and the U (x) polynomial becomes the error location polynomial S (x).

5 is a block diagram showing a hardware configuration of a modified Euclidean algorithm calculation unit applied to the Reed-Solomon decoding apparatus according to the present invention. Referring to FIG. 5, the hardware configuration may be broadly classified into a register / memory unit 500, a processor 502, and a controller 504. The register / memory unit 500 stores the R (x), Q (x), U (x), and V (x) polynomials, and the order of R _deg and Q (x), which are the order values of R (x). Store the value Q _deg .

The registers storing the polynomials of R (x), Q (x), U (x), and V (x) include R ₀ to R _2t , A total of 2t + 1 coefficients are stored from Q ₀ to Q _2t , U ₀ to U _2t , and V ₀ to V _2t , and each coefficient consists of m bits. Where m is the number of symbol bits in the finite field.

The processor 502 includes: a register exchanger 506 for exchanging registers for storing polynomials and order values, a shift operator 508 for raising the order of polynomials, and a finite field multiplier 510 for multiplication within a finite body. ), A finite field adder 512 for performing an addition in the finite field, and a subtraction operator 514 for decreasing the order value by one.

The processor 502 reads a polynomial and an order value from the register / memory unit 500, processes a corresponding operation, and stores the polynomial.

The controller 504 determines a condition for processing each operation using R _deg and Q _deg and controls the overall algorithm flow. The controller 504 is configured to perform a conditional operation using R _deg , Q _deg , t, b, and thus constitute a state machine for controlling the operation flow.

6 to 8 are diagrams illustrating a change of a register value in performing a calculation method of a modified Euclidean algorithm calculation unit applied to the Reed-Solomon decoding apparatus according to the present invention of FIG.

6 is a diagram illustrating a change in a register value according to the polynomial exchange of FIG. Referring to FIG. 6, R (x) and Q (x) polynomial exchanges, U (x) and V (x) polynomial exchanges, and R _deg and Q as performing step S406 or step S416 of FIG. 4. _You can see that the register value changes during the _deg exchange operation.

That is, the coefficient values of R (x) R ₀ to R _2t move to a position corresponding to Q (x), and the coefficient values of Q (x) Q ₀ to Q _{2t correspond} to R (x). Go to location. Further, a position from the counter value, which are U ₀ of U (x) U _2t are moved to a position that corresponds to the V (x), and, from coefficient values, which are V ₀ of V (x) V _2t corresponding to U (x) Go to. In addition, R _deg moves to a position of the Q _{deg, deg} Q is moved to the position of R _deg.

FIG. 7 is a diagram illustrating a change in register values according to R (x), U (x), and R _deg operations of FIG. 4. Referring to FIG. 7, R (x) = x (b * R (x) + a * Q (x)), U (x) = x (b * U (x) in step S412 shown in FIG. 4. It can be seen that the register value changes as the operation of (+ a * V (x)), R _deg = R _deg -1.

That is, in the relation between R (x) and Q (x), the finite field multiplication and addition are performed using a, which is the highest coefficient of R (x), and b, which is the highest coefficient of Q (x), and then the order is By a shift operation of 1, the R (x) registers stored from R ₀ to R _2t are raised by 1, so that the constant term position is filled with '0' and the remainders are x (b * R (x). After calculating according to the equation (+) * a * Q (x)), the new values R ₀ to R _2t-1 are filled.

Similarly, in the relation between U (x) and V (x), the finite field multiplication and addition are performed using a, which is the highest order coefficient of U (x), and b, which is the highest order coefficient of V (x). By a shift operation of 1, the U (x) registers stored from U ₀ to U _2t are raised by order 1, so that the constant term position is filled with '0' and the coefficients are U (x) = x ( After calculation according to the formula b * U (x) + a * V (x)), new values U ₀ to U _2t-1 are filled.

In addition, Q (x) and V (x) remain unchanged, the R _deg value is decreased by '1' so that the R _deg −1 value is stored, and the Q _deg is unchanged.

FIG. 8 is a diagram illustrating a change in a register value according to the Q (x), V (x), and Q _deg operations of FIG. 4. Referring to FIG. 8, a register value is obtained by performing Q (x) = xQ (x), V (x) = xV (x) and Q _deg = Q _deg −1 operations in step S410 of FIG. 4. It can be seen that this is changed.

That is, step S410 illustrated in FIG. 4 is a step of performing a shift operation of Q (x) and V (x) and a decrement operation of Q _deg . The Q (x) polynomial coefficients Q ₀ to Q _2t The values shift by 1, and the values from V ₀ to V _2t , the V (x) polynomial coefficients, also shift by 1. In addition, R (x) and U (x) are unchanged, Q _deg is decreased by 1, Q _deg-1 value is stored, and R _deg is unchanged.

FIG. 9 is a diagram illustrating an arithmetic circuit structure of a modified Euclidean algorithm calculation unit applied to a Reed-Solomon decoding device according to an embodiment of the present invention. 9 shows a modified Euclidean algorithm calculation circuit that calculates repeatedly using one Euclidean cell as an example.

The signal received from the syndrome polynomial calculation unit of the Reed-Solomon decoding device receives the initial value or the previous operation value from the modified Euclidean calculator and outputs the order signals of R (x) and Q (x). Two multiplexers 900, four registers 902 and a polynomial that receive the initial or previous operation value and output the R (x), Q (x), U (x), and V (x) polynomial coefficients. One register 902 for outputting a synchronization signal, the output values of the multiplexer 900 and the register 902 are input to perform a modified Euclidean algorithm operation, and output the performed operation value i = 2 * t One or more operation cells 904 input to the multiplexer 900 and the register 902 and the operation cells are connected to control the system until the expression is satisfied, and the valid region indication signal of the error location and error location evaluation polynomial is received. 1st output And a group (906).

Referring to the modified Euclidean operator, the syndrome coefficients calculated in the syndrome polynomial are input to a register for initializing the Q (x) polynomial, and the R (x) polynomial is x ^2t , and the U (x) polynomial is' 0 ', the V (x) polynomial is initialized to' 1 '.

Also, the two order signals are the order signals of the R (x) and Q (x) polynomials, and are initialized to 2 * t and 2 * t-1, respectively, and the polynomial synchronization signal is initialized to the '00 ... 01 'bit string. This ensures that the position of bit '1' always indicates the highest order term of the polynomial.

The initialized Euclidean algorithm operation cell 902 initializes the Euclidean cell loop operation 2 * t times until i = 2 * t is satisfied, and when the loop operation is completed, the controller 906 generates an algorithm end signal. To stop the register 902 so that no further shift operation is performed. The values in the R (x) polynomial register are then output as the error evaluation polynomial w (x), and the values in the U (x) polynomial register are output as the error location polynomial s (x).

FIG. 10 is a diagram illustrating an arithmetic cell structure of a modified Euclidean algorithm calculation unit applied to a Reed-Solomon decoding device according to an embodiment of the present invention. Referring to FIG. 10, the arithmetic cell calculates R _deg and Q _deg, which are the highest orders of the R (x) and Q (x) polynomials, and generates a control signal according to the condition of each variable to determine whether R _deg decreases by -1. It is divided into a first part 1000 that determines whether Q _deg decreases by -1 and a second part 1002 that calculates R (x), Q (x), U (x), and V (x) polynomials.

The first part 1000 is composed of two multiplexers and five flip-flops, and the second part 1002 is comprised of 12 multiplexers (MUX), 14 flip-flops, 4 finite intramultipliers, 2 finite It consists of an adder in the body and includes a polynomial synchronous input / output unit composed of three flips.

The major components are explained by exchanging R (x) and Q (x), U (x) and V (x) through the multiplexer, and the highest order coefficients of R (x) and Q (x). Where a and b are stored in registers to perform finite field multiplication and finite addition operations, where the highest order term of Q (x) is '0', that is, when b is '0' and stop It is divided into MUX part according to signal.

There is also a polynomial synchronization signal indicating the position of the highest order term. The polynomial synchronization signal is used to indicate the order position of coefficients because the coefficients of each polynomial are sequentially input to the operation cell in a serial manner.

The Euclidean arithmetic cell 904 designed in the present invention is a serial method of inputting coefficients of a polynomial in series, may be used only as a single cell, or may be used by connecting several cells. The greater the number of cells used, the faster the throughput. How many are implemented depends on Reed-Solomon specifications and Euclid's throughput.

The present invention has been described above with reference to the preferred embodiments, which are merely examples and are not intended to limit the present invention, and those skilled in the art to which the present invention pertains do not depart from the essential characteristics of the present invention. It will be appreciated that various modifications and applications are not possible that are not illustrated above.

For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

In designing the Reed-Solomon decoding device, a single Euclidean algorithm calculation cell can be used to reduce the size of the calculation circuit and simplify the circuit configuration of the Euclidean calculation cell, thereby enabling an efficient structure for low power operation.

Claims (8)

In the Euclidean algorithm arithmetic circuit for obtaining an error evaluation polynomial (ω (x)) and an error position polynomial (σ (x)) using a syndrome polynomial (S (x)), Four coefficients for storing the coefficients of the polynomials R _i (x), Q _i (x), U _i (x), and V _i (x), where 0 ≦ _i ≦ 2t, and t are error-correctable blocks Four registers, each initialized with R ₀ (x) = x ^2t , Q ₀ (x) = S (x), U ₀ (x) = 0, and V ₀ (x) = 1; The polynomial a degree (Q_deg _i) of R _i (x) order (R_deg _i) and polynomial Q _i (x) of a second memory unit for storing, respectively, R_deg ₀ = 2 * t and Q_deg ₀ = 2 * t Memory units initialized to -1 and Two control signals are generated by performing a comparison operation between the orders R_deg _i and Q_deg _i stored in the two memory units and a value of t and the orders, and according to the control signals, R _{i + 1} (x), the coefficients of Q _{i + 1} (x), U _{i + 1} (x) and V _{i + 1} (x) and the order of the R _{i + 1} (x) and Q _{i + 1} (x) (R_deg the Euclidean arithmetic cell for repeatedly performing 2 * t times the operation of calculating _{i + 1} and Q_deg _{i + 1} ) and storing the result in the corresponding register and memory unit, respectively; After repeating 2 * t times of operation of the Euclidean operation cell, the polynomial R (x) is output as an error evaluation polynomial (ω (x)), and the polynomial U (x) is an error position polynomial (σ (x)). Control to output to Euclidean algorithm operation circuit comprising a. The method of claim 1, wherein the Euclidean operation cell, Wherein R _{i + 1} (x) and the degree calculating section for calculating the degree (R_deg _{i + 1} and Q_deg _{i + 1)} of Q _{i + 1} (x), the polynomial _{R i + 1 (x),} Q i + 1 (x), a Euclidean algorithm arithmetic circuit comprising independently a coefficient calculating section for calculating coefficients of U _{i + 1} (x) and V _{i + 1} (x). The method of claim 2, wherein the order calculation unit, The R-order value of _i (x) (R_deg _i) and Q _i (x) the order values first to set the first control signal if the judgment, and is less if smaller than the value of (Q_deg _i) t 1 of Control signal setting means, When the first control signal value is 0 and R_deg _i is greater than or equal to Q_deg _i , and when the first control signal value is 1 and R_deg _i is smaller than Q_deg _i , a second control signal is set to 1; 2 control Signal setting means, Means for exchanging R_deg _i and Q_deg _i when the second control signal value is 1; Means for setting R_deg _{i + 1} = R_deg _i -1 when the first control signal value is 0 and b _i indicating the highest order coefficient of Q _i (x) is not zero; Means for setting Q_deg _{i + 1} = Q_deg _i -1 when the first control signal value is 0 and b _i is 0 Euclidean algorithm operation circuit comprising a. The method of claim 3, wherein the coefficient calculating unit, Means for exchanging R _i (x) and Q _i (x) stored in the register and exchanging U _i (x) and V _i (x) when the second control signal value is 1; A _i, b _i , R _i (x), Q _i (x), U _i (x) indicating the highest order coefficient of R _i (x) when the first control signal value is zero and b _i is not zero; ), First computing means for calculating R _{i + 1} (x) and U _{i + 1} (x) by performing finite field multiplication, finite field addition and shift operations on V _i (x), In the case where the first control signal value is 0, and b _i is 0, Q _i (x) and V _i (x) the Q _{i + 1} (x) and V _{i + 1} (x) by performing a shift operation on the Second calculating means for calculating Euclidean algorithm operation circuit comprising a. 4. The euclidean algorithm calculating circuit according to claim 3, wherein the first control signal is a stop signal and the second control signal is sigma _i . The method of claim 1, And a polynomial synchronizing signal register for storing a polynomial synchronizing signal for indicating a highest order position of said polynomials, said register being initialized to a "000 ... 01" bit string. The method of claim 1, Each of the four registers for storing the coefficients of the polynomials R _i (x), Q _i (x), U _i (x) and V _i (x) respectively stores a total of 2t + 1 coefficients, and each coefficient Is a Euclidean algorithm arithmetic circuit composed of m bits representing the number of symbol bits in the fin. A syndrome polynomial computation circuit for computing syndrome polynomials from Reed Solomon codewords, Euclid according to any one of claims 1 to 7 for obtaining an error evaluation polynomial (ω (x)) and an error position polynomial (σ (x)) using the syndrome polynomial calculated by the syndrome polynomial calculation unit. Algorithm algorithms, A chain search circuit for calculating an error position and an error evaluation value using the error evaluation polynomial (ω (x)) and error position polynomial (σ (x)) calculated by the Euclidean algorithm calculation circuit; Pony algorithm calculation circuit for performing error correction by calculating the error value using the error position and the error evaluation value calculated by the chain search circuit Reed Solomon decoding device comprising a.

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