KR20060063224A - Register controlled delay locked loop in semiconductor memory device - Google Patents

Abstract

An object of the present invention is to provide a register-controlled delay locked loop that meets high integration and low power.

The register-controlled delay locked loop of the present invention comprises: a clock buffer for receiving an external clock and an external inverted clock and outputting an internal clock; One delay line capable of shifting the phase of the internal clock; And a phase separator configured to separate a phase of the clock output from the delay line and output a rising DL clock and a falling DL clock, wherein the falling DL clock is in an inverse relationship with the rising DL clock. .

Semiconductor memory, delay lock loop, phase separator, area reduction

Description

REGISTER CONTROLLED DELAY LOCKED LOOP IN SEMICONDUCTOR MEMORY DEVICE}             

1 is an overall block diagram of a register controlled DLL according to the prior art;

2 is an overall block diagram of a register controlled delay locked loop in accordance with one embodiment of the present invention;

3 is a circuit diagram of an embodiment of the delay line of FIG. 2;

4 is a circuit diagram of another embodiment of the delay line of FIG. 2; and

FIG. 5 is a circuit diagram of an embodiment of the phase separator of FIG. 2.

Description of the main parts of the drawing

211: clock buffer 212: clock divider

213: Delay Line 214: Delay Model

215: phase comparator 216: shift controller

217: Shift register 218: DLL driver

219: phase separator

The present invention relates to a delay locked loop (DLL) of a semiconductor memory device, and more particularly, to a DLL that can prevent a clock from being stuck. Here, the stuck of the clock means that the clock phase is locked and locked.

The DLL is a clock generator for compensating skew between an external clock and data, or an external clock and an internal clock. The present invention is applicable to any semiconductor device or computer system using the DLL.

In general, a clock is used as a reference for timing operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay (clock skew) caused by an internal circuit occurs, and a DLL is used to compensate for this time delay so that the internal clock has the same phase as the external clock. have. That is, the DLL synchronizes the timing of the data sensed using the external clock through the data output buffer with the timing of the external clock.

The DLL applied to the DDR SDRAM will be described as an example.

1 is a block diagram of a register controlled DLL according to the related art, and includes a first clock buffer 111, a second clock buffer 112, a clock divider 113, and first to third delay lines 114 and 115. 116, shift register 117, shift controller 118, phase comparator 119, first and second DLL drivers 120 and 121, and delay model 122.

The function and operation of each block will be described below.

The first clock buffer 111 receives the external inverted clock / clk as an input to generate a first internal clock fall_clk which is generated in synchronization with the falling edge of the external clock clk.

The second clock buffer 112 generates the second internal clock rise_clk which is generated in synchronization with the rising edge of the external clock clk using the external clock clk as an input.

The clock divider 113 divides the second internal clock rise_clk into 1 / n (n is a positive integer, typically n = 8) to output a delay monitoring clock dly_in and a reference clock ref. .

The first DLL driver 120 drives the output ifclk of the first delay line 114 to generate the DLL clock fclk_dll, and the second DLL driver 121 outputs the output of the second delay line 115 ( Run irclk to generate the DLL clock (rclk_dll).

The delay model 122 is configured such that the clock feedback_dly undergoes the same delay condition as the actual clock path by using the output feedback_dly of the third delay line 116 as an input.

The phase comparator 119 compares a phase of the rising edge of the feedback clock output from the delay model 122 and the rising edge of the reference clock ref.

The shift controller 118 outputs or delays the shift control signals SR and SL for shifting the clock phases of the first to third delay lines in response to the control signal ctrl output from the phase comparator 119. A delay lock signal dll_lockb indicating that locking is performed is output.

The shift register 117 operates the register according to the shift control signals SR and SL output from the shift controller 118 so that the first delay line 114 and the second internal input the first internal clock fall_clk. The delay amount of the second delay line 115, which receives the clock rise_clk, and the third delay line 116, which receives the delay monitoring clock dly_in, is adjusted.

The delay model 122 here includes a dummy clock buffer, a dummy output buffer, and a dummy load, also called a replica circuit. The shift register 117 and the shift controller 118 in the DLL loop are delay control signal generators 123 for controlling the first to third delay lines 114, 115, and 116 in the delay unit 110. do.

However, the prior art DLL illustrated in FIG. 1 includes three delay line units each occupying the largest area among the elements constituting the DLL. In addition, since two clock buffers are used and two drivers are used, they take up a lot of area and consume a lot of power, which is becoming a burden on semiconductor memory devices that are becoming increasingly integrated and low power.

In order to solve the above problems, an object of the present invention is to provide a register-controlled delay locked loop that meets high integration and low power.

A register-controlled delay locked loop of the present invention for achieving the above object includes a clock buffer for receiving an external clock and an external inverted clock and outputting an internal clock; One delay line capable of shifting the phase of the internal clock; And a phase separator configured to separate a phase of the clock output from the delay line and output a rising DL clock and a falling DL clock, wherein the falling DL clock is in an inverse relationship with the rising DL clock. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

2 is an overall block diagram of a register controlled delay locked loop in accordance with one embodiment of the present invention.

According to an embodiment of the present invention, the register controlled delay locked loop includes one clock buffer 211 for receiving an external clock clk and an external inverted clock clkb and outputting an internal clock iclk.

According to one embodiment of the invention, the register controlled delay locked loop includes one delay line 213 capable of shifting the phase of the internal clock iclk according to the shift signal applied from the shift register 217.

According to an embodiment of the present invention, the register-controlled delay locked loop may separate a phase of a clock output from the delay line 213 to output a rising DL clock rclk_dll and a falling DL clock fclk_dll. The separator 219 is included. That is, the rising DL clock (rclk_dll) and the falling DL clock (fclk_dll) having a 180 degree phase difference can be output from the clock output from the DL driver without using two DL drivers.

3 is a circuit diagram of an embodiment of the delay line of FIG. 2.

The delay line according to an embodiment of the present invention may be configured using a unit delay cell of NAND gate + inverter.

4 is a circuit diagram of another embodiment of the delay line of FIG.

The delay line according to another embodiment of the present invention may be configured using a unit delay cell of NAND gate + NAND gate.

FIG. 5 is a circuit diagram of an embodiment of the phase separator of FIG. 2.

The phase separator according to the exemplary embodiment of the present invention outputs a falling DL clock having the same phase as the clock output from the DL driver and a falling DL clock having an inverted phase. Here, the resistor R1 is equal to the resistance value of one inverter INV to compensate for the delay caused by the inverter.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

According to the present invention, the area occupied by the DLL can be reduced, and power consumption can be reduced. As a result, it is possible to meet the trend of semiconductor memory devices which are becoming increasingly integrated and low power.

Claims (5)

A clock buffer for receiving an external clock and an external inverted clock and outputting an internal clock; One delay line capable of shifting the phase of the internal clock; And A phase separation unit capable of separating a phase of the clock output from the delay line and outputting a rising DL clock and a falling DL clock, wherein the falling DL clock is in inverse relationship with the rising DL clock Register controlled delay locked loop comprising a. The method of claim 1, wherein the phase separation unit, First and second inverters connected in series with a clock output from the delay line as an input; Third to fifth inverters connected in series using a clock output from the delay line as an input; And Resistor for coupling between the first inverter and the second inverter Register controlled delay locked loop comprising a. The method of claim 2, The resistor controlled delay locked loop of which the magnitude of the resistor is equal to the magnitude of the inverter. The method of claim 3, And a unit delay cell in the delay line includes a NAND gate and an inverter connected in series. The method of claim 3, And a unit delay cell in the delay line includes two NAND gates connected in series.

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