KR20060062757A - Mis capacitor fabricating method - Google Patents

Mis capacitor fabricating method Download PDF

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KR20060062757A
KR20060062757A KR1020040101707A KR20040101707A KR20060062757A KR 20060062757 A KR20060062757 A KR 20060062757A KR 1020040101707 A KR1020040101707 A KR 1020040101707A KR 20040101707 A KR20040101707 A KR 20040101707A KR 20060062757 A KR20060062757 A KR 20060062757A
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capacitor
film
lower electrode
nitride film
forming
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KR1020040101707A
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Korean (ko)
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오종혁
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 엠아이에스 캐패시터의 제조 방법에 관한 것으로, 보다 상세하게는 원자층증착(Atomic Layer Deposition; ALD)방식으로 질화막을 균일하게 증착시킴으로써, 하부전극인 실리콘에 발생하는 기생산화막의 생성을 방지함으로써 캐패시터의 충전용량을 향상시키는 기술을 개시한다. 이를 위해, 본 발명의 실시예에 따른 엠아이에스 캐패시터의 제조방법은, (a) 하부전극을 형성하는 공정과, (b) 상기 하부전극을 클리닝하여 자연산화막을 제거하고, 그 상부에 원자층증착(Atomic Layer Deposition; ALD)방식으로 질화막을 균일하게 증착하는 공정과, (c) 상기 질화막의 상부에 유전체막을 형성하고 열처리하는 공정과, (d) 상기 유전체막의 상부에 상부전극을 형성하는 공정을 포함함을 특징으로 한다.The present invention relates to a method of manufacturing an MS capacitor, and more particularly, by depositing a nitride film uniformly by atomic layer deposition (ALD), thereby preventing the formation of a pre-production film generated in silicon, which is a lower electrode. Disclosed is a technique for improving the charging capacity of. To this end, the manufacturing method of the MS capacitor according to the embodiment of the present invention, (a) forming a lower electrode, (b) cleaning the lower electrode to remove the natural oxide film, the atomic layer deposition (top) Uniformly depositing a nitride film by an Atomic Layer Deposition (ALD) method, (c) forming and heat treating a dielectric film on the nitride film, and (d) forming an upper electrode on the dielectric film. It is characterized by.

Description

엠아이에스 캐패시터의 제조 방법{MIS capacitor fabricating method}MIS capacitor fabricating method

도 1a 내지 도 1d는 종래의 엠아이에스 캐패시터의 제조방법을 도시한 공정도.1A to 1D are process diagrams showing a manufacturing method of a conventional MS capacitor.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 엠아이에스 캐패시터의 제조 방법을 도시한 공정도.2a to 2d is a process diagram showing a manufacturing method of an MS capacitor according to an embodiment of the present invention.

본 발명은 엠아이에스 캐패시터의 제조 방법에 관한 것으로, 보다 상세하게는 원자층증착(Atomic Layer Deposition; ALD)방식으로 질화막을 균일하게 증착시킴으로써, 하부전극인 실리콘에 발생하는 기생산화막의 생성을 방지함으로써 캐패시터의 충전용량을 향상시키는 기술이다.The present invention relates to a method of manufacturing an MS capacitor, and more particularly, by depositing a nitride film uniformly by atomic layer deposition (ALD), thereby preventing the formation of a pre-production film generated in silicon, which is a lower electrode. It is a technique to improve the charging capacity.

일반적으로, 캐패시터는 전하를 저장하고, 반도체 소자의 동작에 필요한 전하를 공급하는 부분으로서, 반도체 소자가 고집적화 됨에 따라 단위셀(cell)의 크기는 작아지면서 소자의 동작에 필요한 정전용량(capacitance)은 약간씩 증가하는 것이 일반적인 경향이다.In general, a capacitor stores electric charges and supplies electric charges necessary for the operation of the semiconductor device. As the semiconductor device is highly integrated, the size of the unit cell decreases and the capacitance required for the operation of the device is reduced. A slight increase is a common trend.

특히, 높은 정밀도를 요구하는 씨모스 아이씨 로직 소자(CMOS IC Logic device)에 적용되는 아날로그 캐패시터(Analog Capacitor)는 어드벤스드 아날로그 모스 기술 (Advanced Analog MOS Technology), 특히, A/D 컨버터나 스위칭 캐패시터 필터 분야의 핵심 요소이다. 이러한 아날로그 캐패시터의 구조로는 피아이피(PIP : Poly-Insulator-Poly), 피아이엠(PIM : Poly -Insulator-Metal), 엠아이피(MIP : Metal-Insulator-Poly), 엠아이에스(MIS : Metal Insulator Silicon), 및 엠아이엠(MIM : Metal-Insulator-Metal) 등 다양한 구조들이 이용되어 왔다. In particular, Analog Capacitors applied to CMOS IC Logic devices that require high precision are Advanced Analog MOS Technology, especially A / D converters or switching capacitor filters. It is a key element of the field. The structure of the analog capacitor is PIP (Poly-Insulator-Poly), PIM (Poly-Insulator-Metal), MIP (Metal-Insulator-Poly), MIS (Metal Insulator Silicon) ), And MIM (Metal-Insulator-Metal), such as various structures have been used.

특히, MPS(Metal Poly Silicon)을 이용한 엠아이에스(MIS : Metal Insulator Silicon) 캐패시터는 탄탈륨 옥시나이트라이드(TaON) 및 탄탈륨 옥사이드(Ta2O5) 등의 고유전상수를 갖는 물질을 이용하여 유전체막을 형성함으로써 충분한 충전용량과 누설 전류 특성을 확보할 수 있다.In particular, a metal insulator silicon (MIS) capacitor using MPS (Metal Poly Silicon) forms a dielectric film using materials having high dielectric constants such as tantalum oxynitride (TaON) and tantalum oxide (Ta 2 O 5 ). Sufficient charging capacity and leakage current characteristics can be ensured.

도 1a 내지 도 1c는 종래의 엠아이에스 캐패시터의 제조방법을 도시한 공정도이다. 도 1a 내지 도 1c를 참조하여 종래의 엠아이에스 캐패시터의 제조방법을 설명하기로 한다.1A to 1C are process diagrams illustrating a method of manufacturing a conventional MS capacitor. A method of manufacturing a conventional MS capacitor will be described with reference to FIGS. 1A to 1C.

도 1a에 도시한 바와 같이, 폴리실리콘(poly silicon)을 이용한 하부전극(10)을 형성한다. 이때, 하부전극(10) 면적을 증가시켜 캐패시터의 충전용량을 증가시키기 위해 MPS(Metastable Poly Silicon; SAES(Surface Area Enhanced Silicon), HSG(Hemispherical Grained Silicon) 공정을 추가하기도 한다. 그러나, 이웃한 셀과의 쇼트나 애스펙트비(aspect ratio)가 큰 경우에는 증착된 폴리실리콘을 바로 하부전극(10)으로 사용할 수 있다. As shown in FIG. 1A, the lower electrode 10 using polysilicon is formed. In this case, in order to increase the charge capacity of the capacitor by increasing the area of the lower electrode 10, a metastable poly silicon (MPS) surface area enhanced silicon (SAES) process and a hemispherical grained silicon (HSG) process may be added. In the case of short and aspect ratio, the deposited polysilicon may be directly used as the lower electrode 10.                         

이어서, 도 1b에 도시한 바와 같이, 도 1a의 하부전극(10)의 자연산화막을 제거하기 위해 소정의 클리닝 공정을 진행한 후, 그 상부에 저압화학기상증착(low pressure chemical vapor deposition; LPCVD) 및 플라즈마(plasma) 방식 등을 통해 질화막(nitride)(11)을 증착한다. 이때, 저압화학기상증착(low pressure chemical vapor deposition; LPCVD)을 이용하여 질화막(11)을 증착하면 애스펙트비(aspect ratio)가 큰 경우 전제 캐패시터 영역에 균일한 질화막(11)을 증착하는 것이 어렵고 플라즈마(plasma) 방식을 통해 질화막(11)을 증착하면 표면이 얇고 불안정하여 다른 층의 산소성분 및 실리콘 성분들이 침투하기가 용이한 문제점이 있다.Subsequently, as shown in FIG. 1B, a predetermined cleaning process is performed to remove the native oxide film of the lower electrode 10 of FIG. 1A, and then low pressure chemical vapor deposition (LPCVD) is disposed thereon. And a nitride film 11 by a plasma method or the like. In this case, when the nitride film 11 is deposited using low pressure chemical vapor deposition (LPCVD), it is difficult to deposit the uniform nitride film 11 in the entire capacitor region when the aspect ratio is large, and the plasma may be difficult. When the nitride film 11 is deposited through a plasma method, the surface is thin and unstable, so that oxygen and silicon components of another layer may easily penetrate.

그 후, 도 1c에 도시한 바와 같이, 질화막(11)의 상부에 탄탈륨 옥시나이트라이드(TaON)나 탄탈륨 옥사이드(Ta2O5) 등의 고유전물질을 이용하여 유전체막(12)을 증착하고, 질화막(12)에 혼합되어 있는 탄소성분(C)을 제거하기 위해 나이트러스옥사이드(N2O) 열처리를 실시한다.After that, as shown in FIG. 1C, the dielectric film 12 is deposited on the nitride film 11 by using a high dielectric material such as tantalum oxynitride (TaON) or tantalum oxide (Ta 2 O 5 ). In order to remove the carbon component (C) mixed in the nitride film 12, nitrous oxide (N 2 O) heat treatment is performed.

이때, 열처리 시에 유전체막(12)의 탄탈륨 옥시나이트라이드(TaON) 및 탄탈륨 옥사이드(Ta2O5) 등의 고유전물질의 산소성분(O)이나 열처리를 위한 나이트러스옥사이드(N2O)의 산소성분(O)들이 질화막(11)에 침투되어 하부전극인 실리콘 표면(10) 상에 산소성분과 실리콘성분이 결합하여 기생산화막(13)을 형성한다. 이러한 기생산화막(13)은 캐패시터의 충전용량을 감소시키는 악요인이 된다.At this time, the oxygen component (O) of the high dielectric material such as tantalum oxynitride (TaON) and tantalum oxide (Ta 2 O 5 ) of the dielectric film 12 during the heat treatment or nitrous oxide (N 2 O) for heat treatment Oxygen components (O) are penetrated into the nitride film 11, the oxygen component and the silicon component are combined on the silicon surface 10, which is the lower electrode, to form the vaporization film 13. This pre-production film 13 is a bad factor to reduce the charge capacity of the capacitor.

이어서, 도 1d에 도시한 바와 같이, 유전체막(12)의 상부에 상부전극(14)을 증착한다. 이때, 상부전극(14)은 TiCl4를 이용한 TiN을 이용하여 바람직하게는 600 ℃ 이하의 온도에서 증착한다. Subsequently, as shown in FIG. 1D, the upper electrode 14 is deposited on the dielectric film 12. At this time, the upper electrode 14 is deposited at a temperature of preferably 600 ° C. or less using TiN using TiCl 4.

상기와 같은 공정을 통해 제조한 종래의 엠아이에스 캐패시터는, 유전체막(12)의 열처리시에 기생 산화막(13)이 발생하여 엠아이에스 캐패시터의 충전용량을 감소시키는 문제점이 있다.The conventional MS capacitor manufactured through the above process has a problem in that the parasitic oxide film 13 is generated during the heat treatment of the dielectric film 12 to reduce the charging capacity of the MS capacitor.

상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, 원자층증착(Atomic Layer Deposition; ALD)방식으로 질화막을 균일하게 증착시켜, 유전체막 열처리시에 발생하는 기생산화막의 생성을 방지함으로써 캐패시터의 충전용량을 향상시키는데 있다. An object of the present invention for solving the above problems is to uniformly deposit a nitride film by Atomic Layer Deposition (ALD) method, thereby preventing the formation of a pre-production film generated during the dielectric film heat treatment to charge the capacitor. To improve the dose.

상기 과제를 달성하기 위한 본 발명의 실시예에 따른 엠아이에스 캐패시터의 제조방법은, (a) 하부전극을 형성하는 공정과, (b) 상기 하부전극을 클리닝하여 자연산화막을 제거하고, 그 상부에 원자층증착(Atomic Layer Deposition; ALD)방식으로 질화막을 균일하게 증착하는 공정과, (c) 상기 질화막의 상부에 유전체막을 형성하고 열처리하는 공정과, (d) 상기 유전체막의 상부에 상부전극을 형성하는 공정을 포함함을 특징으로 한다.In order to achieve the above object, a method of manufacturing an MS capacitor according to an embodiment of the present invention includes: (a) forming a lower electrode, and (b) cleaning the lower electrode to remove a natural oxide film, wherein Uniformly depositing a nitride film by an Atomic Layer Deposition (ALD) method, (c) forming and heat treating a dielectric film on top of the nitride film, and (d) forming an upper electrode on the dielectric film Characterized in that it comprises a process.

이하, 첨부된 도 2a 내지 도 2d를 참조하여 본 발명의 실시예에 따른 엠아이에스 캐패시터의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing an MS capacitor according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2D.

먼저, 도 2a에 도시한 바와 같이, 폴리실리콘을 이용한 하부전극(100)을 형성한다. 이때, 하부전극(100)의 면적을 증가시켜 캐패시터의 충전용량을 증가시키 기 위해 SAES(Surface Area Enhanced Silicon)공정을 추가로 실시하는 것이 바람직하나, 이웃한 셀과의 쇼트나 애스펙트비(aspect ratio)가 큰 경우에는 이 공정을 생략할 수 있다.First, as shown in FIG. 2A, a lower electrode 100 using polysilicon is formed. In this case, the surface area enhanced silicon (SAES) process may be additionally performed in order to increase the area of the lower electrode 100 to increase the charge capacity of the capacitor. However, a short or aspect ratio with neighboring cells may be used. If) is large, this step can be omitted.

이어서, 도 2b에 도시한 바와 같이, 하부전극(100)에 발생하는 자연산화막을 제거하기 위한 클리닝 공정을 수행하고 그 상부에 원자층증착(Atomic Layer Deposition; 이하, ALD)방식을 이용하여 질화막(101)을 균일하게 증착한다.Subsequently, as shown in FIG. 2B, a cleaning process for removing a natural oxide film generated on the lower electrode 100 is performed, and a nitride film (ALD) method is formed thereon. 101) is deposited uniformly.

이때, 클리닝 공정은 HF 희석용액을 이용하거나, NF3 가스를 이용하여 원격 플라즈마(remote plasma)를 이용하여 하부전극(100)인 실리콘 표면상의 자연산화막을 제거한다. 이때, 애스팩스비(Aspect Ratio)가 큰 하부전극(100)의 경우에는 HF 희석용액에 계면활성제를 포함시켜 클리닝하는 것이 바람직하다.At this time, the cleaning process removes the native oxide film on the silicon surface of the lower electrode 100 by using a HF dilution solution or a remote plasma using NF 3 gas. In this case, in the case of the lower electrode 100 having a large aspect ratio, it is preferable to include a surfactant in the HF dilution solution and clean it.

또한, ALD 방식은 250토르(torr) 이하의 압력과 300~ 500℃ 이하의 온도 조건의 SiC14의 공급과, 400토르 이하의 압력과 500~ 600℃ 이하의 온도 조건의 NH3의 공급을 교번적으로 수행하면서 질화막(101)을 5~ 20Å의 두께로 증착한다. In addition, the ALD system alternately supplies SiC14 at a pressure of 250 torr or less and temperature of 300 to 500 ° C., and NH 3 at a pressure of 400 torr and a temperature of 500 to 600 ° C. or less. While performing as described above, the nitride film 101 is deposited to a thickness of 5 to 20 mW.

그 후, 도 2c에 도시한 바와 같이, 질화막(101)의 상부에 유전체막(102)을 증착한다. 유전체막(102)은 탄탈륨 옥시나이트라이드(TaON)나 탄탈륨 옥사이드(Ta2O5) 등의 고유전물질을 이용하여 형성한다.Thereafter, as shown in FIG. 2C, the dielectric film 102 is deposited on the nitride film 101. The dielectric film 102 is formed using a high dielectric material such as tantalum oxynitride (TaON) or tantalum oxide (Ta 2 O 5 ).

이때, 유전체막(102)은 300~ 500℃의 온도 및 0.01~ 100 토르의 압력조건에서 100 ~ 1000W의 파워로 금속유기화학기상증착(metal-organic chemical vapor deposition;MOCVD)방식으로 탄탈륨 옥시나이트라이드(TaON) 또는 탄탈륨 옥사이드 (Ta2O5)를 증착하되, 특히, 탄탈륨 옥시나이트라이드(TaON)는 증착시에 NH3를 플라즈마에 혼입하여 형성시킬 수도 있다.At this time, the dielectric film 102 is tantalum oxynitride by metal-organic chemical vapor deposition (MOCVD) at a power of 100 ~ 1000W at a temperature of 300 ~ 500 ℃ and a pressure of 0.01 ~ 100 Torr (TaON) or tantalum oxide (Ta 2 O 5 ), but in particular, tantalum oxynitride (TaON) may be formed by incorporating NH 3 into the plasma during deposition.

이어서, 탄탈륨 옥사이드(Ta2O5)나 탄탈륨 옥시나이트라이드(TaON) 증착시 금속유기화학기상증착방식을 사용함으로 인해 유전체막(102)에 남아있는 탄소성분(C)을 제거하기 위해, 나이트러스옥사이드(N2O) 열처리를 행한다. 이때, 열처리는 상기 반도체 기판이 챔버내에 로딩시 산소 농도를 조절할 수 있는 장비가 장착된 챔버내에서 N2 또는 NH3 가스 분위기 및 600℃ 이상의 공정 온도에서 진공 상태로 RTP 열처리를 진행하며, N2 퍼지 박스가 장착된 퍼니스(furnace) 내에서 500℃ 이상의 온도에서 진공 열처리를 진행할 수 있다. 특히, 본 발명에서는 퍼니스내에서 500~ 800℃, 100토르 이상의 압력조건에서 2시간 이하로 열처리를 수행하는 것이 바람직하다.Next, in order to remove the carbon component (C) remaining in the dielectric film 102 by using a metal organic chemical vapor deposition method during the deposition of tantalum oxide (Ta 2 O 5 ) or tantalum oxynitride (TaON), Oxide (N 2 O) heat treatment is performed. At this time, the heat treatment is RTP heat treatment in a vacuum state in the N 2 or NH 3 gas atmosphere and a process temperature of 600 ℃ or more in a chamber equipped with equipment for adjusting the oxygen concentration when the semiconductor substrate is loaded into the chamber, N 2 Vacuum heat treatment may be performed at a temperature of 500 ° C. or higher in a furnace equipped with a purge box. In particular, in the present invention, it is preferable to perform heat treatment in a furnace at 500 to 800 ° C. and 100 torr or more for 2 hours or less.

그 후, 도 2d에 도시한 바와 같이, 유전체막(102)의 상부에 상부전극(103)을 증착한다. 이때, 상부전극(103)은 티타늄 나이트라이드(TiN), 탄탈륨 나이트라이드(TaN), 텅스텐(W), 및 루비듐(Ru) 등의 금속물질을 이용하여 형성되나, 본 발명에서는 TiN막 증착을 예로 들고 있으며, TiN막은 바람직하게 600℃ 이하의 온도에서 증착한다.  Thereafter, as shown in FIG. 2D, the upper electrode 103 is deposited on the dielectric film 102. In this case, the upper electrode 103 is formed using a metal material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and rubidium (Ru), but in the present invention, TiN film deposition is used as an example. The TiN film is preferably deposited at a temperature of 600 占 폚 or lower.

이어서, 상부전극(103)위에 산화막 및 컨택형성 및 메탈 공정등 후속 공정을 진행한다.Subsequently, an oxide film, a contact forming process, and a metal process are performed on the upper electrode 103.

이상에서 살펴본 바와 같이, 본 발명은 원자층증착(Atomic Layer Deposition; ALD)방식으로 질화막을 균일하게 증착시켜 하부전극인 폴리실리콘 표면에 기생산화막의 생성을 방지함으로써 캐패시터의 충전용량을 향상시키는 효과가 있다.As described above, the present invention has the effect of improving the charge capacity of the capacitor by uniformly depositing a nitride film by the atomic layer deposition (ALD) method to prevent the production of a pre-production film on the surface of polysilicon, the lower electrode. have.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

(a) 하부전극을 형성하는 공정;(a) forming a lower electrode; (b) 상기 하부전극을 클리닝하여 자연산화막을 제거하고, 그 상부에 원자층증착(Atomic Layer Deposition; ALD)방식으로 질화막을 균일하게 증착하는 공정;(b) cleaning the lower electrode to remove the native oxide film, and depositing a nitride film uniformly thereon by atomic layer deposition (ALD); (c) 상기 질화막의 상부에 유전체막을 형성하고 열처리하는 공정; 및(c) forming a dielectric film on the nitride film and performing heat treatment; And (d) 상기 유전체막의 상부에 상부전극을 형성하는 공정(d) forming an upper electrode on the dielectric film 을 포함하는 것을 특징으로 하는 엠아이에스 캐패시터의 제조방법.Manufacturing method of the MS capacitor comprising a. 제 1항에 있어서, 상기 하부전극은 폴리실리콘을 이용하여 형성함을 특징으로 하는 엠아이에스 캐패시터의 제조방법.The method of claim 1, wherein the lower electrode is formed using polysilicon. 제 2항에 있어서, 상기 (b) 공정은,The method of claim 2, wherein the step (b) HF 희석용액 및 상기 HF 희석용액에 계면활성제를 혼합한 혼합용액 중 어느 하나를 이용하여 상기 하부전극을 클리닝하거나 NF3 가스를 이용한 원격 플라즈마를 이용하여 상기 자연산화막을 제거함을 특징으로 하는 엠아이에스 캐패시터의 제조방법.Cleaning the lower electrode using any one of HF dilution solution and a mixed solution mixed with the HF dilution solution or removing the natural oxide film using a remote plasma using NF 3 gas of the MS capacitor Manufacturing method. 제 1항에 있어서, 상기 (b)공정의 원자층증착 방식은,According to claim 1, wherein the atomic layer deposition method of the step (b), 250토르 이하의 압력과 300~ 450℃ 범위 이하의 온도하에서의 SiC14의 공급과 400토르 이하의 압력과 500~ 600℃ 범위 이하의 온도하에서의 NH3 공급을 교번적으로 하면서 상기 질화막을 증착함을 특징으로 하는 엠아이에스 캐패시터의 제조방법.Depositing the nitride film with alternating supply of SiC14 at a pressure below 250 Torr and a temperature below the range of 300 to 450 ° C. and NH 3 under a pressure below 400 Torr and a temperature below the range of 500 to 600 ° C. Method for producing an MS capacitor. 제 1항에 있어서, 상기 (c) 공정의 열처리는 The method of claim 1, wherein the heat treatment of step (c) 퍼니스내에서 500~800℃ 범위의 온도와 100토르 이상의 압력조건하에서 2시간동안 N2O 열처리를 수행하는 것을 특징으로 하는 엠아이에스 캐패시터의 제조방법.Method for producing an MS capacitor, characterized in that the N 2 O heat treatment for 2 hours at a temperature in the furnace range of 500 ~ 800 ℃ and pressure conditions of 100 torr or more.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180104461A (en) 2017-03-13 2018-09-21 주식회사 에스엔아이 Manufacturing method of MIS capacitor
US11197372B2 (en) 2018-10-25 2021-12-07 Korea Electronics Technology Institute Capacitor having through hole structure and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180104461A (en) 2017-03-13 2018-09-21 주식회사 에스엔아이 Manufacturing method of MIS capacitor
US11197372B2 (en) 2018-10-25 2021-12-07 Korea Electronics Technology Institute Capacitor having through hole structure and manufacturing method therefor

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