KR20060059857A - Modified FIFNFC CMOS device structure - Google Patents

Abstract

A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

Description

Modified FIFNTM COMOS device structure {STRAINED FINFET CMOS DEVICE STRUCTURES}

The present invention relates to dual gate semiconductor device structures and more specifically to FinFET devices.

Dual-gate semiconductor device structures are ideal for next-generation microelectronic devices because of the almost ideal sub-threshold slope, absence of body-effects, immunity to short-channel effects, and very large current driveability. Is a promising candidate. A technically related double gate device structure is the FinFET. FinFETs are particularly attractive because they are relatively simple to manufacture compared to other double gate devices. The channel for the FinFET is a thin rectangular Si island, commonly referred to as fin. The gate surrounds the fin and is gated at both ends of the vertical portion of the Fin structure, providing better gate control than a planar single gate MOSFET.

FinFETs are well known. For example, Hu, filed Oct. 23, 2000, filed July 2, 2002, entitled "FinFET Transistor Structures Having a Double Gate Channel Extending Vertically from a Substrate and Methods of Manufacture" See, eg, US Pat. No. 6,413,802. FinFETs with enhanced mobility, which are incorporated herein by reference, are also known. See, for example, US Patent Application No. 2002/0063292 A1, filed November 29, 2000, published May 30, 2002, entitled " CMOS Fabrication Process Utilizing Special Transistor Orientation " See This prior art method is for the purpose of improving nFET mobility so that only limited improvements can be obtained in CMOS circuits. Thus, there is a need to improve the mobility of the p-FinFET and n-FinFET located on the same wafer.

However, the inventors believe that improvements using strained layers to increase mobility are achievable.

With respect to the present invention, a semiconductor device structure includes a PMOS device and an NMOS device on a substrate, wherein the PMOS device includes a compressive layer that stresses an active region of the PMOS device, The NMOS device includes a tensile layer that compresses the active region of the NMOS device, where the compressive layer comprises a first dielectric material, the tensile layer comprises a second dielectric material and the PMOS and NMOS devices are FinFETs. Device.

The present invention aims at a new modified FinFET device structure for enhanced mobility. The integrated approach introduces a new process flow to induce compressive stress in the longitudinal direction of the n-FinFET and induces tensile stress in the longitudinal direction of the p-FinFET. This stress increases the mobility significantly and enhances device performance. In the invention described here, the longitudinal stress induced in the channel is significantly enhanced than what can be obtained in a standard planar MOSFET, because the stressing film is thin instead of on the SOI layer or bulk substrate. This is because it is applied from both sides of the FinFET.

It is a major goal of the present invention to enhance mobility in a double gate CMOS device structure.

Enhancing mobility in FinFET device structures is a further goal of the present invention.

It is a further object of the present invention to improve the method of fabricating the modified FinFET device structure.

The invention and other objects and features will become more apparent from the following detailed description, which will be described later in conjunction with the following drawings.

1 and 2 schematically show examples of FinFETs perpendicular to Fin and parallel to Fin according to the prior art.

3 schematically illustrates a vertical view of a FinFET semiconductor device structure according to the prior art.

4 through 17 schematically illustrate various examples of intermediate and final FinFET semiconductor device structures in accordance with the present invention.

The present invention aims at novel FinFET semiconductor device structures and methods of fabricating such structures. Preferred final structures according to the invention are shown in FIGS. 16 and 17.

With reference to other figures, in particular, FIGS. 1 to 3, a known FinFET device (FIGS. 1 and 2) and a device structure (FIG. 3) are shown.

Beginning, standard or existing FinFET device fabrication processes proceed through patterning and etching of fins, formation of gate dielectrics and conductors, sidewall spacers (not shown), source / drain doping, and salicidation. do. After salicylation, the gate sidewall spacers are removed to enable the process of inducing deformation in Fin according to the present invention.

More specifically, for example, an SOI wafer is provided as described with reference to FIG. 3. As shown in FIG. 3, the SOI wafer includes a substrate 1 positioned beneath the buried SiO ₂ layer 2. Above the buried SiO ₂ layer 2 is a silicon on insulator (SOI) layer that is patterned as an area forming the active region of each device, shown by FIN 3 of FIGS. Fins may be formed with standard lithography and etching operations known in the art. Instead, a known side wall image transfer method can be used to form each Fin 3.

After the Fin is formed, a sacrificial oxidation procedure, well known in the art, may be performed to remove any damage from the Fin etch procedure. If a well implant is used to adjust the threshold voltage of the FinFET device, the sacrificial oxide layer can be used as a screen to prevent channeling during the well implant.

The sacrificial oxide is then removed with a dry or wet etching chemical. For example, dilute hydrofluoric acid can be used to remove the sacrificial oxide. The gate dielectric may be formed after removal of the sacrificial oxide. Gate oxidation may be a thermal SiO ₂ (thermal SiO _2), a nitride, SiO ₂ (nitrided SiO ₂₎ or nitride oxide (oxy nitride). The gate dielectric can be a high K material, such as TaO ₃ , HfO _2, or any other gate dielectric material.

The gate electrode material may then be deposited on the entire wafer and then lithography and etching procedures may be performed. The gate electrode is represented by the electrode 4 in the figure.

After gate formation, reoxidation operations, well known in the art, can be used to improve gate dielectric properties. Gate reoxidization may be omitted.

During the procedure flow, here, source / drain extensions may be implanted or, in other approaches, offset spacers may be used to make the distance between the gate edge and the implanted Fin region. Lithography masks can be used to prevent the nFET region from being implanted while the pFET region is implanted, which is common in conventional CMOS process technology. Similar operations can be used to implant into the nFET region while blocking the pFET region.

After the source drain extension region is formed, extension anneal may be used to heal the damage caused by the implant. In another approach, heat treatment may be omitted. A deep source drain spacer can then be fabricated by depositing a SiN film in the range of 100 kV to 1000 kV and then highly directional etched to remove the SiN film from the horizontal plane but leaving the film in the vertical portion of the gate electrode.

Block masks and implants, which are standard in CMOS process technology, are used to form the source and drain regions for nFET device region 30 and pFET device region 20. Existing rapid thermal annealing is then used to activate the bond formed with the implant. This is followed by an existing salicide process using silicides known in CoSi ₂ , TiSi, NiSi or other known in the art.

In the course of the procedure, the invented steps and structures (FIGS. 4-17) begin to improve device performance for n-FET and p-FinFET devices. First, as shown in FIGS. 4 and 5, a SiO ₂ liner layer 5 is disposed (eg deposited), for example, by a low temperature deposition technique. The thickness of the film is in the range 25-300 mm 3 and the film deposition temperature is in the range 200-750 ° C. The film may be deposited by any of a variety of other known techniques, including sputter deposition, plasma enhanced chemical vapor deposition (PECVD), high speed thermal chemical vapor deposition (RTCVD), or other standard chemical vapor deposition (CVD) techniques. It is not limited to this. The purpose of this SiO ₂ film 5 acts as an etch stop for the second film to be deposited next. Thus, the liner layer or etch stop layer 5 need not be SiO ₂ and is any material that provides adequate etch stop capability for the next film deposited directly on the liner material layer 5.

After deposition of the liner layer or etch stop layer 5, the compressed film 6 shown in FIGS. 6 and 7 is deposited on the entire wafer. In a preferred embodiment, the compressed film 6 is, for example, a SiN film deposited by PECVD. The film 6 may be deposited with increased power in the range of 400 W to 1500 W to make greater compression on the film. To make the film compressive, it can be deposited using low deposition rates and temperature zones. Ideally, the compression in the film should range from -300 MPa to -3000 MPa and the film thickness should range from 200 kPa to 2000 kPa. Preferred deposition parameters are as follows: process temperature of 480 ° C, pressure of 5.75 torr, 395 mils spacing between wafer and electrode, 2% dilution SiH ₄ gas at 3000 sccm flow rate, NH at 15 sccm flow rate using 900 Watt RF power N gas at ₃ gas and 1060 sccm flow rates are used. This process produces a deposition rate of about 15.95 kW / s and a film stress of about (± 10%) -1400 MPa.

After the compressed film 6 is applied to the wafer, the block mask 7 shown in FIGS. 8 and 9 is used to mask the pFET region of the wafer. This block mask can be formed by existing lithography techniques known in the art. This mask is formed by conventional lithography procedures in which the photosensitive material is coated on the wafer surface and exposed through the mask. The photosensitive material is then developed, leaving a resist image or shape on the wafer that blocks the pFET region on the wafer.

After forming the block mask 7, the compressed film 6 is removed as a known wet etching or dry etching technique capable of removing the compressed film selectively to the block mask material. Plasma comprising CH ₂ F ₂ when the compressed film is SiN is an example of dry etching used for this purpose. After the compressed film is removed from the nFET region on the wafer, an intermediate structure appears in FIGS. 10 and 11.

In the process flow of the present invention, the block mask 7 is then removed from the wafer using a solvent or O ₂ plasma treatment known in the art to remove resist or organic material. Next, a second liner or etch stop material 8 is deposited on the front of the wafer, as shown in FIGS. 12 and 13. The second liner layer 8 has at least similar characteristics as the first liner layer described above. That is, the liner should be used as an etch stop for the subsequent film etch process.

Next, as shown in FIGS. 14 and 15, a tensile film 9 is deposited on the entire wafer. The tensile film is for example SiN and is deposited by, for example, CVD, PECVD, RTCVD or any other deposition technique capable of depositing highly tensile films. The thickness of the film should be in the range of 200 kPa to 2000 kPa and the stress should be in the range of +200 MPa to +2000 MPa or more tensile. Preferred deposition parameters use RF power of 340 Watts, process temperature of 480 ° C, pressure of 6.25 torr, 490 mils spacing between wafer and electrode, 2% dilution of 3000 sccm flow SiH ₄ Gas, NH ₃ gas at 15 sccm flow rate and N gas at 1060 sccm flow rate. This process produces a deposition rate of about 23 kW / s and a film stress of about 500 MPa.

In the process flow of the present invention, the block mask 10 is patterned on the nFET region of the wafer as shown in FIG. The properties of this block mask are similar to those of the block mask described above to block the pFET region. After the block mask is defined, known wet or dry etching procedures are performed to remove the tensile film 9 from the pFET region. This etch should be optional with the liner etch stop material 8. In this way, the etch used to remove the tensile film from the nFET region does not remove the compressed film on the pFET region. This block mask is then removed using a similar method used to remove the first block mask, resulting in final device structures 200 and 300 as shown in FIG.

In the process flow of the present invention, a 50 kPa to 500 kPa (not shown) thin film with low stress from -100 MPa compression to +100 MPa tension can be applied to the wafer to serve as a barrier layer. The purpose of this thin film is to fill in areas that are not covered with a compressive or tensile film. This optional film can be used to improve the suppression of contamination penetrating into Si and also to improve the etch stop properties for source-drain contact etching.

After the above operation is performed, the CMOS process may continue using standard process methods known in the art (not shown). More specifically, the following process is followed: deposition and planarization of the glass layers (ie, BPSG and TEOS), etching of source / drain contacts, deposition and planarization and contacting of the contact metals, wiring, vias and insulation. An additional level of insulation layer is formed to complete the chip.

The presence of a stress film on the longitudinal sidewalls of Fin surrounding the gate conductor creates the same type of stress (ie compression / compression, tensile / tensile) in the channel as the film. The stress of the source / drain regions on the longitudinal sidewalls of Fin is of the opposite type (ie compression / tensile, tensile / compression). To access source / drain diffusion, the film on the top surface of each Fin can be removed without losing the film effect on the longitudinal sidewalls.

Although what is presently considered and described as a preferred embodiment of the invention, it is apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.

The present invention can be applied to microelectronic devices.

Claims (17)

A PMOS device 200 and an NMOS device 300 disposed on the substrates 1, 2; The PMOS device 200 comprising a compressive layer 6 which stresses the active region 3 of the PMOS device; And The NMOS device 300 comprising a tensile layer 9 which stresses the active region 3 of the NMOS device, Wherein the compressive layer comprises a first dielectric material (6), the tensile layer comprises a second dielectric material (9) and the PMOS and NMOS devices are FinFET devices (200, 300). The semiconductor device structure as claimed in claim 1, wherein the first dielectric material comprises SiN. The semiconductor device structure as claimed in claim 1, wherein the second dielectric material comprises SiN. The semiconductor device structure as claimed in claim 1, wherein the first dielectric material has a substantially uniform compressive strain in the range of -300 MPa to -3000 MPa. The semiconductor device structure as claimed in claim 1, wherein the first dielectric material has a substantially uniform thickness in the range of 200 kV to 2000 kV. The semiconductor device structure as claimed in claim 1, wherein the second dielectric material has a substantially uniform tensile strain in the range of +200 MPa to +2000 MPa. The semiconductor device structure as claimed in claim 1, wherein the second dielectric material has a substantially uniform thickness in the range of 200 kV to 2000 kV. The semiconductor device structure as claimed in claim 1, wherein the first dielectric material and the second dielectric material are SiN. Providing a p-FinFET device region 200 and an n-FinFET device region 300 on the same substrate (1, 2); Disposing a first liner (5) on the p-FinFET device region and the n-FinFET device region; Placing a compressed film (6) on the first liner; Placing a first mask (7) on the p-FinFET device region; Removing the compressed film from the n-FinFET device region; Removing the first mask (7); Disposing a second liner (8) over the p-FinFET device region and the n-FinFET device region; Placing a tensile film (9) on the second liner; Placing a second mask (10) on the n-FinFET device region; Removing the tensile film from the p-FinFET device region; And Thereafter removing the second mask A semiconductor device structure manufacturing method comprising a. The method of claim 9, wherein disposing the compressed film comprises depositing a compressed film having a film stress of about −1400 MPa. 10. The method of claim 9, wherein placing the tensile film comprises depositing a tensile film having a film stress of about +500 MPa. The method of claim 9, wherein the compressed film is SiN. The method of claim 9, wherein the tensile film is SiN. The method of claim 9, wherein the compressed film is disposed with a substantially uniform thickness in the range of 200 kPa to 2000 kPa. 10. The method of claim 9, wherein the tensile film is disposed with a substantially uniform thickness in the range of 200 kPa to 2000 kPa. The method of claim 9, wherein disposing the compressed film comprises depositing a compressed film having a film stress of greater than about −1400 MPa. The method of claim 9, wherein disposing the tensile film comprises depositing a tensile film having a film stress of greater than about +500 MPa.

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