KR20060056489A - Method for cancelling interference in parallel dicision feedforward with chip equalizer and apparatus thereof - Google Patents

Abstract

The present invention relates to an adaptive partial parallel interference cancellation method and apparatus, and more particularly, to a parallel detection feedforward interference cancellation method and a device using a chip equalizer in a DS / CDM satellite DMB system. In the parallel detection feedforward interference cancellation method using a chip equalizer according to the preferred embodiment of the present invention, (a) a first estimation signal by filtering a signal received in the multipath channel in a chip equalizer included in the downlink receiver (B) despreading the first estimation signal received by the despreading detector to detect a signal for each channel, and (c) respreading the despreaded signal by the respreading unit (d) summing the respread channel-specific signals in the interference signal adding unit to generate a second estimation signal, (e) removing the second estimation signal from the first estimation signal in the interference signal removing unit Generating a third estimation signal to be reproduced, and (f) detecting the third estimation signal to be reproduced by the reproduction signal detection unit. The parallel detection feedforward interference cancellation method using the chip equalizer and the apparatus according to the present invention can eliminate the multiple access interference by using the chip equalizer at the parallel interference canceller input.

DMB, Chip Equalizer, Parallel Interference Canceller, Feedforward, Feedback.

Description

Method for canceling parallel detection feedforward interference using chip equalizer and its apparatus {Method for canceling interference in parallel dicision feedforward with chip equalizer and Apparatus             

1 is a system block diagram of a DMB digital system E according to the prior art.

2 is a block diagram of a parallel interference canceller for the cancellation of multiple access interference in the DS / CDM system according to the prior art.

3 is a block diagram of a chip equalizer of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a preferred embodiment of the present invention.

4A is a block diagram of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a first preferred embodiment of the present invention.

4B is a block diagram of a despread detection unit of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a first embodiment of the present invention.

4C is a block diagram of a re-spreading unit of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a first exemplary embodiment of the present invention.

5A is a block diagram of a parallel detection feedforward interference canceller using a chip equalizer performing a first step of iteration in a DS / CDM system according to a second preferred embodiment of the present invention.

5B is a block diagram of a parallel detection feedforward interference canceller using a chip equalizer performing a second step of iteration in a DS / CDM system according to a second preferred embodiment of the present invention.

6 is a block diagram of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a third embodiment of the present invention.

<Explanation of protection for main parts of drawing>

410: Chip Equalizer

420: despread detector

430: respreading unit

440: interference signal adder

450: time delay unit

460: interference signal removing unit

470: playback signal detection unit

The present invention relates to an adaptive partial parallel interference cancellation method and apparatus therefor, and more particularly, to a parallel detection feedforward interference cancellation method and a device using a chip equalizer in a DS / CDM satellite DMB system.

DS / CDM-QPSK (Direct Sequence / Code Division Multiplux-Quadrature Phase Shift Keying) adopted as the standard method of domestic digital multimedia breadcating (DMB) is a multi-channel that transmits broadcast contents to the ground through satellite repeaters or ground repeaters. High quality multimedia service.

Satellite DMB Digital System E, recommended by ITU-R BO.1130-4, provides multimedia broadcasting services such as additional data and high quality audio and video to mobile, portable and fixed receivers through satellite repeaters and gap-fillers. Designed to provide

1 is a system block diagram of a DMB digital system E according to the prior art.

Referring to FIG. 1, the satellite DMB broadcasting center 110 transmits various contents received from the program provider 150 and the like to a transmitting earth station, and the transmitting earth station transmits audio, video and data signals to a CDM (Code Division Multiplex) or TDM ( Time division multiplex (QD) multiplexing, Ku-band (14 GHz) carrier signal is QPSK modulated and then transmitted to satellite 120. The satellite 120 directly converts the S-band (2.6 GHz) CDM signal to a mobile terminal 140 such as a mobile phone and a vehicle receiver on the ground, or transmits a ground repeater (a terrestrial repeater) 130 is transmitted as a TDM signal in the Ku band, and the repeater 130 converts the signal into a CDM signal in the S band and transmits it to the subscriber station 140.

Referring to the transmitter of the digital system E, different orthogonal spreading codes are used to independently broadcast their own programs for each station, and the pilot channel synchronizes and controls the receiver. Send the data. The channel code uses a Reed-Solomon code as an outer code and a concatenated code using a convolutional code as an internal code. The outer call is divided into a transmission channel and a pilot channel. The transmission channel uses RS (204, 188), which has removed 51 bytes from RS (255, 239), and the pilot channel uses RS (96, 80), respectively. Error correction capability up to 8 bytes. The convolutional code of the inner code uses puncturing a coded output with a constraint length of 7 and a mother code rate of 1/2, 2/3, 3/4, 5/6, 7 Make a variable code rate of / 8. The byte interleaver uses a convolutional interleaver with a period of 12 in both units of a transport channel and a pilot channel, and the bit interleaver of the transmission signal is a split type convolutional interleaver with a period in 51 of a bit unit. Use

However, the DS / CDM-QPSK signal loses orthogonality between the codes of broadcast channels due to multipath fading in urban environments or shadowed areas where reception environment is poor, and thus, multiple access interference (MAI) is increased. Bit Error Rate, hereinafter referred to as BER). In addition, the Rake receiver currently used to receive satellite DMB signals is simple to implement and has the advantage of achieving receive diversity performance by multiple paths, but it does not eliminate multiple access interference. There is a problem that a large gap occurs between the possible channel capacity and the theoretical channel capacity.

In order to solve this problem, many researches have been conducted on multi-user detectors in wireless mobile communication. Conventional multiple user detection (Multiple User Detection) is a technique required at the receiving end of the base station, has been studied a lot to solve the problem of the multi-access interference generated in the uplink (uplink). The optimal interference canceller proposed by S. Verdu according to the prior art has a problem that it is difficult to implement practically because the complexity of the system increases exponentially with the number of users. As an alternative, a suboptimal detector has been proposed, which is largely divided into a linear interference canceller and a nonlinear interference canceller. The linear interference canceller is a linear transformation applied to the output of a conventional matched filter stage, and is basically proposed for a synchronization system. There are a decorrelating receiver and a minimum mean square error (MMSE) receiver. The decorrelator receiver increases the noise power in the process of multiplying the inverse matrix, and the MMSE receiver has to know the signal size and noise variance of all users in advance. The nonlinear interference canceller improves the structure of the receiver to improve performance. The nonlinear interference canceller is classified into a sequential interference canceller (SIC) and a parallel interference canceller (PIC). The parallel interference canceller is proposed to reduce the detection delay of the sequential interference canceller and to omit the process of rearranging the received signals. That is, all user signals are detected in parallel at the same time, and then other user signals other than the desired user are removed from the received signal. Since the DS / CDM satellite DMB system is a synchronous system and the signal power of all broadcasting channels is the same, multiple access interference can be efficiently removed through a parallel interference canceller structure.

2 is a block diagram of a parallel interference canceller for the cancellation of multiple access interference in the DS / CDM system according to the prior art.

The parallel interference canceller according to the related art estimates all broadcast channel signals sent from a transmitter and simultaneously removes multiple access interference corresponding to each broadcast channel. The received signal of the k-th broadcast channel estimated in the multi-stage d-th is represented by the following equation.

(1)

(One)

는 k(k=1,2,...,K)번째 방송채널의 d-1번째 단계에서 추정된 m번째 QPSK 심볼 데이터이고,

는 l(l=0,1,,...,L-1)번째 경로의 채널 추정된 계수이며, 추정된 QPSK 심볼 데이터

에 방송채널마다 똑같은 채널추정된 계수와 방송채널 구분을 위한 확산 부호열

를 곱해 주어 송신단에서 보내온 신호를 재생(regeneration)하게 된다. 방송신호는 다중 경로 채널을 겪으므로, L개의 탭 길이를 갖는 FIR (Finite Impulse Response) 필터를 이용해서 채널계수를 곱해주게 된다.here,

Is the mth QPSK symbol data estimated in step d-1 of the k (k = 1,2, ..., K) th broadcasting channel,

Is the channel estimated coefficient of the l (l = 0,1, ..., L-1) th path, and the estimated QPSK symbol data

The same channel estimation coefficient for each broadcasting channel and spreading code sequence

Multiply by to regenerate the signal from the transmitter. Since the broadcast signal undergoes a multipath channel, the channel coefficient is multiplied using a finite impulse response (FIR) filter having L tap lengths.

Referring to FIG. 2, a parallel interference canceller structure proposed for multiple access interference cancellation in downlink of a conventional DS / CDM system is shown. Assuming that the first broadcast channel is received, the multiple access interference is expressed as the sum of the remaining broadcast channel signals except the first broadcast channel, as shown in Equation (2), and the rake receiver output is shown in Equation (3). This is removed from the received signal r (t) and the QPSK symbol is detected using the Rake receiver output.

(2)

(2)

(3)

(3)

의 I, Q 신호는 각각 수학식(4), (5)와 같고,

는 부호 검출기를 의미한다.QPSK Symbol

I and Q signals of Equation (4) and (5), respectively,

Means a sign detector.

(4)

(4)

(5)

(5)

As described above, when the rake receiver is used for the parallel interference canceller, more reliable data estimation is possible when the matched filter is used, thereby efficiently eliminating the multiple access interference. However, the rake receiver also has an incorrect data estimate in the initial stage, which remains as an error of the next stage, thereby increasing the multiple access interference.

Accordingly, an object of the present invention is to provide a parallel detection feedforward interference cancellation method and apparatus using a chip equalizer that can eliminate multiple access interference by using a chip equalizer at the parallel interference canceller input stage. have.

Another object of the present invention is to provide a method and apparatus for parallel detection feedforward interference cancellation using a chip equalizer that can improve reception BER performance by removing multiple access interference and increase potential channel capacity.

Another object of the present invention is to provide a parallel detection feedforward interference cancellation method using a chip equalizer and a device capable of reducing hardware complexity by reducing the number of despread detection units.

Other objects of the present invention will become more apparent through the preferred embodiments described below.

In order to achieve the above objects, according to an aspect of the present invention, it is possible to provide a parallel detection feedforward interference cancellation method using a chip equalizer.

In the parallel detection feedforward interference cancellation method using a chip equalizer according to the preferred embodiment of the present invention, (a) a first estimation signal by filtering a signal received in the multipath channel in a chip equalizer included in the downlink receiver (B) despreading the first estimation signal received by the despreading detector to detect a signal for each channel, and (c) respreading the despreaded signal by the respreading unit (d) summing the respread channel-specific signals in the interference signal adding unit to generate a second estimation signal, (e) removing the second estimation signal from the first estimation signal in the interference signal removing unit Generating a third estimation signal to be reproduced, and (f) detecting the third estimation signal to be reproduced by the reproduction signal detection unit.

Here, the receiver on the downlink may be a receiver of a satellite DMB system.

Preferably, in the parallel detection feedforward interference cancellation method using a chip equalizer according to a preferred embodiment of the present invention, step (a) includes transmitting the first estimation signal to a time delay unit in the chip equalizer, The time delay unit may further include delaying and outputting the first estimation signal by a delayed time while the signals for each channel are added to generate the second estimation signal in steps (b) to (d).

In the parallel detection feedforward interference cancellation method using a chip equalizer according to an embodiment of the present invention, the step (d) includes transmitting the generated second estimation signal to a residual channel estimation filter, and the residual channel estimation filter. The method may further include convolutionally calculating the coefficients of the second estimation signal and the residual channel estimation filter to modify the second estimation signal.

In order to achieve the above objects, according to another aspect of the present invention, it is possible to provide a parallel detection feedforward interference cancellation method using a chip equalizer that is repeated.

In the parallel detection feedforward interference cancellation method using a chip equalizer that is repeatedly executed according to a preferred embodiment of the present invention, (a) a chip equalizer included in the downlink receiver may filter a signal received from the multipath channel. Transmitting a first estimated signal to a switch, (b) distributing the received signal at the switch corresponding to a predetermined number of despread detectors, wherein the number of despread detectors is less than the number of channels; (c) despreading the distributed signal received by the despreading detector to detect a signal for each channel, (d) respreading the despreaded signal by the respreading unit, and (e) an interference signal Generating a second estimation signal by summing the respread channel-specific signals in an adder; and (f) the second estimate from the signal received in step (b) in the interference signal canceller. Transmitting a third estimation signal to the switch after removing a call to generate a third estimation signal, and (g) steps (b) to (f) are repeated a predetermined number of times and the interference is repeated in the last iteration. The signal removing unit may include transmitting the third estimation signal to a reproduction signal detection unit, and (h) detecting the third estimation signal to be reproduced by the reproduction signal detection unit.

Here, the receiver on the downlink may be a receiver of a satellite DMB system.

Preferably, in the parallel detection feedforward interference elimination method using a chip equalizer repeatedly performed according to a preferred embodiment of the present invention, the step (b) includes transmitting the received signal from the switch to a time delay unit; The time delay unit may further include delaying and outputting the received signal by a delayed time while the signal distributed in the steps (c) to (e) is generated as the second estimation signal.

In addition, in the parallel detection feedforward interference cancellation method using a chip equalizer that is repeatedly executed according to a preferred embodiment of the present invention, the step (e) includes transmitting the generated second estimation signal to the residual channel estimation filter. The residual channel estimation filter may further include convolutionally calculating the coefficients of the second estimation signal and the residual channel estimation filter to modify the second estimation signal.

In order to achieve the above objects, according to another aspect of the present invention, it is possible to propose a parallel detection feedforward interference canceller using a chip equalizer.

The parallel detection feedforward interference canceller using the chip equalizer according to the preferred embodiment of the present invention filters a signal received in the multipath channel and outputs a first estimation signal, and receives the first estimation signal and receives the inverse. A despread detector that detects a signal for each channel after spreading, a respreader that receives and respreads the despread signal, and an interference signal adder that adds the respreaded channel-specific signals to generate a second estimation signal And an interference signal remover configured to remove the second estimated signal from the first estimated signal to generate a third estimated signal to be reproduced, and a reproduced signal detector to detect the third estimated signal to be reproduced.

Here, the receiver on the downlink may be a receiver of a satellite DMB system.

Preferably, the parallel detection feedforward interference canceller using the chip equalizer according to the preferred embodiment of the present invention receives the first estimation signal from the chip equalizer, and the signals for each channel are summed to generate a second estimation signal. The apparatus may further include a time delay unit configured to delay and output the first estimation signal by a delayed time.

In addition, the parallel detection feedforward interference canceller using the chip equalizer according to the preferred embodiment of the present invention receives the generated second estimation signal and convolutions the coefficients of the second estimation signal and the residual channel estimation filter. The method may further include a residual channel estimation filter for correcting the second estimation signal and transmitting the modified second estimation signal to the interference signal canceller.

In order to achieve the above objects, according to another aspect of the present invention, it is possible to present a parallel detection feedforward interference canceller using a chip equalizer that is repeated.

The parallel detection feedforward interference canceller using a chip equalizer for repetitive implementation according to a preferred embodiment of the present invention filters a signal received in the multipath channel and transmits a first estimated signal to a switch, the chip equalizer. A switch for distributing a signal received from a signal or an interference signal canceller corresponding to a predetermined number of despread detectors, wherein the number of despread detectors is smaller than the number of channels, and after receiving and despreading the distributed signals, A despreading detector detecting a signal for each channel, a respreading unit for receiving and respreading the despread signal, an interference signal adding unit for generating a second estimated signal by adding the respreaded channel-specific signals, and the switch Removes the second estimation signal from the signal received at to generate a third estimation signal, and then transmits the signal to the switch. An interference signal removing unit transmitting the third estimation signal to the reproduction signal detection unit in a last repetition trial may include a reproduction signal detection unit detecting the third estimation signal to be reproduced.

Here, the receiver on the downlink may be a receiver of a satellite DMB system.

Preferably, the parallel detection feedforward interference canceller using a repeater chip equalizer according to a preferred embodiment of the present invention receives the entire signal output from the switch, and the distributed signal is generated as a second estimation signal. The apparatus may further include a time delay unit configured to delay and output the received signal by a delayed time.

In addition, the parallel detection feedforward interference canceller using a repeater chip equalizer according to a preferred embodiment of the present invention receives the generated second estimation signal and weaves coefficients of the second estimation signal and the residual channel estimation filter. The method may further include a residual channel estimation filter for modifying the second estimation signal by performing a convolution operation and transmitting the modified second estimation signal to the interference signal canceller.

Hereinafter, a preferred embodiment of a parallel detection feedforward interference cancellation method and a device using the chip equalizer according to the present invention will be described in detail with reference to the accompanying drawings, and with reference to the accompanying drawings, regardless of the reference numerals The same or corresponding components are given the same reference numerals and redundant description thereof will be omitted.

3 is a block diagram of a chip equalizer of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a preferred embodiment of the present invention. Referring to FIG. 3, the chip equalizer 410 includes an adaptive N-tap FIR filter 413 and an adaptive algorithm 415.

The chip equalizer 410 used in the present invention uses an adaptive finite impulse response (FIR) filter having N taps according to the prior art. Here, the chip equalizer 410 performs a convolution operation on the input signal and the coefficients of the chip equalizer 410 by using an FIR filter and an adaptive algorithm, and outputs the signal, after which the output signal is despread. The detector detects data signals.

The data signal is divided into an input signal and an output signal and described as follows.

(6)

(6)

(7)

(7)

(8)

(8)

(9)

(9)

은 칩 등화기(410)의 입력 신호이고,

은 칩 등화기(410)의 출력 신호이며,

은 칩 등화기(410)의 계수이다. 또한, H는 벡터 헤르미션 변환(vector Hermitian transpose)이고, T는 벡터 트랜스포즈(vector transpose)이다. 칩 등화기(410)의 계수

는 LMS, RLS 등의 적응 알고리즘(adaptive algorithm)을 사용하여 수정된다. here,

Is the input signal of the chip equalizer 410,

Is the output signal of the chip equalizer 410,

Is the coefficient of chip equalizer 410. In addition, H is a vector Hermitian transpose and T is a vector transpose. Coefficient of chip equalizer 410

Is modified using an adaptive algorithm such as LMS and RLS.

In the above, the configuration diagram of the chip equalizer of the parallel detection feedforward interference canceller using the chip equalizer in the DS / CDM system according to the preferred embodiment of the present invention has been described. Hereinafter, the chip equalization according to the present invention will be described with reference to the accompanying drawings. The parallel detection feedforward interference cancellation method and apparatus using the same will be described with reference to specific embodiments. Embodiments according to the present invention are divided into three categories as follows. First, a method of eliminating multiple access interference from a signal received in a multipath channel using a chip equalizer in general, and second, using a chip equalizer to reduce the number of detectors for signal detection and to increase the number of iterations. Third, a method of removing interference is classified into a method of canceling multiple access interference by using a residual channel estimation filter while using a chip equalizer. In all the above-described methods, it is assumed that components for removing multiple access interferences are selectively added while using a chip equalizer in common, and the signal detected and reproduced last is the first broadcast channel signal. In the following description, the method for removing the multiple access interference according to the third method described above will be described first from the first method having the best performance but the lowest implementation complexity.

4A is a block diagram of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a first embodiment of the present invention. Referring to FIG. 4A, the parallel detection feedforward interference canceller using the chip equalizer in the DS / CDM system according to the first exemplary embodiment of the present invention may include a chip equalizer 410, a despread detector 420, and a respreader ( 430, an interference signal adding unit 440, a time delay unit 450, an interference signal removing unit 460, and a reproduction signal detection unit 470.

The chip equalizer 410 filters the signal received in the multipath channel and outputs a first estimation signal. The received signal passing through the chip equalizer 410 is compensated for the inter-symbol interference (ISI) by the channel to restore the orthogonality between the broadcast channels, and also the multiple access interference between the broadcast channels during the despreading process. Reduction can improve reception performance.

The despreading detector 420 receives the first estimation signal from the chip equalizer 410, despreads the signal, and detects a signal for each channel. Since it is assumed that the receiver receives the first broadcast channel signal, the other channel signals become interference signals, and thus, the despreading detector 420 should be included as many as the second to kth broadcast channels corresponding to the broadcast channel. . The signal passing through the chip equalizer 410 passes through the despread detector 420 to detect transmission data for each channel, and the detected data passes through the respreader 430 and the interference signal adder 440. Is generated. The interference signal component in the output signal of the chip equalizer 410 is removed by the interference signal canceller 460 and detected as the first broadcast channel data.

The respreader 430 receives the despread signal from the despreader 420, respreads, and adjusts gain.

The interference signal adder 440 may generate the second estimation signal by summing the respread channel-specific signals.

When the time delay unit 450 receives the first estimation signal from the chip equalizer 410 and the first estimation signal passes through the despread detector 420, the respreader 430, and the interference signal adder 440. Therefore, the first estimation signal is delayed and output by the delayed time while the signals for each channel are summed to generate the second estimation signal. In order to remove the multiple access interference, signal detection is required. In this process, a signal of 64 chips must be input to determine one data symbol, and therefore, the interference signal removal unit 460 detects the third estimation signal, which is the first broadcast channel. In order to generate the data, the waiting time of the first estimation signal is required until a delay time passes through the despread detector 420 and the interference signal adder 440. Therefore, the delay time unit 450 may be further included for the waiting time for the first estimation signal.

This input / output signal is expressed by the following equation.

(10)

10

에 대하여 다중 채널 간섭 요소가 된다. 따라서

신호로부터 p(n)을 빼주면 다중 채널 간섭 요소가 최소화된 신호

을 얻을 수 있다. That is, since the second estimation signal p (n) output from the interference signal adder 440 is delayed by N when performing the above-described detection process and despreading process, the N delayed signal passing through the chip equalizer 410 is delayed. Output signal of chip equalizer 410

It is a multi-channel interference element for. therefore

Subtract p (n) from the signal to minimize multichannel interference

Can be obtained.

The interference signal removing unit 460 removes the second estimation signal from the first estimation signal to generate a third estimation signal, which is the first broadcast channel signal to be reproduced.

The reproduction signal detector 470 detects the third estimation signal to be reproduced, and then reproduces the first broadcast channel signal. The reproduction signal detector 470 detects the reproduction signal according to the same principle as that performed by the despread detection unit 420.

Here, T _C and T _B represent a chip sampling time and a bit (data) bit sampling time, respectively. That is, referring to FIG. 4, a process of processing a signal input at a chip rate or a data rate at each step is illustrated.

4B is a block diagram of a despread detection unit of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a first embodiment of the present invention. Referring to FIG. 4B, the despread detection unit of the parallel detection feedforward interference canceller using a chip equalizer in the DS / CDM system according to the first preferred embodiment of the present invention is a multiplier 423 for integrating a despread, an integrator. and an detector 425 and a detector.

The despreading detector 420 receives the first estimation signal and despreads it, detects the signal for each channel, and expresses the input and output signals by vector equations as follows. The reproduction signal detection unit 470 processes the input and output signals in the same principle. That is, referring to FIG. 4A, 'detect s1', 'detect s2', and the like process the input / output signals as follows.

(11)

(11)

(12)

(12)

(13)

(13)

는 칩 등화기(410)의 출력 벡터이며,

는 첫번째 확산 부호 (spreading code)이다. here,

Is the output vector of the chip equalizer 410,

Is the first spreading code.

4C is a block diagram of a re-spreading unit of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a first embodiment of the present invention. In the DS / CDM system according to the first exemplary embodiment of the present invention, the respreading unit 430 of the parallel detection feedforward interference canceller using the chip equalizer is connected to the gain control unit 435, whereby the despreading detection unit 420 The despread signal is received, respread, gain is adjusted, and the input / output signal is expressed as a vector expression as follows.

(14)

(14)

(15)

(15)

(16)

(16)

은 칩 등화기(410)에서 출력된 신호의 벡터이고,

는 두번째 확산 부호(spreading code)이다. Where g ₂ is the gain scaling,

Is the vector of the signal output from the chip equalizer 410,

Is the second spreading code.

5A is a block diagram of a parallel detection feedforward interference canceller using a chip equalizer performing a first step of iteration in a DS / CDM system according to a second preferred embodiment of the present invention, and FIG. 5B is a second preferred embodiment of the present invention. A block diagram of a parallel detection feedforward interference canceller using a chip equalizer performing a second step of iteration in a DS / CDM system according to an embodiment. 5A and 5B, the parallel detection feedforward interference canceller using the chip equalizer in the DS / CDM system according to the second preferred embodiment of the present invention is the chip equalizer 410, the switch (SW) 510, and the inverse. The diffusion detector 420, the respreader 430, the interference signal adder 440, the time delay unit 450, the interference signal remover 460, and the reproduction signal detector 470 are configured to be included. The differences from the first embodiment described above will be mainly described.

The switch 510 distributes the signal received from the initial chip equalizer 410 corresponding to a preset number of channel detectors. That is, the switch 510 multiplexes the first received signal and the signal from which interference is removed at each step. Here, the number of despread detectors 420 is smaller than the number of channels. That is, instead of the despread detection unit 420 corresponding to the number of channels for detecting the interference signal provided in the above-described first embodiment, the number of despread detection units 420 smaller than the number of channels is provided here. Therefore, without removing the interference signal at once, repeated interference signals are removed. For example, referring to FIG. 5A, when k is 5, first S2, S3, S4, and S5 become the despreading detection units 420 of broadcast channels 2, 3, 4, and 5, respectively, The output signal passes through the interference signal canceller 460 and is again input to the switch 510. Referring to FIG. 5B, the next steps S6, S7, S8, and S9 become the despreading detection units 420 of broadcast channels 6, 7, 8, and 9, respectively. Therefore, by repeatedly performing this process, multiple access interference can be eliminated, and the first broadcast channel to be finally reproduced can be detected and reproduced. The number of repetitions here is determined according to the number of entire channels and the number of signals despread at each step. Therefore, the hardware complexity can be reduced by configuring the number of despread detectors 420 less than the first embodiment.

Here, the time delay unit 450 receives the entire signal output from the switch 510 and receives the entire signal received from the switch 510 by the delayed time while the signal distributed in each iteration step is generated as the second estimation signal. Delayed output.

6 is a block diagram of a parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a third embodiment of the present invention. Referring to FIG. 6, the parallel detection feedforward interference canceller using a chip equalizer in a DS / CDM system according to a third exemplary embodiment of the present invention may include a chip equalizer 410, a switch (SW) 510, and a despread detector. 420, a respreader 430, an interference signal adder 440, a time delay unit 450, a residual channel estimation filter 610, an interference signal canceller 460, and a reproduction signal detector 470. It is configured by. Since the third embodiment may be configured by further adding the residual channel estimation filter 610 to the above-described first and second embodiments, the following description will focus on differences from the second embodiment.

Residual Channel Estimation Filter (RCEF) 610 is an adaptive finite impulse response (FIR) filter for removing channel impulse responses that are not completely compensated for in the chip equalizer 410, and the interference signal adder The second estimation signal generated at 440 is received, and a convolution operation is performed between the channel coefficient and the chip equalizer coefficient and transmitted to the interference signal removing unit 460. The residual channel estimation filter 610 operates at the same chip rate as the chip equalizer 410, and uses a detection directed LMS algorithm, a constant modulus (CMA) algorithm, or a minimum output energy (moe). Coefficients can be adaptively changed using algorithms or the like.

The input / output signal of the residual channel estimation filter 610 is expressed as a vector expression as follows.

(17)

(17)

(18)

(18)

(19)

(19)

(20)

20

은 잔여 채널 추정 필터(610)의 입력 신호의 벡터 표현이고,

은 출력 신호의 벡터 표현이며,

은 잔여 채널 추정 필터(610)의 계수이고, M은 계수 크기이면서 입출력 벡터의 크기이다. here,

Is a vector representation of the input signal of residual channel estimation filter 610,

Is a vector representation of the output signal,

Is the coefficient of the residual channel estimation filter 610, and M is the magnitude of the input and output vectors.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the method and apparatus for parallel detection feedforward interference cancellation using the chip equalizer according to the present invention can eliminate the multiple access interference by using the chip equalizer at the parallel interference canceller input.

In addition, the parallel detection feedforward interference cancellation method and apparatus using the chip equalizer according to the present invention can improve the reception BER performance by eliminating multiple access interference, and can increase the potential channel capacity.

In addition, the parallel detection feedforward interference cancellation method using the chip equalizer and the apparatus according to the present invention can reduce the complexity of hardware by reducing the number of despread detection unit.

Claims (16)

A parallel interference cancellation method performed in a receiver on a downlink for canceling multiple access interference in a multipath channel, (a) outputting a first estimation signal by filtering a signal received in the multipath channel in a chip equalizer included in the downlink receiver; (b) despreading the first estimation signal received by the despreading detector and detecting a signal for each channel; (c) respreading the despread signal in a respreading unit; (d) generating a second estimation signal by summing the respread channel-specific signals in the interference signal adding unit; (e) generating a third estimation signal to be reproduced by removing the second estimation signal from the first estimation signal in the interference signal removing unit; And and (f) detecting a third estimation signal to be reproduced by a reproduction signal detection unit. The method of claim 1, And the receiver on the downlink is a receiver of a satellite DMB system. The method of claim 1, Step (a) is Transmitting the first estimation signal to a time delay unit in the chip equalizer; And The time delay unit may further include delaying and outputting the first estimation signal by a delayed time while the signals for each channel are added to each other in step (b) to (d) to generate the second estimation signal. Parallel Detection Feedforward Interference Cancellation Using Chip Equalizer. The method of claim 1, Step (d) Transmitting the generated second estimation signal to a residual channel estimation filter; And The residual channel estimation filter further comprises convolutionally calculating the coefficients of the second estimation signal and the residual channel estimation filter to modify the second estimation signal. Forward interference cancellation method. A parallel interference cancellation method performed in a receiver on a downlink for canceling multiple access interference in a multipath channel, (a) transmitting a first estimation signal to a switch by filtering a signal received in the multipath channel in a chip equalizer included in the downlink receiver; (b) distributing the received signal at the switch corresponding to a predetermined number of despread detectors, wherein the number of despread detectors is less than the number of channels; (c) despreading the distributed signal received by the despreading detector and detecting a signal for each channel; (d) respreading the despread signal by a respreading unit; (e) generating a second estimation signal by summing the respread channel-specific signals by the interference signal adding unit; (f) generating a third estimation signal by removing the second estimation signal from the signal received in step (b) and transmitting the third estimation signal to the switch by the interference signal removing unit; (g) steps (b) to (f) are repeated a predetermined number of times, and in the last iteration, the interference signal removing unit transmits the third estimation signal to a reproduction signal detection unit; And and (h) detecting, by the reproduction signal detector, the third estimation signal to be reproduced. The method of claim 5, And the receiver on the downlink is a receiver of a satellite DMB system. The method of claim 5, Step (b) is Transmitting the received signal by the switch to a time delay unit; And The time delay unit may further include delaying and outputting the received signal by a delayed time while the signal distributed in the steps (c) to (e) is generated as the second estimation signal. Parallel Detection Feedforward Interference Cancellation Method. The method of claim 5, Step (e) is Transmitting the generated second estimation signal to a residual channel estimation filter; And The residual channel estimation filter further comprises convolutionally calculating the coefficients of the second estimation signal and the residual channel estimation filter to modify the second estimation signal. Forward interference cancellation method. A parallel interference canceller included in a receiver on a downlink in a multipath channel and canceling multiple access interference, A chip equalizer for filtering a signal received in the multipath channel and outputting a first estimation signal; A despread detection unit configured to receive the first estimation signal, despread it, and detect a signal for each channel; A respreading unit for receiving and respreading the despread signal; An interference signal adder configured to add the respread channel-specific signals to generate a second estimation signal; An interference signal removing unit which generates a third estimation signal to be reproduced by removing the second estimation signal from the first estimation signal; And And a reproduction signal detector for detecting the third estimated signal to be reproduced. The method of claim 9, And the receiver on the downlink is a receiver of a satellite DMB system. The method of claim 9, The chip equalizer further includes a time delay unit for receiving the first estimation signal and delaying and outputting the first estimation signal by a delayed time while the signals for each channel are summed to generate a second estimation signal. Parallel detection feedforward interference canceller using a chip equalizer. The method of claim 9, Receiving the generated second estimation signal, convolutionally calculating the coefficients of the second estimation signal and the residual channel estimation filter to modify the second estimation signal, and modifying the modified second estimation signal to the interference signal. Parallel detection feedforward interference canceller using a chip equalizer, characterized in that it further comprises a residual channel estimation filter for transmitting to the canceller. A parallel interference canceller included in a receiver on a downlink in a multipath channel and canceling multiple access interference, A chip equalizer for filtering a signal received in the multipath channel and transmitting a first estimation signal to a switch; A switch for distributing a signal received from the chip equalizer or the interference signal canceller corresponding to a predetermined number of despread detectors, wherein the number of despread detectors is smaller than the number of channels; A despread detection unit configured to receive the distributed signal, despread it, and detect a signal for each channel; A respreading unit for receiving and respreading the despread signal; An interference signal adder configured to add the respread channel-specific signals to generate a second estimation signal; An interference signal that removes the second estimation signal from the signal received by the switch to generate a third estimation signal and transmits it to the switch, and then transmits the third estimation signal to a reproduction signal detection unit in the last repetition of a preset number of times; Removal unit; And And a reproduction signal detector for detecting the third estimated signal to be reproduced. The method of claim 13, And the receiver on the downlink is a receiver of a satellite DMB system. The method of claim 13, And a time delay unit configured to receive the entire signal output from the switch and delay and output the received signal by a delayed time while the distributed signal is generated as a second estimation signal. Parallel Detection Feedforward Interference Canceller. The method of claim 13, Receiving the generated second estimation signal, convolutionally calculating the coefficients of the second estimation signal and the residual channel estimation filter to modify the second estimation signal, and modifying the modified second estimation signal to the interference signal. Parallel detection feedforward interference canceller using a chip equalizer, characterized in that it further comprises a residual channel estimation filter for transmitting to the canceller.

Images