KR20060050821A - Pre-emphasis output buffer and semiconductor memory device for driving output pin connected pull-up termination, method for driving output - Google Patents

Abstract

A data output buffer for driving a transmission line having a pull-up termination resistor is disclosed. The data output buffer includes an output terminal connected to the other end of a transmission line having a pull-up termination resistor connected to one end, a buffer for pulling up the output terminal to a first power supply voltage or a second power supply voltage in response to output data, and the output. And a pull-down driving unit for preemphasizing the initial pull-down driving of the output terminal in response to data. Therefore, it is possible to improve the pulldown characteristics of the transmission line having the pull-up termination resistor.

Description

Pre-emphasis Output Buffer and Semiconductor Memory Device for Driving Output Pin connected Pull-Up Termination, Method for driving Output}

1 is a diagram illustrating a push-pull data output buffer for driving a transmission line connected to a conventional VDDQ termination resistor.

2 is a timing diagram for explaining the operation of FIG.

3 is a timing diagram for explaining a conventional data strobe signal.

4 is a block diagram of a memory device having a pre-emphasis output buffer according to the present invention.

FIG. 5 is a detailed circuit diagram of the pre-emphasis data output buffer of FIG. 4. FIG.

6 is a block diagram of a preferred embodiment of the tip detection unit of FIG.

7 is a timing diagram for explaining the operation of FIG.

8A illustrates an eye pattern of a pre-emphasis data output buffer according to the present invention.

8B is a view showing an eye pattern of a data output buffer without a conventional pre-emphasis function.

9 is a block diagram of a pre-emphasis data strobe signal output buffer according to the present invention.

10 is a detailed circuit diagram of the drivers of FIG.

FIG. 11 is a view of each sub waveform of FIGS. 9 and 10.

The present invention relates to a data output buffer, a data strobe output buffer, and a memory device, and more particularly, to a data output buffer, a data strobe output buffer, and a memory device having a pre-emphasis function for compensating transmission line loss of output data.

As the speed of computer and network systems increases, the speed and capacity of memory such as DRAM are also required. In a computer system, a central processing unit (CPU) and a memory are interconnected through a memory controller, and the memory is composed of a memory module inserted into a slot formed on a motherboard. The memory controller and the memory module are electrically connected through transmission lines formed on the printed circuit board. Therefore, signal attenuation by the transmission line increases the signal attenuation of the transmission line in proportion to the distance between the memory controller and the memory module.

In order to compensate for attenuation due to signal reflection at the transmission line termination, a termination technique has been introduced to apply the termination voltage to the transmission line termination through the termination resistor.

In the DDR2 memory module, in order to simplify the wiring on the motherboard, terminating resistors are installed in the DRAM chips in each module, and the terminating resistors of the active state modules are activated by turning off the terminating resistors of the active state modules. On Die Termination (ODT) technology is adopted to act as the termination resistor of the module.

FIG. 1 is a diagram illustrating a transmission line of a system including a conventional push-pull data output buffer and a termination resistor (RTT) for applying a VDDQ to a transmission line, and FIG. 2 illustrates an operation timing of FIG. 1.

The transmission chip 100 drives the internal data signal DATA to the output terminal 104 through the push-pull data output buffer 102. The output terminal 104 is connected to the terminating resistor RTT through the transmission line 106 and the terminating resistor RTT is connected to the power supply voltage VDDQ.

The receiving chip 110 receives the signal received through the transmission line 106 from the input buffer 112 and compares the signal with the reference voltage VREF to input a data high state or a data low state.

When the transmission chip 100 outputs the data high state, since the data signal DATA is low, the pull-up transistor PUD of the output buffer 102 is turned on and the pull-down transistor PDD is turned off. Therefore, since the power supply voltage VDDQ is applied to the output terminal 104 through the pull-up transistor PUD, and VDDQ is applied through the termination resistor RTT, the data output voltage DQ of the output terminal quickly reaches the VDDQ level. Will rise.

Since the data signal DATAB is high when the transmitting chip outputs the data low state, the pull-up transistor PUD of the output buffer 102 is turned off and the pull-down transistor PDD is turned on. Therefore, since the power supply voltage VSSQ is applied to the output terminal 104 through the pull-down transistor PDD, the data output voltage DQB of the output terminal is slowed down compared to the DQ rising speed to the VOL level of the following equation.

VOL = (VDDQ-VSSQ)RON_PDD / ( RON_PDD + RTT + RTL)

VOL = (VDDQ-VSSQ) RON _PDD / (RON _PDD + RTT + RTL)

RON _PDD ; On-resistance of pulldown transistor

   RTL; Transmission line resistance

Therefore, it can be seen that the intersection of the rising transition and the falling transition occurs at a level higher than the VREF level, as indicated by the portion indicated by A in FIG. 2. That is, skew occurs between the rising transition and the falling transition of the data output signal, thereby degrading signal integrity.

Conventionally, in order to solve the above problem, the enable signal applied to the output buffer during the data high driving is relatively delayed compared to the data low driving so that the rising transition and the falling transition at the VREF level intersect with each other.

However, since this method is controlled by timing, the relative delay value set by the process variable, power supply voltage variable, and temperature variable may fluctuate. Therefore, the variation according to each condition affects the tDQSQ characteristic of the memory. There is a risk of giving.

In the high-speed synchronous semiconductor memory device, the data strobe signal DQS is used to reduce data skew. The DQS signal is output to the outside through the data strobe signal output buffer. The data strobe signal output buffer consists of a push-pull circuit controlled in three states: high impedance, high and low.

3 shows timing for describing a conventional data strobe signal in the case of burst length 8.

Referring to FIG. 3, the DQS is a preamble period (indicated by A in the figure) that remains low for a period corresponding to one cycle of the clock signal, and a period (indicated by B) that toggles in phase with the clock signal. ), And a postamble period (indicated by C). Therefore, the period driven in the low state compared to the intervals B and C falls to a relatively lower state during the long A period. Therefore, since the first rising transition time is delayed, the pulse width W1 is formed relatively narrower than other pulse widths W2.

Therefore, in the memory controller that inputs data in synchronization with the data strobe signal, the width for stably inputting the data D0 becomes narrower than other data, so the signal preservation of DO is relatively inferior.

An object of the present invention is to provide a pre-emphasis output buffer having a pre-emphasis characteristics in order to improve the signal retention in order to solve the problems of the prior art.

Another object of the present invention is to provide a pre-emphasis data strobe output buffer for improving signal retention of a data strobe signal of a semiconductor memory device.

Another object of the present invention is to provide a semiconductor memory device including an output buffer having a pre-emphasis function.

Another object of the present invention is to provide a data output driving method of a semiconductor memory device.

Another object of the present invention is to provide a data strobe signal output driving method of a semiconductor memory device.

In order to achieve the above object, the pre-emphasis output buffer of the present invention includes an output terminal connected to the other end of a transmission line having a pull-up termination resistor connected to one end, and the output terminal pulled up to a first power supply voltage in response to output data; And a pull-down driving unit for pre-emphasizing the pull-down driving initial stage of the output terminal in response to the output data.

The output buffer of the present invention includes a pull-up element comprising a PMOS transistor having a first junction width to which a source and a drain are respectively connected between a first power supply voltage and the output terminal, and the output data is applied to a gate, and a second power supply. A source and a drain are connected between a voltage and the output terminal, respectively, and a pull-down element composed of an NMOS transistor having the first junction width to which the output data is applied to a gate, and the pull-down driving unit pulls down the output terminal. A second junction that detects a tip of an output data signal, a source and a drain are respectively connected between a second power supply voltage and the output terminal, and a tip detection signal is applied to a gate and is wider than the first junction width; It is preferable to comprise the NMOS transistor having a width.

In addition, in the present invention, the NMOS transistor having a wide junction width is configured as a design specification of the NMOS transistor for protecting the static electricity, which can prevent an increase in input capacitance, and the tDQSQ (between the output signal of the plurality of output terminals and the RDQS signal). Skew) characteristics can be obtained.

The active period of the tip detection signal of the tip detection section of the present invention preferably has an active period to compensate for the pull-down delay of the output terminal by the pull-up termination resistor so as to follow the pull-up speed.

The pre-emphasis data strobe signal output buffer of the present invention includes a data strobe signal output terminal and a data strobe signal output terminal in response to a data strobe up and down drive signal to provide a data strobe signal to the output terminal. And a pre-emphasis unit for pre-emphasizing the data strobe signal output terminal in the preamble section of the data strobe signal. Here, the pre-emphasis unit is preferably pre-emphasized for the last 0.5 cycles of one cycle of the preamble period. Pre-emphasis control signal generation unit for generating a pre-emphasis control signal that is active during the second half of the preamble period by combining the preamble signal and the clock signal, the pre-emphasis control signal and the data strobe up And a preemphasis driver configured to pull up the data strobe signal output terminal in response to a down signal. The pull-up driving capability of the pre-emphasis driver is designed to be relatively small compared to the pull-down driving capability of the output driver to increase the level drop due to the difference (0.5 cycles) of the preamble driving period compared to the pull-down driving capability of the output driver. desirable.

The semiconductor memory device of the present invention includes a memory cell array, at least one output terminal connected to the other end of a transmission line having a pull-up termination resistor external to a chip, and the at least one output in response to data read from the memory cell array. At least one pre-emphasis data output buffer for pulling up a terminal to a first power supply voltage or a pull-down to a second power supply voltage and preemphasizing the initial pull-down driving of the at least one output terminal in response to the read data; It includes.

The semiconductor memory device may drive a data strobe signal generator, an output terminal for outputting a data strobe signal, and a data strobe signal generated from the data strobe signal generator to the second output terminal. It is preferable to further include a preemphasis data strobe signal output buffer for preemphasizing the preamble section.

The output driving method of the semiconductor memory device of the present invention detects the leading end of the data signal read out from the memory cell array to generate the leading detection signal, and simultaneously pulls down the data output terminal by the data signal in synchronization with the clock signal. In response to the detected tip detection signal, the data output terminal is pre-emphasized at the beginning of the pull-down driving of the data output terminal.

In addition, the driving method of the present invention generates a data strobe signal in synchronization with a data read operation of a memory cell array, generates a preemphasis control signal corresponding to a preamble section of the data strobe signal, and synchronizes the data in synchronization with a clock signal. The data strobe signal output terminal is driven by the strobe signal and the data strobe signal output terminal is pre-emphasized at the time of preamble driving of the data strobe signal output terminal in response to a preemphasis control signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This embodiment is described in sufficient detail to enable those skilled in the art to practice the invention.

4 shows a block diagram of a semiconductor memory device according to the present invention.

Referring to FIG. 4, the semiconductor memory device 300 is an address buffer 310, a row decoder 320, a column decoder 330, a memory cell array 340, and a timing controller in a synchronous GDDR (Graphic Double Data Rate) SDRAM. 350, an input buffer 360, an output buffer 370, a latency controller 380, a data strobe signal generator 390, and a DLL 395.

The address buffer 310 buffers the external address signal ADDR in synchronization with the clock signal CK and provides the buffered address signal to the row decoder 320 and the column decoder 330. In addition, an address signal including mode set information to be stored in the mode set register MSR included in the timing controller 350 is provided.

The input buffer 360 buffers the input data input through the input / output terminal PAD1 to the memory cell array 340 in response to the internal clock signal. Herein, a data input register is not shown between the input buffer 360 and the memory cell array 340. The data input register operates in response to an input / output control signal generated in response to the write enable signal and the data masking signal.

The output buffer 370 has a pre-emphasis function and receives data read from the memory cell array 340 and outputs the data to the input / output terminal PAD1 in response to an internal clock signal and an output control signal. The prefetch circuit is not shown between the output buffer 370 and the memory cell array 340.

The latency controller 380 receives a signal corresponding to the latency information and burst length information set in the MSR and a read command signal from the timing controller 350 to generate a latency control signal. The generated latency control signal is provided to the column decoder 330, the output buffer 370, and the data strobe signal output buffer 390.

The data strobe signal output buffer 380 outputs the pre-emphasized data strobe signal DQS to the data strobe output terminal PAD2 in response to the latency control signal and the internal clock signal.

The DLL 395 inputs an external clock signal to generate an internal clock signal.

The timing controller 350 may externally include a clock signal CK, a clock enable signal CKE, a chip select signal CS, a low strobe signal RAS, a column strobe signal CAS, and a write enable signal WE. And the like to decode the command and generate internal control signals for performing the decoded command. The timing controller 350 includes a programming register, that is, a mode set register (MSR), stores mode set information provided as an address signal, and generates an associated mode set signal.

Accordingly, the semiconductor memory device may have given column latency information, for example, CL = 2, 3, 4, 5, 6, 7, --- and burst length information, for example, BL = 2, 4, 8, 16 during a data read operation. Generates a data strobe signal in response to, ---. Next, a preemphasis control signal corresponding to the preamble section of the data strobe signal is generated, and the data strobe signal output terminal is driven by the data strobe signal in synchronization with the clock signal. At the same time, in response to the preemphasis control signal, the data strobe signal output terminal is preemphasized when the data strobe signal output terminal is preamble driven.

On the other hand, the pre-emphasis data output buffer detects the leading end of the data signal read out from the memory cell array to generate the leading detection signal, and detects the detected leading edge when the data output terminal is pulled-down driven by the data signal in synchronization with the clock signal. In response to the signal, the data output terminal is pre-emphasized at the beginning of the pull-down driving of the data output terminal.

Hereinafter, the pre-emphasis data output buffer and the pre-emphasis data strobe signal output buffer will be described in detail.

<Pre-emphasis data output buffer>

FIG. 5 illustrates a preferred embodiment of the pre-emphasis data output buffer of FIG. 4.

Referring to FIG. 4, the output buffer 370 includes a buffer 372 and a pull-down driver 374. The buffer 372 is composed of a pull-up transistor PUD and a pull-down transistor PDD. In the pull-up transistor PUD, a source is connected to a power supply voltage VDDQ, a drain is connected to an output terminal 380, and a data signal DATA is applied to a gate. In the pull-down transistor PDD, a source is connected to the ground voltage VSSQ, a drain is connected to the output terminal 380, and a data signal DATA is applied to the gate.

The pull-down driver 374 includes a sub pull-down transistor SPDD and a tip detector DET. The sub pull-down transistor SPDD has a drain connected to the output terminal 380, a source connected to the ground voltage VSSQ, and a front detection signal FEDG applied to the gate.

Compared to the pull-up transistor PUD and the pull-down transistor PDD, the sub pull-down transistor SPDD is composed of a wide transistor. Preferably, designing with a large transistor having a size of an electrostatic protection transistor can prevent an increase in input capacitance. Therefore, desired tDQSQ characteristics can be obtained.

6 illustrates an example of the front end detector of FIG. 5. The front end detector DET of FIG. 6 includes a delay unit DLY, a negative exclusive OR gate G1, and an AND gate G2 that input a data signal DATA and delay a predetermined time.

The negative exclusive OR gate G1 detects a section in which the delayed signal DDATA and the data signal DATA coincide with each other to detect the rising edge and the falling edge of the data signal DATA to generate the edge detection signal EDGE. do. The AND gate G2 combines the edge detection signal EDGE and the data signal DATA to pass only the leading end signal of the edge detection signal and blocks the trailing end signal to generate the leading detection signal FEDG.

Referring to FIG. 7, the data signal DTAT OR DTATB is applied to the output buffer 370 and is also applied to the front end detector DET. The tip detection unit DET detects the tip detection signal FEDG in response to the rising edge of the data signal DATA. The detected signal is applied to the gate of the sub pull down transistor SPDD. The sub pulldown transistor starts to turn on. At the same time, the pull-down transistor PDD starts to turn on in response to the rising edge of the data signal DATA. At this time, the pull-up transistor PUD starts to be turned off. Therefore, the voltage level of the output terminal 380 starts to fall from the VDDQ level.

During the active period of the tip detection signal FEDG, the pull-down transistor PDD and the sub pull-down transistor SPDD are turned on at the same time, so that the potential of the output terminal is quickly decreased.

When the front end detection signal FEDG is non-active, the sub pull-down transistor SPDD is turned off, so that the output terminal 380 is driven to the ground voltage VSSQ only by the pull-down transistor PDD to fall to the VOL level.

That is, in the present invention, in response to the rising transition of the data signal DATA, the pull-down driving capability is increased by the two pull-down transistors PDD and SPDD so that the level of the output signal quickly falls to the VREF level. Therefore, as shown in FIG. 7, as shown by B, the rising transition and the falling transition of the output signal DQ or DQB cross each other at the VREF level so that skew is not generated.

8A and 8B are waveform diagrams comparing an eye pattern of an output buffer of a pre-emphasis structure and an output buffer of a conventional structure according to the present invention. The vertical axis represents the voltage level, and the horizontal axis represents the operation timing. That is, in the drawing, it can be seen that the width of the eye pattern of the output buffer of the pre-emphasis structure is 251 ps, and the width of the eye pattern of the conventional structure is 36 ps compared to 215 ps. This improvement improves signal integrity.

<Pre-emphasis data strobe output buffer>

Unlike the data signal, the data strobe signal has a regular waveform so that the preemphasis operation can be preset. Therefore, it is configured differently from the preemphasis configuration of the data output buffer.

FIG. 9 illustrates a configuration of a pre-emphasis data strobe signal output buffer according to the present invention, FIG. 10 is a detailed circuit diagram of the drivers of FIG. 9, and FIG. 11 is a waveform of each part of FIGS. 9 and 10 in the case of a burst length 8. Shows a figure.

Referring to the drawing, the DQS output buffer 390 includes a DQS multiplexer 392, a DQS driver 394, a preemphasis control signal generator 396, and a preemphasis driver 398.

The DQS multiplexer 392 is the pull-up drive signal PUD and the pull-down drive signal PDD from the internal clock signal CLK in response to the tri-state control signal PTRST and the preamble signal PRMBL provided from the latency controller 380. It consists of a logic combination circuit that generates. As shown in FIG. 11, the three-state control signal PTRST maintains a high state in the DQS signal section and a low state in the remaining sections. As shown in FIG. 11, the preamble signal PRMBL maintains a high state for one cycle of the internal clock signal CLK signal and maintains a low state for the remaining periods. Accordingly, the PUD signal is composed of a signal having the same phase as four cycles of the internal clock signal, and the remaining section is kept low. The PDD signal is combined with 4.5 cycles of the preamble signal and the internal clock signal, and the remaining section is kept high.

The DQS driver 394 includes inverters G3 and G4, a pullup transistor PM1, and a pulldown transistor NM1. The DQS driver 394 outputs the DQS signal to the output terminal PAD2 in response to the pull-up drive signal PUD and the pull-down drive signal PDD.

The preemphasis control signal generator 396 generates a preemphasis control signal PRMPS by combining the preamble signal PRMBL and the internal clock signal CLK. As shown in FIG. 11, the pre-emphasis control signal PRMPS remains high for the second half cycle of the preamble section (one cycle of CLK) and remains low for the remaining sections.

The pre-emphasis driver 398 includes inverters G5, G7 and G8, NAND gate G6, Noah gate G9, pull-up transistor PM2, and pull-down transistor NM2. The size of PM2 and NM2 is preferably designed to be relatively small to raise the level drop due to the difference in driving period (0.5 cycles) compared to the sizes of PM1 and NM1 (channel width / channel length). The pull-up transistor PM2 is turned on only in the high section of the PRMPS signal. The pull-down transistor NM2 remains turned off. Accordingly, since the spring emphasizing driver 398 is pulled up only in the high section of the PRMPS signal, the DQS signal is pre-emphasized during the second half cycle of the preamble section of the DQS so that the low level is slightly increased.

Therefore, as shown in Fig. 11, the first rising edge occurs as fast as the level of the low state (solid line display) is pre-emphasized in the second half cycle of the preamble section compared with the conventional method of the dotted line display, so that the subsequent It operates under the same conditions as the rising edge.

Therefore, the signal retention of the first data D0 is improved as compared with the conventional method.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, in the present invention, the push-pull output buffer driving the transmission line to which the VDDQ termination resistor is connected increases the pull-down driving capability to increase the falling transition speed of the output signal, thereby eliminating the skew of the rising transition and the falling transition.

In addition, by pre-emphasizing the preamble section of the DQS signal, it is possible to improve the signal retention by improving the operation of the first rising edge of the DQS.

Claims (14)

An output terminal connected to the other end of the transmission line to which the pull-up terminating resistor is connected at one end; A buffer which pulls up the output terminal to the first power supply voltage or pulls down the second power supply voltage in response to output data; And a pull-down driving unit for preemphasizing the initial pull-down driving of the output terminal in response to the output data. The method of claim 1, wherein the buffer is A PMOS transistor having a first junction width to which a source and a drain are respectively connected between the first power supply voltage and the output terminal and to which the output data is applied to a gate; And A source and a drain are respectively connected between the second power supply voltage and the output terminal, and an NMOS transistor having the first junction width to which the output data is applied to a gate; The pull-down drive unit A tip detector detecting a tip of an output data signal for driving the output terminal down; And A source and a drain are respectively connected between the second power supply voltage and the output terminal, and a front end detection signal is applied to a gate, and the NMOS transistor has a second junction width wider than the first junction width. Data output buffer. The data output buffer according to claim 2, wherein the NMOS transistor having a wide junction width is formed of an NMOS transistor for static electricity protection. The method of claim 1, wherein the active period of the tip detection signal is And an active period sufficient to compensate for the pull-down delay of the output terminal by the pull-up termination resistor. Data strobe signal output terminal; An output driver for pulling up the data strobe signal output terminal to a first power supply voltage or a second power supply voltage in response to a data strobe up and down drive signal to provide a data strobe signal to the output terminal; And a pre-emphasis unit for pre-emphasizing the data strobe signal output terminal in the preamble section of the data strobe signal. The method of claim 5, wherein the pre-emphasis unit Pre-emphasis data strobe signal output buffer for pre-emphasis for the last 0.5 cycles of one cycle of the preamble period. The method of claim 5, wherein the pre-emphasis unit A preemphasis control signal generator for combining the preamble signal and the clock signal to generate a preemphasis control signal that is activated during the second half of the preamble period; And And a preemphasis driver configured to pull up the data strobe signal output terminal in response to the preemphasis control signal and the data strobe up and down signals. The pull-up driving capability of the pre-emphasis driver is as follows. Pre-emphasis data strobe signal output, characterized in that the relative increase compared to the pull-down driving capability of the output driver to the level down due to the difference (0.5 cycles) of the preamble driving period compared to the pull-down driving capability of the output driver buffer. Memory cell arrays; At least one output terminal connected to the other end of a transmission line to which a pull-up terminating resistor external to the chip is connected at one end; And Pull down the at least one output terminal to a first power supply voltage or pull down to a second power supply voltage in response to data read from the memory cell array, and pull down the at least one output terminal in response to the read data; And at least one preemphasis data output buffer pre-emphasizing the initial driving. Detecting a leading end of the data signal read out from the memory cell array to generate a leading detection signal; Driving a data output terminal down by the data signal in synchronization with a clock signal; And And preemphasizing the data output terminal at an initial stage of the pull-down driving of the data output terminal in response to the detected tip detection signal. Memory cell arrays; A data strobe signal generator; A first output terminal for outputting data; A second output terminal for outputting a data strobe signal; A data output buffer for driving data read from the memory cell array to the first output terminal; And a pre-emphasis data strobe signal output buffer for driving a data strobe signal generated from the data strobe signal generator to the second output terminal and pre-emphasizing a preamble section of the data strobe signal. Semiconductor memory device. Generating a data strobe signal in synchronization with a data read operation of the memory cell array; Generating a preemphasis control signal corresponding to a preamble section of the data strobe signal; Driving a data strobe signal output terminal by the data strobe signal in synchronization with a clock signal; And And pre-emphasizing the data strobe signal output terminal when the preamble driving of the data strobe signal output terminal is performed in response to the preemphasis control signal. Memory cell arrays; A data strobe signal generator for generating a data strobe signal in synchronization with a read operation of the memory cell array; A first output terminal for outputting data; A second output terminal for outputting a data strobe signal; The first output terminal is pulled up to a first power supply voltage or pulled down to a second power supply voltage in response to the data read from the memory cell array, and the pull-down driving of the at least one output terminal is performed in response to the read data. At least one preemphasis data output buffer pre-emphasizing; And And a pre-emphasis data strobe signal output buffer for driving a data strobe signal generated from the data strobe signal generator to the second output terminal and pre-emphasizing a preamble section of the data strobe signal. Memory device. Generating a data strobe signal in synchronization with a data read operation of the memory cell array; Generating a preemphasis control signal corresponding to a preamble section of the data strobe signal; Driving a data strobe signal output terminal by the data strobe signal in synchronization with a clock signal; Preemphasizing the data strobe signal output terminal during the preamble driving of the data strobe signal output terminal in response to the preemphasis control signal; Detecting a leading end of the data signal read out from the memory cell array to generate a leading detection signal; Driving a data output terminal down by the data signal in synchronization with a clock signal; And And pre-emphasizing the data output terminal at an initial stage of pull-down driving of the data output terminal in response to the detected front end detection signal.

Images