KR20060040597A - Result partitioning within simd data processing systems - Google Patents

Abstract

Within a processor (2) providing single instruction multiple data (SIMD) type operation, single data processing instructions can serve to control processing logic (4, 6, 8, 10) to perform SIMD-type processing operations upon multiple independent input values to generate multiple independent result values having a greater data width than the corresponding input values. A repartitioner in the form of appropriately controlled multiplexers serves to partition these result data values into high order bit portions and low order bit portions that are stored into separate registers (38, 40). The required SIMD width preserved result values can be read from the desired high order (38) result register or low order result register (40) without further processing being required. Furthermore, the preservation of the full result facilitates improvements in accuracy, such as over extended accumulate operations and the like.

Description

Splitting results within a single command multiple data processing system {RESULT PARTITIONING WITHIN SIMD DATA PROCESSING SYSTEMS}

The present invention relates to a data processing system. More particularly, the present invention relates to the partitioning of results comprising multiple result data values within a data processing system of single instruction multiple data (SIMD).

Data processing systems with a single instruction plural data function are known. In such systems, registers typically contain a plurality of independent data values to be manipulated. For example, a 32-bit register may contain two independent 16-bit data values, which may be added separately, for example, for two other 16-bit data values stored in another 32-bit register. , Multiplied, or otherwise combined. Such SIMD operations are common in the field of digital signal processing and have many advantages, including increased processing speed and reduced code density.

An example of a known SIMD technology is the MMX instruction of an Intel processor manufactured by Intel Corporation. The MMX instruction includes instructions to multiply two registers, each containing four 16-bit data values. Multiplying the 16-bit data value by another 16-bit data value results in a 32-bit data value. Thus, multiplying the four pairs of 16-bit data values specified in the MMX SIMD instruction together results in four 32-bit result data values. In many cases, it is desirable to preserve the SIMD format and data size when performing these operations. To this end, the MMX instruction includes instructions in the form of four 16-bit result data values in which the result obtained in the above case will be the 16 most significant bits in each 32-bit result, the 16-bit values being single Combined into 64-bit registers, i.e., the result of the SIMD scheme. Alternatively, it is also possible to have separate instructions that produce four least significant 16-bits in the multiplication result as output combined in a 64-bit register.

An apparatus provided according to one aspect of the present invention, wherein an apparatus for performing a data processing operation in response to a data processing instruction includes:

Processing logic for generating each of a plurality of result data values from a plurality of independent data values stored in one or more input storages in response to the data processing command;

A result divider for storing an upper bit portion of each result data value in an upper result storage section and a lower bit portion of each result data value in a lower result storage section in response to the data processing command;

It includes.

As will be appreciated by the present invention, in many cases it may be desirable to produce results in SIMD format, but in some cases it is important to maintain the accuracy of the results completely in order to avoid adverse consequences such as inappropriate rounding errors. Thus, the present technology forms a dense code in response to a single data processing instruction, and executes a SIMD format operation on a plurality of independent data values, so that the SIMD has an upper portion in one storage portion and a lower portion in another storage portion. Provides a system for storing multiple result data values in a format. Thus, the results in SIMD format can be immediately utilized without further processing if necessary, and the accuracy can be fully maintained and rounded forward since the accuracy of the results can be maintained intact in the combination of the two reservoirs and manipulated therefrom. .

It will be appreciated that the format of data processing operations performed by processing logic to generate result data values from a plurality of independent input data values may take a variety of different forms. The input to the processing logic may be the content of a single storage, resulting in the square of the stored independent data value, or the square root of the independent data value, etc., having a certain accuracy, in accordance with a predetermined calculation technique. However, in a preferred embodiment of the present invention, the processing logic is to determine each pair of independent data values from the first independent data value of the pair taken from the first input storage and the second independent data values of the pair taken from the second input storage. It is executable to multiply by.

This SIMD multiplication operation is common and increases the data width of the result which requires the present technique to be utilized if the accuracy is maintained entirely and the result of the SIMD method is still directly generated.

The technique is particularly suitable for situations where cumulative operations are associated with multiplication because the added accuracy maintained by the technique helps to eliminate the cumulative effects of multiple rounding errors that may occur in cumulative operations.

It will be appreciated that the upper and lower bit portions can have a variety of different relationships, but they are most efficient and desirable if they are contiguous and non-overlapping in the associated result data values.

The data processing instruction may specify various other forms of multiplication, such as integer multiplication or multiplication of signed decimal values. However, the present invention is particularly suitable for situations where the designated multiplication is a multiplication of a signed decimal value and the processing logic is feasible to double each result data value to take into account the presence of a sign indicating bit in each input data value. The doubling can be effectively included in other operations with less additional overhead.

The data width of the independent SIMD data values can be varied, and in a preferred embodiment, the data processing instruction specifies the relevant data width.

Multipliers can take many forms depending on the particular situation required, but a particularly preferred form is an integer multiplier that is relatively simple, fast, and capable of constructing a variety of different forms of operation in an appropriate configuration.

As an example of the type of processing operation that may be specified by a data processing instruction, the processing may be optional, such as to perform a saturation operation.

The result divider functions to divide the result data value among the other stores, and in a preferred embodiment a plurality of multiplexers are used for this. The technique can be applied to many other forms of data processing systems, such as DSPs, but is particularly suitable for use in processor cores.

Input storage, upper result storage, lower result storage, and storage in the system can take many different forms, but register bank registers, dedicated registers, buffer memory, first-in-first-out buffers and memory. It will be appreciated that one or more of some (eg cache, main, bulk, etc.). These different types of stores may be used in complex situations where different stores have different forms. When using a memory or buffer instead of a register for storage, streaming of a series of data values to be manipulated can be conveniently provided.

As a method of increasing the range of results to be calculated in a manner readily applicable to the present technology, preferred embodiments may generate one or more higher guard bits, such as those that can be used in the context of a saturation operation. These guard bits may have their own storage where the result partition stores the guard bits.

As a method provided in accordance with another aspect of the present invention, a method of performing a data processing operation in response to a data processing instruction is:

In response to the data processing instruction, generating each of a plurality of result data values from a plurality of independent data values stored in one or more input storages;

In response to the data processing instruction, storing the upper bit portion of each result data value in an upper result storage section and dividing the result data value by storing a lower bit portion of each result data value in a lower result storage section. step;

It includes.

DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments of the present invention will be described by way of example only with reference to the accompanying drawings. In the drawing,

1 schematically illustrates a processor core in a manner that may utilize the present technology;

2 schematically illustrates various SIMD data formats;

3 schematically illustrates the relationship between input data values and output data values according to the present invention for various data widths;

4 schematically illustrates a portion of a data processing path within the processor core of FIG. 1;

5 illustrates a multiplex device for dividing a result data value according to the present technology;

6 schematically illustrates another form of multiplication accumulation operation in accordance with the present technology.

1 shows a processor core 2 such as the product of ARM Limited of Cambridge, England. The processor core 2 includes a register bank 4, a multiplier 6, a shifter 8, and an adder 10 forming part of a data processing data path. The data processing instructions are received by the instruction pipeline 12, from which they are decoded by the instruction decoder 14 to generate control signals that control the operation of other circuit elements in the processor 2. While the processor 2 typically includes many additional circuit elements, it will be appreciated that these elements are not shown for brevity. In the example of FIG. 1, the input data value is read from a register in the register bank 4 and written back to the register in the register bank 4. In other embodiments, input values and result values are read and written to different types of storage, such as dedicated registers, buffer memory, first-in, first-out buffers, and general-purpose memory. They can be used as other options and in various mixed combinations. These different options are not shown in FIG. 1.

2 illustrates several different SIMD data formats. The data width of the data path shown in FIG. 1 may be 64-bit in versions of ARM processors modified to support this data width. This data path can manipulate the full length of a 64-bit word in non-SIMD mode. In this example, the various SIMD modes manipulate two 32-bit data values, four 16-bit data values, or eight 8-bit data values. In the SIMD mode, the data values are independent of each other, and the data path of the processor 2 of FIG. 1 is configured according to the size of the SIMD data value, for example, by blocking a carry chain at an appropriate location or the like, Treat these data values separately. Adaptation of data paths for performing SIMD operations is known per se and is not further described herein.

3 shows the relationship between input data values and result data values of different SIMD data width modes according to the present technology. In embodiment (i), the input data values are two 32-bit input values A0 and A1 stored in a first 64-bit register and two 32-bit input values B0 and B1 stored in a second register. Is done. In this embodiment, since the data processing operation specified by the processing instruction is a SIMD multiplication, the 32-bit value A0 is multiplied by the 32-bit value B0, and the 32-bit value A1 is the 32-bit value. Multiplied by (B1). These multiplications yield 64-bit results of A0B0 and A1B1, respectively. The most significant 32 bits of these two results are written to the upper result register 17. The least significant 32 bits of these two results are written to the lower result register 18. The two portions recorded in the different registers 17 and 18 are continuous portions that do not overlap.

Embodiments (ii) and (iii) are similar, each of which is subject to multiplication by a SIMD multiplication instruction and generates a result data value in a different register, respectively, which is either half of the total result or half of the total result. It relates to bit input values and 8-bit input values.

If it is desired to continue further processing using the result generated by the multiplication of additional SIMD type operations of the same data width, the higher result register 17 can be read directly and used as input for the further operation. have. No shifting or re-arrangement is needed to improve code density, speed, power consumption, etc. In a particularly preferred case, the upper result register 17 and the lower result register 18 are used as destinations for the cumulative operation so that the results of successive multiplications are accumulated in these registers and stored in the lower result register 18. The resulting value can be updated continuously to yield more accurate results and to avoid rounding errors. Thus, the technique allows for direct access to the correct data width value using a single command and still retains accuracy by maintaining the full data width of the result.

4 is a schematic diagram illustrating a portion of the data path of FIG. 1 in more detail. The SIMD integer multiplier 20 is supplied with two 64-bit input values obtained from each register in the register bank 4. These input values may represent a single 64-bit * 64-bit non-SIMD operation, or one of the three SIMD scheme operations described above. The SIMD multiplier 20 provides appropriate cutoff for carry chains, etc., to properly divide the independent input values and the resulting output values. The output from the SIMD multiplier 20 is a carry-on format. When the system is operating in signed fractional mode, the fractional mode, which represents the signal supplied to the multiplexers 22 and 24, is floated, such as by doubling numerical values, by compensating additional sign bits at the highest positions. Function to shift the reserve output by one bit position. The adder 26 stores the carry-preservation output from the SIMD multiplier 20, the partially accumulated value recycled from the hold and carry registers 28, 30 or the register bank 40 selected by the multiplexers 32, 34. To 128-bit values from registers (D, C). The multiplexers 32, 34 are controlled by accumulation control signals whose various values are shown in the table at the bottom of FIG. The system may be arranged to accumulate from the source register file, multiply without accumulation, accumulate to previous partial computed results, such as during vectorized operations, or bypass the register bank as a source for accumulated values.

Upon completion of the multiply and add operations in a given processing operation, the final 128-bit preservation and rounding values from registers 28 and 30 are passed to adder 36, where they are added together to result in the usual 128-bit of the result. Get a representative value. Multiplication and addition may be pipelined operations. The output of adder 36 is twice the bit width compared to the 64-bit input value from registers A and B. Thus, the SIMD result has twice the width of the independent SIMD input value. The output of adder 36 is fed to the result divider in the form of the various multiplexers shown in FIG. 5 in this embodiment.

In Fig. 5, the upper result register 38 contains a selected portion of each result value that becomes upper part. Lower result register 40 receives the corresponding lower portion of the result value. The control signals B, H, W and L indicate the SIMD data widths (bytes, half words, words and long words) used. One of these values is established at any time as "1" and the other as "0". These width specifying signals control the multiplexer shown in FIG. 5 according to the logical representation given to each adjacent multiplexer to select between the various inputs of the associated multiplexer. The overall operation of the multiplexer of FIG. 5 controlled by the control signal is selected / repartitioned between the 128 bit outputs by the adder 36, so that the upper result register 38 and the lower result as shown in another embodiment of FIG. The contents of the register 40 are formed.

The program instructions supplied to the decoder 14 of FIG. 1 to control the circuits of FIGS. 4 and 5 in the illustrated manner specify whether the data width used is a non-SIMD pre data width or one of various SIMD data widths. It has a syntax that includes parameters. The program instruction also specifies whether the accumulation is to be performed and whether the accumulation is performed using additional register values or "internal" partial results.

In addition to the two result registers 38, 40 of FIG. 5, a guard register may also be provided. This guard register is supplied with a guard bit computed from the extended version of the accumulation result. For example, if a 16-bit SIMD data value is used in a multiplication accumulating operation, the accumulator is, for example, 34 or 36 bits, depending on whether two or four guard bits are provided, such that the overflow of the accumulated value is accommodated in the guard bits. It can be greater than a bit. In this embodiment, the guard bit may be divided into separate guard bit registers, in which the guard bit register preserves the SIMD width where the lower result register provides the guard bit at the bottom of the result and the upper result register is normally needed. To provide a data value, it may be considered to provide a guard bit at the top of the result.

6 schematically illustrates providing a stacked register result with multiple cumulative operations with multiple data formats.

Registers A and B are in this case a 64-bit SIMD register holding four 16-bit quantities A0-A3 and B0-B3. The result of multiplying these registers together is a vector of four results, each of which can be up to 32 bits wide.

The four 32-bit multiplication results can be accumulated in four 32-bit values held in two different registers C and D, each holding two 32-bit amounts.

The result of the addition may be stored in registers RL and RH in a stacked format.

Claims (32)

A device for performing data processing operations in response to a data processing command: Processing logic for generating each of a plurality of result data values from a plurality of independent data values stored in one or more input storages in response to the data processing command; And a result divider for storing the upper bit part of each result data value in the upper result storage part and the lower bit part of each result data value in the lower result storage part in response to the data processing command. A device for performing data processing operations. The method of claim 1, Wherein said processing logic is executable to multiply each pair of first independent data values of a pair taken from a first input storage and an independent data value of a second independent data value of a pair taken from a second input storage. Device for performing data processing operations. The method of claim 2, The processing logic is executable to accumulate values already stored in the upper result storage section and the lower result storage section to values generated from the respective pairs of independent data values to generate the plurality of result data values. A device for performing data processing operations. The method according to claim 1, wherein And the upper bit portion and the lower bit portion of each result data value are non-overlapping consecutive portions of the result data value. The method according to claim 2, wherein Wherein said data processing instruction indicates that said independent data value is a value below a sign display decimal point, and said processing logic is executable to double each value obtained by multiplying a first independent data value by a second independent data value. A device for performing data processing operations. The method according to any of the preceding claims, Each input storage unit stores M independent N-bit data values. The method of claim 6, And the data processing instruction specifies a data width of the independent data value. The method according to claim 2, wherein And said processing logic comprises an integer multiplier operable to multiply each said pair of independent data values together. The method according to any of the preceding claims, And said processing logic is executable to perform a saturation data processing operation on said independent data value. The method according to any of the preceding claims, And the result divider comprises a plurality of multiplexers controlled according to the data processing instructions. The method according to any of the preceding claims, And said device is a processor core. The method according to any of the preceding claims, The one or more input storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; At least one of the data processing operation performing apparatus. The method according to any of the preceding claims, The upper result storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; Data processing operation performing apparatus, characterized in that one of. The method according to any of the preceding claims, The lower result storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; Data processing operation performing apparatus, characterized in that one of. The method according to any of the preceding claims, And said processing logic is operable to generate at least one higher guard bit for each result data, and said result divider is executable to store said guard bit in a guard bit storage. The method of claim 15, The guard bit storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; Data processing operation performing apparatus, characterized in that one of. As a method of performing data processing operations in response to data processing instructions: In response to the data processing instruction, generating each of a plurality of result data values from a plurality of independent data values stored in one or more input storages; In response to the data processing instruction, storing the upper bit portion of each result data value in an upper result storage section and dividing the result data value by storing a lower bit portion of each result data value in a lower result storage section. And performing a data processing operation. The method of claim 17, Wherein each pair of independent data values is multiplied together, the first independent data value of the predetermined pair is taken from the first input storage and the second independent data value of the pair is taken from the second input storage. How to perform processing operations. The method of claim 18, And the values already stored in the upper result storage section and the lower result storage section accumulate to values generated from the respective pairs of independent data values to generate the plurality of result data values. The method of claim 17, wherein And the upper and lower bit portions of each result data value are consecutive portions which are not duplicated of the result data value. The method of claim 18, wherein The data processing instruction indicates that the independent data value is a value below the sign display decimal point, and each value obtained by multiplying the second independent data value by the first independent data value is doubled. . The method of claim 17, wherein Each input storage unit stores M independent N-bit data values. The method of claim 22, And the data processing instruction designates a data width of the independent data value. The method of claim 18, wherein And wherein each pair of independent data values is executed to be multiplied together by an integer multiplier. The method of claim 17, wherein And a saturation data processing operation is performed on the independent data values. The method of claim 17, wherein And at least partially partitioning is performed by a plurality of multiplexers controlled according to the data processing instructions. The method of claim 17, wherein And wherein said method is performed in a processor core. The method of claim 17, wherein The one or more input storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; And at least one of the data processing operations. The method of claim 17, wherein The upper result storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; Data processing operation method characterized in that one of the. The method of claim 17, wherein The lower result storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; Data processing operation method characterized in that one of the. The method of claim 17 to 30, And said processing logic is executable to generate at least one higher guard bit for each result data, said result divider being executable to store said guard bit in a guard bit storage. The method of claim 31, wherein The guard bit storage unit, Register bank registers; Dedicated registers; Buffer memory; First-in, first-out buffer; And Memory; Data processing operation method characterized in that one of the.

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