KR20060039143A - Semiconductor package - Google Patents

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Publication number
KR20060039143A
KR20060039143A KR1020040088213A KR20040088213A KR20060039143A KR 20060039143 A KR20060039143 A KR 20060039143A KR 1020040088213 A KR1020040088213 A KR 1020040088213A KR 20040088213 A KR20040088213 A KR 20040088213A KR 20060039143 A KR20060039143 A KR 20060039143A
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South Korea
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lead
chip
semiconductor package
package
lower lead
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KR1020040088213A
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Korean (ko)
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이장우
목승곤
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삼성전자주식회사
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Publication of KR20060039143A publication Critical patent/KR20060039143A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 반도체 패키지에 관한 것으로, 하부리드와, 상기 하부리드에 대하여 바깥쪽으로 상향 단차지게 형성된 상부리드를 갖는 리드; 상기 하부리드 위에 부착된 제 1 칩; 상기 제 1 칩 위에 부착된 제 2 칩; 상기 제 1 칩, 제 2 칩의 본딩패드와 상기 하부리드를 전기적으로 연결하는 연결수단; 상기 상부리드의 상면과 하부리드의 하면이 외부로 노출되도록 상기 제 1 칩, 제 2 칩, 연결수단을 봉지한 수지 봉지부; 및 상기 노출된 상부리드의 상면과 하부리드의 하면에 도포된 도전성 물질을 포함하는 것을 특징으로 하는 반도체 패키지를 제공한다. 본 발명에 따른 반도체 패키지에 의하면, 하나의 패키지 안에 두개의 칩을 적층함으로써 칩의 실장밀도를 향상시킬 수 있고, 리드의 상면과 하면을 노출시킴으로써 패키지의 적층이 용이하며, 열 방출 효과를 상승시킬 수 있다.The present invention relates to a semiconductor package, comprising: a lead having a lower lead and an upper lead formed outwardly upwardly with respect to the lower lead; A first chip attached to the lower lead; A second chip attached to the first chip; Connecting means for electrically connecting the bonding pads of the first chip and the second chip and the lower lead; A resin encapsulation portion encapsulating the first chip, the second chip, and the connecting means so that the upper surface of the upper lead and the lower surface of the lower lead are exposed to the outside; And a conductive material applied to an upper surface of the exposed upper lead and a lower surface of the lower lead. According to the semiconductor package according to the present invention, by stacking two chips in one package, the mounting density of the chip can be improved, and by stacking the packages by exposing the upper and lower surfaces of the leads, the heat dissipation effect can be enhanced. Can be.

반도체 패키지, 버텀 리드 패키지, QFN 패키지, 플립칩 본딩, 와이어 본딩Semiconductor Package, Bottom Lead Package, QFN Package, Flip Chip Bonding, Wire Bonding

Description

반도체 패키지{Semiconductor Package}Semiconductor Package {Semiconductor Package}

도 1은 종래 기술에 따른 BLP(Bottom Lead Package)를 나타내는 단면도이다.1 is a cross-sectional view showing a bottom lead package (BLP) according to the prior art.

도 2는 본 발명에 따른 반도체 패키지의 제 1실시예를 나타내는 단면도이다.2 is a cross-sectional view showing a first embodiment of a semiconductor package according to the present invention.

도 3은 본 발명에 따른 반도체 패키지의 제 2실시예를 나타내는 단면도이다.3 is a cross-sectional view showing a second embodiment of a semiconductor package according to the present invention.

도 4는 본 발명에 따른 반도체 패키지의 제 3실시예를 나타내는 단면도이다.4 is a cross-sectional view showing a third embodiment of a semiconductor package according to the present invention.

<도면의 주요부분에 대한 간단한 설명><Brief description of the main parts of the drawing>

11, 111; 리드 13, 113; 칩11, 111; Read 13, 113; chip

14, 114; 접착부재 15, 115; 본딩 와이어14, 114; Adhesive members 15 and 115; Bonding wire

117; 도전성 범프 18, 118; 도전성 물질117; Conductive bumps 18, 118; Conductive material

19, 119; 수지 봉지부19, 119; Resin bag

본 발명은 반도체 패키지에 관한 것으로서, 보다 구체적으로는 상부와 하부가 이중 절곡된 리드에 칩을 적층하고 리드의 상면과 하면이 노출되도록 수지 봉지함으로써 칩의 실장밀도를 높이고 열방출 효과를 상승시키며, 다수의 패키지를 적층할 수 있는 구조의 반도체 패키지에 관한 것이다. The present invention relates to a semiconductor package, and more particularly, by stacking a chip on a double bent upper and lower leads and encapsulating the resin to expose the upper and lower surfaces of the lead, thereby increasing the mounting density of the chip and increasing the heat dissipation effect. The present invention relates to a semiconductor package having a structure in which a plurality of packages can be stacked.                         

BLP(Bottom Lead Package)는 종래 반도체 패키지 중 외부로의 전기적 연결과 열전달 경로가 되는 아웃리드를 배제하고, 리드의 하면이 외부로 노출되도록 봉지하여 버텀(Bottom)면에 노출되는 리드를 통해 외부와의 연결이 가능한 구조를 가지고 있다. 최근 QF(Quad Flat)형 패키지도 패키지의 크기를 줄이기 위하여 이러한 구조를 취하고 있으며, 아웃리드가 형성되어 있지 않다고 하여 QFN(Quad Flat Non-Leaded) 패키지라고도 한다.BLP (Bottom Lead Package) excludes outlead that is an electrical connection and heat transfer path to the outside of the conventional semiconductor package, and encapsulates the lower surface of the lead to be exposed to the outside and leads to the outside through the lead exposed to the bottom surface. It has a structure that can be connected. Recently, quad flat (QF) packages have such a structure in order to reduce the size of the package, and because they do not have an outlead, they are also called quad flat non-leaded (QFN) packages.

종래 기술에 따른 BLP의 일 실시예가 도 1에 도시되어 있다. 도 1을 참조하면, 리드(11)는 일정한 높이차를 가지고 상부(이하 상부리드라 함;11b)와 하부(이하 하부리드라함;11a)가 서로 반대 방향을 향하도록 이중 절곡된 구조를 갖는다. 즉 상부리드는 바깥쪽을 향하여 수평하게 절곡되어 있으며 하부리드는 내부를 향하여 수평하게 절곡되어 있다.One embodiment of a BLP according to the prior art is shown in FIG. 1. Referring to FIG. 1, the lid 11 has a constant height difference and has a double bent structure so that the upper portion (hereinafter referred to as upper lid 11b) and the lower portion (hereinafter referred to as lower lid 11a) face each other in opposite directions. That is, the upper lead is bent horizontally outward and the lower lead is bent horizontally toward the inside.

칩(13)은 하부리드(11a) 위에 접착부재(14)에 의하여 부착되어 있으며, 칩(13)의 본딩 패드(도시되어 있지 않음)와 상부리드(11b)의 상면은 본딩 와이어(15)에 의하여 전기적으로 연결되어 있다.The chip 13 is attached to the lower lead 11a by an adhesive member 14, and a bonding pad (not shown) of the chip 13 and an upper surface of the upper lead 11b are attached to the bonding wire 15. Is electrically connected.

하부리드(11a)의 하면은 외부로 노출되고 상부리드(11b)는 내설(內設)되도록 칩(13), 리드(11), 본딩 와이어(15)를 봉지한 수지 봉지부(19)가 형성되며, 외부로 노출된 하부리드(11a)의 하면에는 외부와의 전기적 연결을 위한 솔더와 같은 도전성 물질(18)이 도포되어 있다.The resin encapsulation portion 19 encapsulating the chip 13, the lead 11, and the bonding wire 15 is formed so that the lower surface of the lower lead 11a is exposed to the outside and the upper lead 11b is insulated. The lower surface of the lower lead 11a exposed to the outside is coated with a conductive material 18 such as solder for electrical connection with the outside.

이와 같은 종래 기술에 따른 버텀 리드 패키지는 패키지 크기를 줄이기 위해 아웃리드를 배제함으로로써 외부로 노출되는 리드의 단면적이 감소하여 열방출 효 과가 줄어드는 문제가 있었다.The bottom lead package according to the related art has a problem in that the cross-sectional area of the lead exposed to the outside is reduced by eliminating the outlead to reduce the package size, thereby reducing the heat dissipation effect.

그리고 리드의 하면만이 외부로 노출되어 패키지의 적층이 용이치 못한 어려움이 있었다.And only the bottom of the lid is exposed to the outside, there was a difficulty in stacking the package.

본 발명의 제 1목적은 상부리드의 상면과 하부리드의 하면을 모두 외부로 노출시킴으로써 열방출 효과를 상승시킨 반도체 패키지를 제공하는데 있다.A first object of the present invention is to provide a semiconductor package in which the heat dissipation effect is enhanced by exposing both the upper surface of the upper lead and the lower surface of the lower lead to the outside.

본 발명의 제 2목적은 노출된 리드의 상면과 하면이 모두 외부와 연결가능하도록 함으로써 반도체 패키지를 적층시키기에 용이한 구조를 갖는 반도체 패키지를 제공하는데 있다.A second object of the present invention is to provide a semiconductor package having a structure that is easy to stack semiconductor packages by allowing both the upper and lower surfaces of the exposed leads to be connected to the outside.

본 발명의 제 3목적은 하나의 패키지 안에 두개의 칩을 적층함으로써 실장밀도가 높은 반도체 패키지를 제공하는데 있다.A third object of the present invention is to provide a semiconductor package having high mounting density by stacking two chips in one package.

이와 같은 목적 달성을 위하여 본 발명은, 하부리드와, 상기 하부리드에 대하여 바깥쪽으로 상향 단차지게 형성된 상부리드를 갖는 리드; 상기 하부리드 위에 부착된 제 1 칩; 상기 제 1 칩 위에 부착된 제 2 칩; 상기 제 1 칩, 제 2 칩의 본딩패드와 상기 하부리드를 전기적으로 연결하는 연결수단; 및 상기 상부리드의 상면과 하부리드의 하면이 외부로 노출되도록 상기 제 1 칩, 제 2 칩, 연결수단을 봉지한 수지 봉지부를 포함하며, 상기 노출된 상부리드의 상면과 하부리드의 하면에 도전성 물질이 도포된 것을 특징으로 하는 반도체 패키지를 제공한다.In order to achieve the above object, the present invention, a lead having a lower lead, and an upper lead formed to step outwardly with respect to the lower lead; A first chip attached to the lower lead; A second chip attached to the first chip; Connecting means for electrically connecting the bonding pads of the first chip and the second chip and the lower lead; And a resin encapsulation portion encapsulating the first chip, the second chip, and the connecting means so that the upper surface of the upper lead and the lower surface of the lower lead are exposed to the outside, and conductive on the upper surface of the exposed upper lead and the lower surface of the lower lead. It provides a semiconductor package characterized in that the material is applied.

본 발명에 따른 반도체 패키지에 있어서 연결수단은 제 1 칩을 하부리드에 플립칩 본딩시키는 도전성 범프와, 제 2 칩과 하부리드를 연결하는 본딩 와이어를 포함하는 것을 특징으로 한다.In the semiconductor package according to the present invention, the connecting means includes a conductive bump for flip chip bonding the first chip to the lower lead and a bonding wire for connecting the second chip and the lower lead.

본 발명에 따른 반도체 패키지에 있어서 또 다른 연결 수단은 제 1 칩과 하부리드를 연결하는 제 1 본딩 와이어와, 제 2 칩과 하부리드를 연결하는 제 2 본딩와이어를 포함하는 것을 특징으로 한다.Another connecting means in the semiconductor package according to the present invention is characterized in that it comprises a first bonding wire for connecting the first chip and the lower lead, and a second bonding wire for connecting the second chip and the lower lead.

본 발명에 따른 반도체 패키지는 상부리드의 상면과 하부리드의 하면이 노출된 단일 반도체 패키지를 상부리드의 상면은 상면끼리 하부리드의 하면은 하면끼리 접촉되게 부착하여 상하로 적층한 것을 특징으로 한다.The semiconductor package according to the present invention is characterized in that the upper surface of the upper lead and the lower surface of the lower lead is exposed, and the upper surface of the upper lead is attached to the upper surface and the lower surface of the lower lead to be in contact with the lower surface and stacked up and down.

이하 본 발명에 따른 반도체 패키지의 실시예를 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, an embodiment of a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체 패키지의 제 1실시예를 나타내는 단면도이다. 도 2를 참조하면, 본 발명의 제 1실시예에 따른 반도체 패키지(100)는 상부와 하부가 반대 방향을 향하도록 이중 절곡된 리드(111)에 제 1 칩(113a)과 제 2 칩(113b)이 적층되고, 제 1 칩(113a)은 플립칩 본딩(Filp Chip Bonding)에 의해, 제 2 칩(113b)은 와이어 본딩에 의해 리드(111)와 전기적으로 연결된 구조를 갖는다.2 is a cross-sectional view showing a first embodiment of a semiconductor package according to the present invention. Referring to FIG. 2, in the semiconductor package 100 according to the first embodiment of the present invention, the first chip 113a and the second chip 113b are formed on the lead 111 that is double bent so that the top and the bottom thereof face in opposite directions. ) Is stacked, and the first chip 113a is electrically connected to the lead 111 by wire chip bonding, and the second chip 113b is electrically connected to the lead 111 by wire bonding.

리드(111)는 바깥쪽으로 수평하게 절곡 형성된 상부리드(111b)와 안쪽으로 수평하게 절곡 형성된 하부리드(111a)로 이루어져 있으며, 상부리드(111b)는 하부리드(111a)에 대해서 상향 단차지게 형성되어 있다.The lead 111 is composed of an upper lead 111b formed horizontally bent outward and a lower lead 111a formed horizontally bent inward, and the upper lead 111b is formed to be stepped upward with respect to the lower lead 111a. have.

본딩 패드(도시되어 있지 않음)에 도전성 범프(Bump;117)가 형성된 제 1 칩(113a)은 하부리드(111a) 위에 플립칩 본딩되어 있다. The first chip 113a having the conductive bump 117 formed on the bonding pad (not shown) is flip chip bonded on the lower lead 111a.                     

제 2 칩(113b)은 제 1 칩(113a)의 비활성면에 접착부재(114)에 의하여 부착되며, 제 2 칩(113b)의 활성면이 위를 향하도록 부착되어 있다. 접착부재(114)은 필름 타입의 접착제를 사용하는 것이 바람직하나 절연성을 갖는 접착물질이라면 어느것이라도 무방하며, 패키지의 두께를 줄이기 위해 접착부재(114)은 가능한 얇게 형성되는 것이 바람직하다. The second chip 113b is attached to the inactive surface of the first chip 113a by the adhesive member 114, and the active surface of the second chip 113b is attached upward. The adhesive member 114 is preferably a film-type adhesive, but may be any adhesive material having an insulating property, the adhesive member 114 is preferably formed as thin as possible to reduce the thickness of the package.

제 2 칩(113b)의 본딩 패드와 하부리드(111a)는 본딩 와이어(115)에 의하여 전기적으로 연결된다. 이 때 본딩 와이어(115)는 수지 봉지부(119) 형성 후에도 외부로 노출되지 않도록, 상부리드(111b)의 상면보다 아래쪽에 형성된다.The bonding pads of the second chip 113b and the lower leads 111a are electrically connected by the bonding wires 115. At this time, the bonding wire 115 is formed below the upper surface of the upper lead 111b so as not to be exposed to the outside even after the resin encapsulation 119 is formed.

제 1 칩(113a)과 제 2 칩(113b), 본딩 와이어(115)를 보호하기 위하여 상부리드(111b)의 상면과 하부리드(111a)의 하면이 외부로 노출되도록 수지 봉지부(119)가 형성되며, 노출된 상부리드(111b)의 상면과 하부리드(111a)의 하면에는 패키지 적층 및 외부로의 전기적 신호 전달이 가능하도록 솔더와 같은 도전성 물질(118a, 118b)이 도포된다.In order to protect the first chip 113a, the second chip 113b, and the bonding wire 115, the resin encapsulation part 119 is disposed such that the upper surface of the upper lead 111b and the lower surface of the lower lead 111a are exposed to the outside. Conductive materials 118a and 118b, such as solder, are coated on the upper surface of the exposed upper lead 111b and the lower surface of the lower lead 111a to allow package stacking and electrical signal transmission to the outside.

도 3는 본 발명에 따른 반도체 패키지의 제 2실시예를 나타내는 단면도이다. 도 3을 참조하면, 본 발명의 제 2실시예에 따른 반도체 패키지(200)는 상부와 하부가 반대 방향을 향하도록 이중 절곡된 리드(111)에 제 1 칩(113a)과 제 2 칩(113b)이 접착부재(114)에 의하여 적층되며, 제 1 칩(113a)과 제 2 칩(113b) 모두 본딩 와이어(115a, 115b)에 의해 하부리드(111a)와 전기적으로 연결된 구조를 갖는다.3 is a cross-sectional view showing a second embodiment of a semiconductor package according to the present invention. Referring to FIG. 3, the semiconductor package 200 according to the second exemplary embodiment of the present invention may include a first chip 113a and a second chip 113b in a lead 111 that is double bent so that upper and lower sides thereof face in opposite directions. ) Is stacked by the adhesive member 114, and both the first chip 113a and the second chip 113b have a structure electrically connected to the lower lead 111a by the bonding wires 115a and 115b.

제 1 칩(113a)은 하부리드(111a) 위에 접착부재(114)에 의하여 부착되어 있으며, 제 1 칩(113a)의 본딩 패드와 하부리드(111a)는 본딩 와이어(115a)에 의하여 전기적으로 연결되어 있다. 이때 제 1 칩(113a)의 본딩 와이어(115a)는 제 1 칩(113a)과 제 2 칩(113b)의 크기가 동일할 경우에는 패키지의 두께 조절을 위하여 역와이어 본딩으로 형성하는 것이 바람직하다.The first chip 113a is attached to the lower lead 111a by the adhesive member 114, and the bonding pad and the lower lead 111a of the first chip 113a are electrically connected by the bonding wire 115a. It is. At this time, when the bonding wire 115a of the first chip 113a is the same size as the first chip 113a and the second chip 113b, the bonding wire 115a may be formed by reverse wire bonding to control the thickness of the package.

제 2 칩(113b)은 제 1 칩(113a)의 활성면에 접착부재(114)에 의하여 제 2 칩(113b)의 활성면이 위를 향하도록 부착되어 있다. 접착부재(114)은 제 1 칩(113a)의 본딩패드 사이의 영역에 형성되어 있으며, 제 1 칩(113a)의 본딩 와이어(115a)의 공간확보 및 제 2 칩(113b) 적층시 제 1 칩(113a)의 본딩 와이어(115a) 손상을 방지하기 위해 어느 정도의 높이를 가지는 것이 바람직하다. The second chip 113b is attached to the active surface of the first chip 113a so that the active surface of the second chip 113b faces upward by the adhesive member 114. The adhesive member 114 is formed in a region between the bonding pads of the first chip 113a, and secures space of the bonding wire 115a of the first chip 113a and the first chip when the second chip 113b is stacked. In order to prevent damage to the bonding wire 115a of the 113a, it is preferable to have a certain height.

그 밖의 구조는 본 발명의 제 2실시예에서 설명한 바와 동일하기 때문에 상세한 설명은 생략한다. Since other structures are the same as those described in the second embodiment of the present invention, detailed descriptions are omitted.

도 4은 본 발명에 따른 반도체 패키지의 제 3실시예를 나타내는 단면도이다. 도 4를 참조하면, 본 발명의 제 3실시예에 따른 반도체 패키지(300)는 본 발명의 제 1실시예에 따른 단일 반도체 패키지(이하 단일 패키지라 함)를 3단 적층한 구조로 이루어져 있다.4 is a cross-sectional view showing a third embodiment of a semiconductor package according to the present invention. Referring to FIG. 4, the semiconductor package 300 according to the third embodiment of the present invention has a structure in which a single semiconductor package (hereinafter, referred to as a single package) according to the first embodiment of the present invention is stacked in three layers.

제 1 단일 패키지(100) 위에 제 2 단일 패키지(100')가 제 1 단일 패키지(100)의 상부리드(111b)의 상면과 제 2 단일 패키지(100')의 상부리드(111b')의 상면이 서로 마주보도록 적층되며, 제 2 단일 패키지(100') 위에 제 3 단일 패키지(100")가 제 2 단일 패키지(100')의 하부리드(111a')의 하면과 제 3 단일 패키지(100")의 하부리드(111a")의 하면이 서로 마주보도록 적층된다.A second single package 100 'is disposed on the first single package 100, and an upper surface of the upper lead 111b of the first single package 100 and an upper surface of the upper lead 111b' of the second single package 100 '. Are stacked so as to face each other, and a third single package 100 "is disposed on the second single package 100 'and the lower surface of the lower lid 111a' of the second single package 100 'and the third single package 100". Lower surfaces of the lower leads 111a "are stacked to face each other.

각각의 단일 패키지(100,100',100")는 패키지의 상면과 하면에 도포된 도전 성 물질(118)에 의해서 서로 접착되며, 이로 인하여 제 1 단일 패키지(100), 제 2 단일 패키지(100'), 제 3 단일 패키지(100") 사이의 전기적 신호 전달이 가능해진다.Each single package 100, 100 ′, 100 ″ is bonded to each other by a conductive material 118 applied to the top and bottom surfaces of the package, thereby allowing the first single package 100 and the second single package 100 ′ to adhere to each other. The electrical signal transmission between the third single package 100 "is possible.

본 발명의 제 3 실시예에 따른 반도체 패키지(300)는 단일 패키지 3개를 적층하였으나, 이와 같은 구조로 둘 또는 넷 이상의 단일 반도체 패키지를 적층할 수 도 있으며, 단일 패키지는 제 1 실시예에 따른 반도체 패키지(100) 뿐 아니라 제 2 실시예에 따른 반도체 패키지(도 3의 200)로 이루어 질 수도 있다.In the semiconductor package 300 according to the third embodiment of the present invention, three single packages are stacked, but two or more single semiconductor packages may be stacked in such a structure, and the single package may be stacked according to the first embodiment. Not only the semiconductor package 100 but also the semiconductor package (200 of FIG. 3) according to the second embodiment may be formed.

이상에서 살펴본 바와 같이 본 발명에 의한 반도체 패키지는 상부리드의 상면과 하부리드의 하면이 모두 외부로 노출된 구조를 가지고 있어 하부리드의 하면만이 노출된 종래 버텀 리드 패키지에 비해 열방출 효과가 우수하다.As described above, the semiconductor package according to the present invention has a structure in which both the upper surface of the upper lid and the lower surface of the lower lid are exposed to the outside, so that the heat dissipation effect is superior to the conventional bottom lead package in which only the lower surface of the lower lid is exposed. Do.

또한 외부로 노출된 상부리드의 상면과 하부리드의 하면에 외부와 전기적으로 연결 가능한 도전성 물질이 도포되어 있어 다수의 패키지를 적층하는데 유리한 구조를 갖는다.In addition, a conductive material that is electrically connected to the outside is coated on the upper surface of the upper lid and the lower lid exposed to the outside, and thus has an advantageous structure for stacking a plurality of packages.

뿐만 아니라 하나의 패키지 안에 두개의 칩을 적층함으로써 칩의 실장밀도를 향상에 기여한다.In addition, by stacking two chips in one package, it contributes to the improvement of chip mounting density.

Claims (4)

하부리드와, 상기 하부리드에 대하여 바깥쪽으로 상향 단차지게 형성된 상부리드를 갖는 리드;A lead having a lower lead and an upper lead formed outwardly with respect to the lower lead; 상기 하부리드 위에 부착된 제 1 칩;A first chip attached to the lower lead; 상기 제 1 칩 위에 부착된 제 2 칩;A second chip attached to the first chip; 상기 제 1 칩, 제 2 칩의 본딩패드와 상기 하부리드를 전기적으로 연결하는 연결수단;Connecting means for electrically connecting the bonding pads of the first chip and the second chip and the lower lead; 상기 상부리드의 상면과 하부리드의 하면이 외부로 노출되도록 상기 제 1 칩, 제 2 칩, 연결수단을 봉지한 수지 봉지부; 및A resin encapsulation portion encapsulating the first chip, the second chip, and the connecting means so that the upper surface of the upper lead and the lower surface of the lower lead are exposed to the outside; And 상기 노출된 상부리드의 상면과 하부리드의 하면에 도포된 도전성 물질을 포함하는 것을 특징으로 하는 반도체 패키지.And a conductive material applied to an upper surface of the exposed upper lead and a lower surface of the lower lead. 제 1 항에 있어서, 상기 연결수단은The method of claim 1, wherein the connecting means 상기 제 1 칩을 상기 하부리드에 플립칩 본딩시키는 도전성 범프와;A conductive bump for flip chip bonding the first chip to the lower lead; 상기 제 2 칩과 상기 하부리드를 연결하는 본딩 와이어를 포함하는 것을 특징으로 하는 반도체 패키지.And a bonding wire connecting the second chip and the lower lead. 제 1 항에 있어서, 상기 연결수단은The method of claim 1, wherein the connecting means 상기 제 1 칩과 상기 하부리드를 연결하는 제 1 본딩 와이어와;A first bonding wire connecting the first chip and the lower lead; 상기 제 2 칩과 상기 하부리드를 연결하는 제 2 본딩 와이어를 포함하는 것을 특징으로 하는 반도체 패키지.And a second bonding wire connecting the second chip and the lower lead. 제 1항 내지 3 항 중 어느 한 항의 반도체 패키지를 복수개 포함하며, 상기 반도체 패키지의 노출된 상부리드의 상면은 상면끼리, 하부리드의 하면은 하면끼리 접촉되게 부착하여 상기 반도체 패키지가 상하로 적층되도록 하는 것을 특징으로 하는 반도체 패키지.The semiconductor package according to any one of claims 1 to 3, wherein the upper surface of the exposed upper lead of the semiconductor package is attached to the upper surface and the lower surface of the lower lead to be in contact with the lower surface so that the semiconductor package is stacked up and down. A semiconductor package, characterized in that.
KR1020040088213A 2004-11-02 2004-11-02 Semiconductor package KR20060039143A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008020810A1 (en) * 2006-08-18 2008-02-21 Wai Seng Chew Edge bond chip connection (ebcc)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008020810A1 (en) * 2006-08-18 2008-02-21 Wai Seng Chew Edge bond chip connection (ebcc)

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