KR20060032028A - Method of forming recess gate - Google Patents

Method of forming recess gate Download PDF

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KR20060032028A
KR20060032028A KR1020040081034A KR20040081034A KR20060032028A KR 20060032028 A KR20060032028 A KR 20060032028A KR 1020040081034 A KR1020040081034 A KR 1020040081034A KR 20040081034 A KR20040081034 A KR 20040081034A KR 20060032028 A KR20060032028 A KR 20060032028A
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polysilicon film
film
depositing
recess gate
forming
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KR1020040081034A
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Korean (ko)
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김수호
박동수
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주식회사 하이닉스반도체
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Publication of KR20060032028A publication Critical patent/KR20060032028A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 리세스 게이트 형성 방법에 관한 것으로, 본 발명의 리세스 게이트 형성과정은 소자분리막으로 활성영역이 정의된 반도체 기판상에서 활성영역의 소정부를 에칭하여 트렌치를 형성하는 단계와 상기 트렌치 상에 게이트 산화막을 증착하는 단계와 상기 산화막 위에 도핑된 폴리실리콘막을 증착하는 단계와 상기 도핑된 폴리실리콘막 위에 언도핑된 폴리실리콘막을 증착하는 단계와 상기 언도핑된 폴리실리콘막을 평탄화하는 단계를 포함하여 이루어져 폴리실리콘막 위의 워터마크를 억제하고 리프팅 결함을 막아 반도체 소자의 수율을 증가시킬 수 있는 효과가 있다. The present invention relates to a method of forming a recess gate. The process of forming a recess gate according to the present invention comprises forming a trench by etching a predetermined portion of an active region on a semiconductor substrate in which an active region is defined as an isolation layer, and forming a trench on the trench. Depositing a gate oxide film, depositing a doped polysilicon film on the oxide film, depositing an undoped polysilicon film on the doped polysilicon film, and planarizing the undoped polysilicon film. There is an effect that the yield of the semiconductor device can be increased by suppressing the watermark on the polysilicon film and preventing lifting defects.

리세스 게이트(recess gate), 워터마크(water mark), 언도핑된 폴리실리콘Recess gate, watermark, undoped polysilicon

Description

리세스 게이트 형성방법{Method of forming recess gate}Method of forming recess gate

도1a 내지 도1c는 종래의 리세스 게이트 형성 과정을 보여주는 공정 단면도이다. 1A to 1C are cross-sectional views illustrating a conventional recess gate forming process.                 

도2a 내지 도2c는 본 발명의 일실시예에 따른 리세스 게이트 형성 과정을 보여주는 공정 단면도이다. 2A to 2C are cross-sectional views illustrating a process of forming a recess gate according to an exemplary embodiment of the present invention.

***** 도면의 주요부분에 대한 부호의 설명 ***** ***** Explanation of symbols for main parts of drawing *****

10: 반도체 기판 11: 게이트 산화막 10: semiconductor substrate 11: gate oxide film

12: 선형 질화막 13: 필드 산화막12: linear nitride film 13: field oxide film

14: 필드 절연막 16: 도핑된 폴리실리콘막14: field insulating film 16: doped polysilicon film

17: 워터마크 18: 언도핑된 폴리실리콘막17: watermark 18: undoped polysilicon film

20: 실리사이드막20: silicide film

본 발명은 리세스 게이트 형성 방법에 관한 것으로, 특히 실리사이드막의 증착을 위한 사전 세정 처리 중에 폴리실리콘막 상에 워터마크가 생성되는 것을 방지하여 폴리실리콘막과 실리사이드막 사이의 리프팅 결함을 방지함으로써 반도체소자의 수율을 증가시키는 리세스 게이트 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a recess gate, and more particularly, to prevent a watermark from being generated on a polysilicon film during a pre-cleaning process for depositing a silicide film, thereby preventing lifting defects between the polysilicon film and the silicide film. A method of forming a recess gate for increasing the yield of

최근, 반도체 장치의 집적도가 높아질수록 게이트 길이가 짧아져서 SCE(short channel effect)에 의한 문턱전압(threshold voltage)의 급속저하(rolling off) 및 유효채널 길이 감소 등이 문제되고, 이를 해결하기 위해 건식식각에 의해 형성된 얕은 트랜치(shallow trench)에 게이트 전극을 형성하는 리세스 게이트(Recess Gate) 구조가 많이 연구되고 있다. Recently, as the degree of integration of semiconductor devices increases, the gate length becomes shorter, leading to problems such as a rolling off of a threshold voltage due to a short channel effect (SCE) and a reduction of an effective channel length. A recess gate structure for forming a gate electrode in a shallow trench formed by etching has been studied.                         

그런데, 이러한 리세스 게이트를 형성하는 과정 중 폴리실리콘막을 평탄화한 후 실리사이드막을 증착하는 과정에서 폴리실리콘막 상에 워터마크에 의해 반도체 수율이 감소되는 문제가 발생하고 있다. However, in the process of forming the recess gate, the semiconductor yield is reduced due to the watermark on the polysilicon layer in the process of depositing the silicide layer after planarizing the polysilicon layer.

이하 도면을 통해 상세히 살펴본다.It looks at in detail through the drawings.

도1a 내지 도1c는 종래의 리세스 게이트 형성 과정을 보여주는 공정 단면도이다. 1A to 1C are cross-sectional views illustrating a conventional recess gate forming process.

우선 도1a를 참조하면, 소자분리막으로 활성영역이 정의된 반도체 기판에서 활성 영역의 소정부를 에칭(eaching)하여 트렌치를 형성한다. 그 후 형성된 트렌치에 게이트산화막(11)을 증착하고, 그 위에 인(Phosphorous)으로 도핑된 폴리실리콘막(16)을 증착한다. 증착된 폴리실리콘막(16)은 트렌치의 형태를 반영하여 불균일한 높이로 형성되므로 CMP 공정처리 등에 의한 평탄화 작업이 필요하다.Referring to FIG. 1A, a trench is formed by etching a predetermined portion of an active region in a semiconductor substrate in which an active region is defined as an isolation layer. After that, a gate oxide film 11 is deposited on the formed trench, and a polysilicon film 16 doped with phosphorous is deposited thereon. Since the deposited polysilicon film 16 is formed to have a non-uniform height reflecting the shape of the trench, planarization work such as a CMP process is necessary.

평탄화 작업을 거치면 도1b에서 도시한 바와 같이 균일한 높이를 갖는 폴리실리콘막(16)이 형성된다. 다음으로 평탄화한 폴리실리콘막(16)위에 실리사이드막(20)을 증착하기 위해 사전 세정(pre cleaning) 처리를 한다.After the planarization operation, as shown in FIG. 1B, a polysilicon film 16 having a uniform height is formed. Next, a pre-cleaning process is performed to deposit the silicide film 20 on the planarized polysilicon film 16.

그런데 사전 세정 공정에서 도펀트(dopant)인 인(phosphorous) 성분이 폴리실리콘막(16) 표면의 그레인 경계(grain boundary)에 모여 반도체 기판의 일부지역에 도1b에서 도시한 바와 같은 워터마크(17)를 형성한다. 워터마크(17)는 일반적인 고온에서 성장시킨 게이트 산화막(11)보다 열화 되기 쉽고 강도가 낮은 물리적 성질을 갖는다. However, in the pre-cleaning process, a dopant phosphorous component gathers at a grain boundary of the surface of the polysilicon film 16 and shows a watermark 17 as shown in FIG. To form. The watermark 17 is more prone to deterioration and has a lower physical strength than the gate oxide film 11 grown at a general high temperature.

도1c를 참고하면, 워터마크(17)가 형성된 폴리실리콘막(16) 위에 실리사이드 막(20)을 증착하는 경우, 이러한 워터마크에 의해 폴리실리콘막과 실리사이드막 사이의 접합성이 감소하는 리프팅 결함(lifting defect)이 발생한다. 그 결과 저항이 증가하여 게이트전극의 동작 전압을 차단하고 반도체 소자의 수율을 저해하는 문제가 있다.Referring to FIG. 1C, when the silicide film 20 is deposited on the polysilicon film 16 on which the watermark 17 is formed, a lifting defect in which the adhesion between the polysilicon film and the silicide film is reduced by the watermark ( lifting defect) occurs. As a result, there is a problem that the resistance is increased to block the operating voltage of the gate electrode and to inhibit the yield of the semiconductor device.

본 발명은 상기와 같은 문제를 해결하기 위하여 안출된 것으로, 리세스 게이트 형성과정에서 도핑된 폴리실리콘막 상에 언도핑된 폴리실리콘막을 증착하여 실리사이드막 증착을 위한 사전 세정공정에서 워터마크가 발생하는 것을 억제함으로써 반도체소자의 수율을 증가 시키는 것을 목적으로 한다. The present invention has been made to solve the above problems, the watermark is generated in the pre-cleaning process for depositing the silicide film by depositing the undoped polysilicon film on the doped polysilicon film during the recess gate formation process It is aimed at increasing the yield of a semiconductor element by suppressing it.

상기한 목적 달성을 위해, 본 발명의 리세스 게이트 형성과정은 소자분리막으로 활성영역이 정의된 반도체 기판 상에서 활성영역의 소정부를 에칭하여 트렌치를 형성하는 단계와, 상기 트렌치 위에 게이트 산화막을 증착하는 단계와, 상기 산화막위에 도핑된 폴리실리콘막을 증착하는 단계와, 상기 도핑된 폴리실리콘막 위에 언도핑된 폴리실리콘막을 증착하는 단계와, 상기 언도핑된 폴리실리콘막을 평탄화하는 단계를 포함하여 이루어진다.In order to achieve the above object, the recess gate forming process of the present invention comprises forming a trench by etching a predetermined portion of an active region on a semiconductor substrate in which an active region is defined as an isolation layer, and depositing a gate oxide layer on the trench. And depositing a doped polysilicon film on the oxide film, depositing an undoped polysilicon film on the doped polysilicon film, and planarizing the undoped polysilicon film.

이하 도면에 따라 상기 발명의 실시예를 상세히 설명한다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 이점 및 특징, 그리고 이를 달성하는 방법은 첨부된 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라, 이 실시예들을 벗어나 다양 한 형태로 구현 가능하다. 한편, 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Advantages and features of the present invention, and a method of achieving the same will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms beyond the embodiments. In addition, like reference numerals refer to like elements throughout the specification.

도2a 내지 도2c는 본 발명의 일실시예에 따른 리세스 게이트의 형성과정을 보여주는 공정 단면도이다.2A to 2C are cross-sectional views illustrating a process of forming a recess gate according to an exemplary embodiment of the present invention.

도2a는 본 발명의 일실시예에 따른 리세스 게이트 형성 과정에서 성장시킨 폴리실리콘막 위에 언도핑된 폴리실리콘막을 증착시킨 모습을 보여주는 공정 단면도이다. FIG. 2A is a cross-sectional view illustrating a process of depositing an undoped polysilicon film on a polysilicon film grown in a recess gate formation process according to an exemplary embodiment of the present invention.

우선 활성화 영역을 구분하기 위해 필드 부분에 라이너질화막(12), 필드산화막(13)과 필드절연막(14)을 증착하여 소자분리막을 형성한다. First, a device isolation film is formed by depositing a liner nitride film 12, a field oxide film 13, and a field insulating film 14 on the field portion to distinguish the activation region.

상기 소자분리막으로 활성영역이 정의된 반도체 기판(10)에서 활성영역의 소정부에 리세스 게이트(recess gate)를 형성하기 위한 에칭(eaching) 공정을 실시하여 트렌치를 형성하고, 그 위에 게이트 산화막(11)을 증착한다. In the semiconductor substrate 10 in which the active region is defined as the isolation layer, an etching process is performed to form a recess gate in a predetermined portion of the active region, thereby forming a trench, and forming a trench thereon. 11) Deposit.

게이트산화막(11) 위에는 폴리실리콘막(16,18)을 증착하게 되는데 인(Phosphorous)으로 도핑된 폴리실리콘막(16)을 먼저 증착한 후, 그 위에 언도핑된 폴리실리콘막(18)을 증착한다. 상기 언도핑된 폴리실리콘막(18)을 증착하는 이유는 도핑된 폴리실리콘막(16)의 도펀트(dopant)인 인(Phosphorous)성분이 실리사이드막이 형성되는 폴리실리콘막의 표면위로 확산되는 것을 방지하기 위한 것이다.The polysilicon layers 16 and 18 are deposited on the gate oxide layer 11. The polysilicon layer 16 doped with phosphorous is deposited first, and then the undoped polysilicon layer 18 is deposited thereon. do. The reason for depositing the undoped polysilicon film 18 is to prevent the phosphorus component, which is a dopant of the doped polysilicon film 16, from being diffused onto the surface of the polysilicon film on which the silicide film is formed. will be.

본 발명의 일실시예에 따라 상기 도핑된 폴리실리콘(16)의 증착은 두께 300~1000Å 정도로 하고, 소스 가스의 종류를 SiH4, Si2H6, PH3로 하며, 가스의 양은 SiH4(100~3000 sccm), Si2H6(50~1500 sccm), PH3(10~500 sccm 1% PH3/SiH4 기 준)으로 하고, 압력 0.1~1.5torr와 증착온도 500~580℃로 하는 것을 공정 조건으로 한다.According to an embodiment of the present invention, the doped polysilicon 16 is deposited to a thickness of about 300 to 1000Å, the type of source gas is SiH4, Si2H6, PH3, and the amount of gas is SiH4 (100-3000 sccm), Si2H6 (50 ~ 1500 sccm) and PH3 (10 ~ 500 sccm 1% PH3 / SiH4 standard) were used, and the process conditions were set at a pressure of 0.1 to 1.5 torr and a deposition temperature of 500 to 580 ° C.

또한 본 발명의 일실시예에 따라 상기 언도핑된 폴리실리콘(18)의 증착은 두께 300~1000Å 정도로 하고, 소스 가스의 종류를 SiH4, Si2H6로 하며, 가스의 양은 SiH4(100~3000 sccm), Si2H6(50~1500 sccm)으로 하고, 압력 0.1~1.5torr와 증착온도를 500~650℃로 하는 것을 공정 조건으로 한다.In addition, the deposition of the undoped polysilicon 18 according to an embodiment of the present invention is about 300 ~ 1000Å thickness, the source gas is SiH4, Si2H6, the amount of gas SiH4 (100 ~ 3000 sccm), The process conditions are made into Si2H6 (50-1500 sccm), and the pressure of 0.1-1.5 torr and the deposition temperature to 500-650 degreeC.

도2b는 본 발명의 일실시예에 따른 리세스 게이트 형성과정에서 언도핑된 폴리실리콘막을 CMP 공정처리 한 후의 모습을 보여주는 공정 단면도이다.2B is a cross-sectional view illustrating a state after an undoped polysilicon film is subjected to a CMP process during a recess gate formation according to an embodiment of the present invention.

폴리실리콘막(16,18)을 증착한 후에는 CMP(Chemical Mechanical Polish) 공정을 사용하여 폴리실리콘막 위를 평탄화 시킨다.After the polysilicon layers 16 and 18 are deposited, the polysilicon layer is planarized by using a chemical mechanical polish (CMP) process.

CMP(Chemical Mechanical Polish)공정은 물, 실리카 연마 입자 및 수산화 칼륨 또는 아민계 화합물(amine-based agent)과 같은 첨가제를 포함하는 슬러리(slurry) 화합물을 사용하여 표면을 평탄화 하거나 단차를 줄이는데 사용된다. 슬러리(slurry) 화합물은 CMP 공정에 사용되는 연마 용액으로 기계적 연마를 위한 미세 입자가 균일하게 분산되어 있고, 연마되는 웨이퍼와의 화학적 반응을 위한 산 혹은 염기와 같은 용액을 초순수(DI water)에 분산 및 혼합시킨 용액이다.Chemical Mechanical Polish (CMP) processes are used to planarize surfaces or reduce steps by using slurry compounds that include additives such as water, silica abrasive particles, and potassium hydroxide or amine-based agents. The slurry compound is a polishing solution used in the CMP process. The fine particles for mechanical polishing are uniformly dispersed, and a solution such as an acid or a base for chemical reaction with the wafer being polished is dispersed in ultra pure water (DI water). And a mixed solution.

도2c는 본 발명의 일실시예에 따른 리세스 게이트 형성과정에서 CMP 공정처리 한 언도핑된 폴리실리콘막 위에 실리사이드막을 형성시킨 모습을 보여주는 도면이다.FIG. 2C is a view illustrating a silicide layer formed on an undoped polysilicon layer subjected to a CMP process during a recess gate formation process according to an embodiment of the present invention.

실리사이드막(20)을 언도핑된 폴리실리콘막(18) 위에 증착하기 위해서는 사 전 세정(pre cleaning) 처리가 필요하다. 사전 세정 공정에서 발생하는 워터마크는 폴리실리콘막(18)의 표면으로 확산되는 도펀트(본 발명의 일실시예의 경우 인(phosphorous) 성분)에 의해 발생한다.In order to deposit the silicide layer 20 on the undoped polysilicon layer 18, a pre-cleaning process is required. The watermark generated in the pre-cleaning process is generated by the dopant (phosphorous component in one embodiment of the present invention) diffused to the surface of the polysilicon film 18.

그러므로 본 발명의 일실시예에 의한 리세스 게이트 형성방법에서는 도핑된 폴리실리콘막(16) 위에 언도핑된 폴리실리콘막(18)을 증착하여 도펀트인 인(phosphorous) 성분 등이 표면으로 확산되는 것을 방지한다. 그 결과 폴리실리콘막(18)위로 확산되는 인(phosphorous) 성분에 의한 워터마크(17)의 발생이 억제된다. Therefore, in the method of forming a recess gate according to an exemplary embodiment of the present invention, the undoped polysilicon layer 18 is deposited on the doped polysilicon layer 16 to diffuse the dopant phosphorous component to the surface. prevent. As a result, generation of the watermark 17 due to the phosphorous component diffused onto the polysilicon film 18 is suppressed.

이때, 언도핑된 폴리실리콘막(18)은 평탄화한 후 높이가 50Å 이상이 되는 것이 바람직하다. 이는 도핑된 폴리실리콘의 인(Phosphorous)성분이 실리사이드막이 증착되는 언도핑된 폴리실리콘(18)상의 표면으로 확산되지 않게 하기 위해 필요한 최소한의 두께이다. At this time, it is preferable that the undoped polysilicon film 18 has a height of 50 kPa or more after planarization. This is the minimum thickness required to ensure that the Phosphorous component of the doped polysilicon does not diffuse to the surface on the undoped polysilicon 18 on which the silicide film is deposited.

도2c를 참고하면, 본 발명의 일실시예에 의해 형성되는 리세스 게이트에서 실리사이드막(20)은 리프팅 결함(lifting defect) 없이 언도핑된 폴리실리콘(18) 위에 균일한 두께로 평탄하게 형성된다. 그 결과 언도핑된 폴리실리콘막(18)과 그 위에 증착되는 실리사이드막(20)의 접합성이 감소에 의해 발생하는 저항증가를 막아 반도체 수율을 개선할 수 있다. Referring to FIG. 2C, in the recess gate formed by the embodiment of the present invention, the silicide layer 20 is formed to have a uniform thickness on the undoped polysilicon 18 without a lifting defect. . As a result, the semiconductor yield can be improved by preventing the increase in resistance caused by the decrease in the adhesion between the undoped polysilicon layer 18 and the silicide layer 20 deposited thereon.

본 발명의 바람직한 실시예에 의해서 실리사이드막은 WSix 또는 TiSix 금속을 사용할 수 있고, W 혹은 TiN과 같은 금속을 사용해도 무방하다.According to a preferred embodiment of the present invention, the silicide film may use WSix or TiSix metal, and a metal such as W or TiN may be used.

본 발명에 의하면, 리세스 게이트 형성과정에서 도핑된 폴리실리콘막 위에 언도핑된 폴리실리콘막을 증착하여 실리사이드막 증착을 위한 사전 세정공정에서 워터마크가 발생하는 것을 억제함으로써 반도체소자의 수율을 증가 시킬 수 있는 효과가 있다.

According to the present invention, the yield of a semiconductor device can be increased by depositing an undoped polysilicon film on a doped polysilicon film during the formation of a recess gate to suppress the occurrence of a watermark in a pre-cleaning process for silicide film deposition. It has an effect.

Claims (6)

소자분리막으로 활성영역이 정의된 반도체 기판상에서 활성영역의 소정부를 에칭하여 트렌치를 형성하는 단계와;Etching a predetermined portion of the active region on the semiconductor substrate in which the active region is defined as an isolation layer to form a trench; 상기 트렌치 위에 게이트 산화막을 증착하는 단계와;Depositing a gate oxide film over the trench; 상기 게이트 산화막위에 도핑된 폴리실리콘막을 증착하는 단계와;Depositing a doped polysilicon film on the gate oxide film; 상기 도핑된 폴리실리콘막 위에 언도핑된 폴리실리콘막을 증착하는 단계와;Depositing an undoped polysilicon film on the doped polysilicon film; 상기 언도핑된 폴리실리콘막을 평탄화하는 단계;Planarizing the undoped polysilicon film; 를 포함하는 리세스 게이트 형성방법. Recess gate forming method comprising a. 제 1항에 있어서, 상기 평탄화는 CMP에 의하는 것을 특징으로 하는 리세스 게이트 형성방법. 2. The method of claim 1, wherein said planarization is by CMP. 제 2항에 있어서, 상기 도핑된 폴리실리콘막이 300~1000Å의 두께로 증착되는 리세스 게이트 형성방법. 3. The method of claim 2, wherein the doped polysilicon layer is deposited to a thickness of 300 to 1000 microns. 제 3항에 있어서, 상기 언도핑된 폴리실리콘막이 300~1000Å의 두께로 증착되는 리세스 게이트 형성방법. 4. The method of claim 3, wherein the undoped polysilicon film is deposited to a thickness of 300 to 1000 microns. 제 1항에 있어서, 상기 언도핑된 폴리실리콘막은 평탄화한 후의 두께가 50Å 이상인 리세스 게이트 형성방법. The method of claim 1, wherein the undoped polysilicon layer has a thickness of 50 GPa or more after planarization. 제 1항에 있어서, 상기 언도핑된 폴리실리콘막 위에 실리사이드막을 증착시키는 단계를 더 포함하는 리세스 게이트 형성방법. The method of claim 1, further comprising depositing a silicide film on the undoped polysilicon film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745930B1 (en) * 2006-05-22 2007-08-02 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR100780629B1 (en) * 2006-11-15 2007-11-30 주식회사 하이닉스반도체 Method for manufacturing semiconductor device with recess gate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745930B1 (en) * 2006-05-22 2007-08-02 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR100780629B1 (en) * 2006-11-15 2007-11-30 주식회사 하이닉스반도체 Method for manufacturing semiconductor device with recess gate
US7575974B2 (en) 2006-11-15 2009-08-18 Hynix Semiconductor Inc. Method for fabricating semiconductor device including recess gate

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