KR20060022404A - Semiconductor memory device having open bitline structure - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an open bit line structure. More particularly, the present invention relates to a semiconductor memory device including a charge / discharge means or a switching element in a pair of bit lines in an open bit line structure of a semiconductor memory device. A technique for improving the noise characteristic of a sense amplifier by zooming is disclosed. The present invention provides a first mat having a plurality of cells between a plurality of bit lines and a plurality of word lines, a second mat having a plurality of cells between a plurality of bit line bars and a plurality of word lines; When the voltage of any one of the plurality of bit lines or the plurality of bit line bars increases, the voltage of the bit line bar or the bit line corresponding to the bit line or bit line bar on which the voltage rises is increased to increase the plurality of bit lines and the And a plurality of amplifiers each amplifying data carried on the plurality of bit line bars.

Description

Semiconductor memory device having open bitline structure

1 is a schematic diagram of a semiconductor memory device having a conventional folded bit line structure.

2 is a schematic diagram of a semiconductor memory device having a conventional open bitline structure.

3 is a schematic diagram of a semiconductor memory device having an open bitline structure in accordance with an embodiment of the present invention.

4 is a schematic diagram of a semiconductor memory device having an open bitline structure in accordance with another embodiment of the present invention.

5 is an operation timing diagram of the semiconductor memory device of FIGS. 3 and 4.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an open bit line structure. More particularly, the present invention relates to a bit line pair in which a charge and a discharging means and a switching element are provided to the bit line pair. This technology improves the noise characteristics of the sense amplifier by zooming in.

In general, a semiconductor memory device is for storing data or reading data in a plurality of memory cells, and includes a plurality of bit lines and a plurality of word lines, a circuit for selecting the bit lines and word lines, and a plurality of bit lines. Peripheral circuits such as sense amplifiers.

In particular, among the plurality of sense amplifiers, the bit line sense amplifier senses and amplifies the data on the bit line and outputs the data to the data bus, and the data bus sense amplifier senses and amplifies the data amplified by the bit line sense amplifier again and outputs the data. Output to the buffer.

The semiconductor memory device is classified into an open bit line structure and a folded bit line structure according to the sense amplifier and the bit line structure.

1 is a schematic diagram of a semiconductor memory device having a conventional folded bit line structure.

As shown in FIG. 1, a folded bit line structure includes a pair of bit lines in one mat (MAT).

In the folded bit line structure, when a voltage is applied to a word line and a cell is selected, the voltage of the bit line pair is slightly increased simultaneously by a coupling capacitor existing between the word line and the bit line.

However, the semiconductor memory device having the folded bit line structure as described above has a problem in that the area consumption is large because all bit line pairs are provided on one mat.

To solve this problem, a semiconductor memory device having an open bit line structure as shown in FIG. 2 is used.

As shown in FIG. 2, the conventional open bitline structure includes a plurality of sense amplifiers between two mats 10 and 20. In this case, the mat A 10 includes a plurality of cells between the plurality of bit lines and the plurality of word lines, and the mat B 20 includes a plurality of cells between the plurality of bit line bars and the plurality of word lines.

The plurality of sense amplifiers 3 are connected between the mats 10 and 20, that is, between the bit lines BLO, BL1, BL2 and the bit line bars / BL0, / BL1, / BL2.

However, in the semiconductor memory device having the open bit line structure, when the voltage is applied to the word line of the mat A 10 and the cell is selected, the word line of the mat B 20 is not selected, so the bit line of the mat A 10 is selected. Noise induced in the bit line bar of the mat B 20 is different from each other.

As described above, the conventional semiconductor memory device having an open bit line structure has a problem in that it is difficult to amplify a bit signal so that the noise of the bit line pair is different.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and includes a capacitor in a bit line pair of a semiconductor memory device having an open bit line structure to prevent a voltage difference between the bit line pairs, thereby improving noise characteristics of the bit line pairs. The purpose is to.

In addition, an object of the present invention is to provide a switch controlled by a predetermined control signal of an open bit line structure to control a voltage of a bit line pair connected to a sense amplifier to a predetermined level to improve noise characteristics and to improve tRP speed.

A semiconductor memory device having an open bit line structure according to the present invention for achieving the above object is a first mat having a plurality of cells between a plurality of bit lines and a plurality of word lines, a plurality of bit line bars and a plurality of A second mat having a plurality of cells between word lines, and a bit corresponding to the bit line or the bit line bar in which the voltage is increased when the voltage of any of the plurality of bit lines or the plurality of bit line bars rises. And a plurality of amplifiers for amplifying the voltages of the plurality of bit lines and the data on the plurality of bit line bars by increasing the voltage of the line bar or the bit line.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic diagram of a semiconductor memory device having an open bit line structure in accordance with an embodiment of the present invention.

A semiconductor memory device having an open bit line structure according to an exemplary embodiment of the present invention includes a mat A 100, a mat B 200, and an amplifier 300.

The mat A 100 and the mat B 200 include a plurality of cells including NMOS transistors and capacitors between the word lines and the bit lines. In this case, the mat A 100 includes a plurality of word lines WL0A to WL2A and a plurality of bit lines BL0 to BL2, and the mat B 200 includes word lines WL0B to WL2B and bit lines BL0 to BL2. Although only a certain number of bit lines and word lines are shown here, the number of word lines and bit lines is set variously according to the size of the semiconductor memory.

The plurality of amplifiers 300 are connected to each bit line pair, and each of the amplifiers 300 includes a sense amplifier 301 connected to the bit line pair and a coupling capacitor C connected in parallel with the sense amplifier 301. do. In this case, the coupling capacitor C is formed using a dielectric material such as a cell capacitor when forming the cell capacitor.

The sense amplifier 301 senses and amplifies the data of the bit line pair, and the capacitor C is a coupling capacitor and removes common mode noise generated when the sense amplifier 301 amplifies the data.

Hereinafter, the operation of the semiconductor memory device having the open bit line structure having the above configuration will be described.

First, when a voltage is applied to the word line WL0A of the mat A 100, the voltages of the bit lines BL0 to BL2 also increase. At this time, the voltage of the bit line bars / BL0 to / BL2 is increased in accordance with the voltage level of the bit lines BL0 to BL2 by the coupling capacitor C connected to the bit line pair.

Accordingly, the common mode noise of the bit line pair is minimized by keeping the voltage levels between the bit line pairs nearly the same.

4 is a schematic diagram of a semiconductor memory device having an open bit line structure in accordance with another embodiment of the present invention.

A semiconductor memory device having an open bit line structure according to an exemplary embodiment of the present invention includes a mat A 100, a mat B 200, and an amplifier 400.

The mat A 100 and the mat B 200 include a plurality of cells including NMOS transistors and capacitors between the plurality of word lines and the plurality of bit lines. In this case, the mat A 100 includes a plurality of word lines WL0A to WL2A and a plurality of bit lines BL0 to BL2, and the mat B 200 includes word lines WL0B to WL2B and bit lines BL0 to BL2. Although only a certain number of bit lines and word lines are shown here, the number of word lines and bit lines is set variously according to the size of the semiconductor memory.

A plurality of amplifiers 400 are connected to each bit line pair, and each of the amplifiers 400 is parallel to the sense amplifier 401 and the sense amplifier 401 connected to the NMOS transistors NM1, NM2, and bit line pairs. A coupling capacitor C is connected.

The NMOS transistors NM1 and NM2 connect the source to the bit line pair, the drain to the node S, and are controlled by the control signals A and B, respectively, to control the potentials of the nodes N1 and N2. At this time, the node S is connected to a plate to have a plate voltage VCP level, and the plate voltage VCP level is preferably set equal to the bit line precharge voltage level (= VCORE / 2).

Coupling capacitor C is formed using a dielectric material such as a cell capacitor when forming the cell capacitor. The sense amplifier 401 is connected to the bit line pair to sense and amplify the data of the bit line pair.

Hereinafter, an operation of a semiconductor memory device having an open bit line structure according to another exemplary embodiment of the present invention will be described with reference to FIG. 5.

First, the bit line pairs are precharged by the bit line equalization bar signal BLEQB. After that, the NMOS transistors NM1 and NM2 are turned on by the high-level control signals A and B to connect the bit line pairs to the node S to maintain the nodes N1 and N2 at the plate voltage VCP level.

Thereafter, when the word line WL of the mat A 100 is activated, charge stored in the cell is charged with the bit line BL. Capacitor C supplies charge to the lower potential of the pair of bit lines.

At this time, by disabling the control signal A to a low level, the NMOS transistor NM1 is turned off so that the node N1 is in a charge distribution state, the control signal B is maintained at a high level, and the node N2 is maintained at the plate voltage VCP level.

Thereafter, the control signal B is turned low to turn off the NMOS transistor NM2 immediately before the sense amplifier 401 is driven, that is, just before the sense amplifier enable signal SAEN is enabled to a high level.

Subsequently, the sense amplifier 401 starts to drive and amplifies and outputs the data of the bit line pair. When the operation of the sense amplifier 401 is completed, the control signals A and B are brought to a high level together with the bit line equalization bar signal BLEQB. Is enabled.

3 and 4, when the word line of the mat A 100 is selected so that the voltage of the bit line of the mat A 100 is increased, the mat B (using a coupling capacitor) is used. By supplying a constant charge to the bit line bar of 200, the voltage of the bit line bar is also raised to a constant level, thereby minimizing the voltage difference between the bit line pairs, thereby improving noise characteristics of the bit line pairs.

In addition, the NMOS transistors NM1 and NM2 of FIG. 4 serve to fix the bit line pairs to a predetermined level.

3 and 4 of the present invention show only an example in which only a capacitor is provided or a switching device and a capacitor are included together. However, only the switching device of FIG. 4 can remove the noise of the bit line pair.

As described above, the present invention has the effect of improving the noise characteristics of the bit line pair by using the coupling capacitor.

In addition, the plate voltage is selectively applied to the bit line pairs to improve the noise characteristics of the bit line pairs and to improve the tRP speed.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

A first mat having a plurality of cells between the plurality of bit lines and the plurality of word lines; A second mat having a plurality of cells between the plurality of bit line bars and the plurality of word lines; And When the voltage of any one of the plurality of bit lines or the plurality of bit line bars increases, the voltage of the bit line bar or bit line corresponding to the bit line or bit line bar where the voltage rises is increased to increase the voltage of the plurality of bit lines. A plurality of amplifiers each amplifying data carried on the plurality of bit line bars; A semiconductor memory device having an open bit line structure, characterized in that comprising a. The method of claim 1, wherein the plurality of amplifiers, A charge connected between the bit line and the bit line bar and charging and discharging a charge to supply charge to either the bit line bar or the bit line when the potential of either the bit line or the bit line bar rises Way; And A sense amplifier connected in parallel with the charging means and sensing and amplifying data of the bit line and the bit line bar; A semiconductor memory device having an open bit line structure, characterized in that it comprises a. The method of claim 2, wherein the charging means, A semiconductor memory device having an open bit line structure, characterized in that it is a capacitor. The method of claim 1, wherein the plurality of amplifiers, A first switching element controlled by a first control signal to supply a predetermined charge to the bit line; A second switching element controlled by a second control signal to supply a predetermined charge to the bit line bar; A charge connected between the bit line and the bit line bar and charging and discharging a charge to supply charge to either the bit line bar or the bit line when the potential of either the bit line or the bit line bar rises Way; And A sense amplifier connected in parallel with the charging means and sensing and amplifying data of the bit line and the bit line bar; A semiconductor memory device having an open bit line structure, characterized in that it comprises a. The method of claim 4, wherein the charging means, A semiconductor memory device having an open bit line structure, characterized in that it is a capacitor. The method of claim 4, wherein the first and second switching elements, A semiconductor memory device having an open bit line structure, characterized in that the NMOS transistor.

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