KR20060020173A - Display panel and display device having signal line - Google Patents

Abstract

The present invention relates to a display panel and a display device having a signal line.

A display panel including a plurality of signal lines each having a first portion and a second portion, the display panel including a connection region consisting of the first portion of the signal line, and a display region consisting of the second portion of the signal line. The first portion of the substrate includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film formed on the gate line, a protective film formed on the gate insulating film, and a contact hole formed in the protective film and the gate insulating film. And the connection member formed on the protective film and the gate insulating film.

In this manner, by making the RC delay of the signal entering the display area constant, problems of image quality such as luminance caused by the difference in the RC delay can be improved.

Printed Circuit Board, Flexible, Connection Line, Lead Wire, Signal Line, Connection Member, Contact Hole

Description

Display panel and display device with signal line {DISPLAY PANEL AND DISPLAY DEVICE HAVING SIGNAL LINE}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.

4 is an enlarged layout view of the fan out area illustrated in FIG. 3.

FIG. 5 is an enlarged layout view of a part of the connecting line illustrated in FIG. 4.

FIG. 6 is a cross-sectional view of the connection line illustrated in FIG. 5 taken along the line VI-VI '.

FIG. 7 is an equivalent circuit diagram of the connection line shown in FIG. 5.

The present invention relates to a display panel and a display device having a signal line.

Recently, organic electroluminescence display (OLED), plasma display panel (PDP), liquid crystal display (LCD), instead of heavy and large cathode ray tube (CRT) Such flat panel displays are actively being developed.

PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic EL display device displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display and an organic EL display device may turn on / off a switching element of a pixel by emitting a gate signal to a pixel including a switching element, a display panel provided with a display signal line, and a gate line among the display signal lines. A gate driver to be turned off, a data driver to apply a data voltage to the data lines of the display signal lines, and a signal controller to control them.

The driving circuit is positioned near the edge of the display device and is connected to the end of the signal line. For this connection, the end of the signal line is concentrated in a narrow area (hereinafter referred to as a connection area). On the other hand, in an area where pixels are located (hereinafter referred to as a display area), signal lines need to maintain intervals determined according to pixel sizes, and thus, line intervals are larger than those of ends connected to the driving circuit. Therefore, in the area between the display area and the connection area, there is a fan-out area in which the distance between the signal lines is gradually widened (or narrowed) in the shape of a side chatter.

The signal lines located near the center of the fan out area are almost straight without changing direction, but the angle at which the signal lines are bent increases toward the edge of the fan out area. Due to this structure, the signal lines have different lengths, and thus the resistance values of the signal lines are also different, thereby degrading the image quality.

In particular, the liquid crystal display adopts a voltage control method for controlling and controlling the voltage applied to each pixel. The time required to reach a predetermined voltage, that is, the RC delay, is different due to the difference in resistance of the signal line. For example, if the RC delays of the gate signals applied to the switching elements of the pixel in the gate driver are different from each other, the gate voltages of the switching elements are different, which also causes the difference in the kickback voltage. As a result, a difference in pixel voltage may cause a problem regarding image quality such as luminance, block deviation, or horizontal stripes throughout the screen.

Accordingly, an object of the present invention is to provide a display device that can solve the problems of the prior art.

According to an exemplary embodiment of the present invention, a display panel includes a plurality of signal lines each including a first portion and a second portion, and a connection area including the first portion of the signal line, and the signal line. A display area formed of the second part,

The first portion of each signal line is formed on an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film formed on the gate line, a protective film formed on the gate insulating film, the protective film and the gate insulating film. A contact hole, and the connection member formed in the protective film and the gate insulating film. In this case, the length of the first portion of each signal line may be longer toward the edge.

In addition, it is preferable that the product of the resistance and the capacitance of the first portion of each signal line is constant, and at least a portion of the first portion of each signal line may have a curved shape and the remaining portion may extend straight.

On the other hand, the display device according to an embodiment of the present invention, a display panel portion consisting of a connection region and the display region, a plurality of gate driving integrated circuit for generating a gate signal, and a flexible printed circuit having the gate driving integrated circuit A plurality of connection lines are disposed in a connection area of the display panel;

The connection line includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film formed on the gate line, a protective film formed on the gate insulating film, a contact hole formed in the protective film and the gate insulating film, and And the connection member formed on the protective film and the gate insulating film.

In this case, it is preferable that the product of the resistance and the capacitance of each connection line is constant, and at least a part of the connection line may have a curved shape and the rest may extend straight.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal control unit 600 to control them.

The display panel unit 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels Px connected to the plurality of display signal lines G ₁ -G _n and D ₁ -D _m in an equivalent circuit.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. It includes the line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a pixel circuit connected thereto.

The switching element Q is a three-terminal element whose control terminal and input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively, and the output terminal is connected to the pixel circuit. have. In addition, the switching element Q is preferably a thin film transistor, and particularly preferably comprises amorphous silicon.

In the case of a liquid crystal display, which is a representative example of a flat panel display, the lower panel 100, the upper panel 200, and a liquid crystal layer 3 therebetween are included as shown in FIG. 2. The display signal lines G ₁ -G _n , D ₁ -D _m and the switching elements Q are provided on the lower display panel 100. The pixel circuit of the liquid crystal display device includes a liquid crystal capacitor C _LC and a storage capacitor C _ST connected to the switching element Q. The holding capacitor C _ST can be omitted as necessary.

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided with a color filter 230 of three primary colors, for example, red, green, or blue, in a region corresponding to the pixel electrode 190. It is possible by doing. In FIG. 2, the color filter 230 is formed on the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to outer surfaces of at least one of the two display panels 100 and 200 of the display panel unit 300 of the liquid crystal display device.

Referring back to FIG. 1, the gray voltage generator 800 generates one or two gray voltages related to the luminance of the pixel. If there are two sets, one of the sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n . The gate driver 400 includes a plurality of stages arranged substantially in a row as a shift register.

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a display device will now be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal and the input image signals R, G, and B, and generates the image signals R, G, and B. After appropriately processing the display panel 300 according to the operating conditions, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transferred to the data driver 500. Export.

The gate control signal (CONT1) includes a gate-on voltage vertical synchronization start signal (STV) for instructing the start of output of the (V _on), the gate-on voltage gated clock signal that controls the output timing of the (V _on) (CPV) and the gate-on An output enable signal OE or the like that defines the duration of the voltage V _on .

The data control signal CONT2 is a load signal LOAD and a data clock signal for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data DAT and the data lines D ₁ -D _m . (HCLK). In the case of the liquid crystal display or the like shown in FIG. 2, the polarity of the data voltage with respect to the common voltage V _com (hereinafter referred to as "polarization of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage") is inverted. The inversion signal RVS may also be included.

The data driver 500 sequentially receives the image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In the case of the liquid crystal display shown in FIG. 2, the difference between the data voltage applied to the pixel and the common voltage V _com is represented as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. In the case of the liquid crystal display shown in FIG. 2, in particular, when one frame ends, the next frame starts and an inversion signal applied to the data driver 500 such that the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame. The state of (RVS) is controlled ("frame inversion"). At this time, the polarity of the data voltage flowing through one data line is changed according to the characteristics of the inversion signal RVS even in one frame (eg, "row inversion", "point inversion"), The polarities can also be different (eg "invert columns", "invert points")

Next, the display panel and the display device according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 7.

FIG. 3 is a schematic diagram of a display device according to an exemplary embodiment of the present invention, FIG. 4 is an enlarged layout view of the fan out region shown in FIG. 3, FIG. 5 is an enlarged layout view of the connection line illustrated in FIG. 4, and FIG. 6. 5 is a cross-sectional view of the connecting line shown in FIG. 5 taken along the line VI-VI ', and FIG. 7 is an equivalent circuit diagram of the connecting line shown in FIG.

In FIG. 3, gate lines G ₁ -G _n are denoted by reference numeral '121', and data lines D ₁ -D _m are denoted by reference numeral '171'.

As shown in FIG. 3, the display device according to an exemplary embodiment of the present invention includes a display panel 300, a plurality of gate FPC substrates 410 and a plurality of data FPC substrates 510 attached thereto. And a printed circuit board (PCB) 550 attached to the data FPC board 510.

A gate driver integrated circuit (IC) 440 and a data driver integrated circuit 540 are mounted in the form of a chip on the gate FPC board 410 and the data FPC board 510, respectively. , 540 and leader lines 420 and 520 for electrical connection with the outside are formed. The FPC substrates 410 and 510 are made of polyimide or polyester.

The printed circuit board 550 includes various circuit elements for driving and controlling the liquid crystal panel assembly 300. For example, the signal controller 600 and the gray voltage generator 800 illustrated in FIG. 1 are mounted on the PCB 550. These circuit elements are connected to the data driving integrated circuit 540 through a signal line (not shown) provided on the printed circuit board 550 and a lead line 520 and a connection line of the data FPC board 510. The electrical connection between the integrated circuit 440 and the printed circuit board 550 may include signal lines (not shown) separately provided on the data FPC substrate 510 and the lower panel 100 and the lead lines of the gate FPC substrate 410. 420 and connecting lines 430a and 430b, and the leader lines 420 and 520 are made of a material such as copper having a relatively low resistance. Alternatively, the driving integrated circuits 440 and 550 may be directly mounted on the lower panel 100 of the display panel unit 300, in which case the gate FPC substrate 410 is not necessary.

The lower panel 100 of the display panel unit 300 is positioned on and outside the display area D in which the array of pixel electrodes 190 is disposed, and the display signal lines 121 and 171 and the FPC substrates 410 and 510. Or a peripheral area in which physical and electrical connections with the driving integrated circuits 440 and 540 are made.

The display signal lines 121 and 171 are connected to the pixel electrode 190 through the switching element Q in the display area D, and are substantially parallel to each other, and end portions of the signal lines 121 and 171 positioned in the peripheral area. The FPC boards 410 and 510 are connected to the driving integrated circuits 440 and 540. However, in the case of the display device illustrated in FIG. 3, the gap between the lead lines 420 of the FPC boards 410 and 510 for the connection between the driving integrated circuits 440 and 540 and the display signal lines 121 and 171 is represented in the display area. Since the distance between the signal lines 121 and 171 in the peripheral area is gradually changed as compared with the interval between the display signal lines 121 and 171 in (D), an area in which the signal lines 121 and 171 are arranged in a fan shape (hereinafter, referred to as " a " (F) is called a fan-out area.

4 illustrates a region where the gate driver 400 is located among the fan out regions.                     

The fan out area includes a connection line 430, that is, a front connection line 430a connected to the gate FPC substrate 410 and a rear connection line 430b connected to the gate line 121 of the display area D. At this time, the front end connection line 430a is repeated in a curved shape, and the rear end connection line 430b extends in a straight line, while the curved shape increases toward the center of the front connection line 430a, while the straight line distance of the rear connection line 430b is increased. Decreases. This may compensate to some extent that the length of the connection line 430 is extended to the edge due to the fan out. However, since the bend spacing of the connection line 430a and the width of the wiring have to be taken into consideration, the connection line 430 becomes longer toward the edge.

5 and 6, the connection line 430 is formed on the substrate, and the gate insulating layer 140 is formed on the connection line 430. A passivation layer 180 is formed on the gate insulating layer 140, and contact holes 182a and 182b are formed in the passivation layer 810 and the gate insulating layer 140 at both ends of the connection line 430, that is, the front end connection line 430a. It is formed at the end of the start portion and the rear connection line (430b). The connection member 82 is formed on the passivation layer 180 and the gate insulating layer 140. The connection member 82 is preferably made of indium tin oxide (ITO) or indium zinc oxide (IZO) having excellent contact characteristics.

In this way, the connection line 430 is also connected to each other through the connecting member 82 can be seen as a kind of short circuit state. However, the length of the connecting line 430 is not short but has a very long length. Therefore, since there is not a resistance at all but a slight resistance, it can be represented by an equivalent circuit as shown in FIG.                     

That is, it can be seen that the upper connection member 82 and the lower connection line 430 are connected in parallel with two contact holes 182a and 182b at both ends. In detail, since the connection member 82 and the connection line 430 do not have the same resistance value, resistances having different resistance values may be positioned. As a result, since the voltage values of the two contacts N1 and N2 are different, a kind of capacitor C including the passivation layer 180 and the gate insulating layer 140 as a dielectric material is formed between the connection member 82 and the connection line 430. do.

The capacitance of this capacitor C is inversely proportional to the length, as is known. That is, if the length of the connection line 430 is long, the capacitance is reduced, and if the length is short, the capacitance is increased. However, the resistance is the opposite of the capacitance, so the longer the resistance increases, the shorter the resistance decreases. For example, the connection line 430 located at the edge has a long resistance and has a large capacitance while the capacitance is small, and the connection line 430 located at the center has a short resistance and has a large capacitance while having a large resistance.

In this way, the product of the resistance of each connection line 430 and the capacitance have a constant value. Therefore, the time taken to reach a constant voltage, that is, the RC delay is all constant. As a result, the voltage difference caused by the difference in the RC delay disappears so that the RC delay of the gate signal applied to the switching element Q of the pixel in the gate driver 400 is constant, thereby making the kickback voltage constant. As a result, the difference in pixel voltage disappears, and thus problems related to image quality such as luminance, block deviation, or horizontal stripes may be solved.

 In this way, by forming contact holes 182a and 182b at both ends of the connecting line 430 and connecting them through the connecting member 82, the resistance according to the difference in length of each signal line is compensated by the capacitance to reduce the RC delay. Make it constant. Therefore, it is possible to solve the poor image quality caused by the difference in the RC delay.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A display panel including a plurality of signal lines each consisting of a first portion and a second portion, A connection region consisting of the first portion of the signal line, and A display area formed of the second portion of the signal line Including; The first portion of each signal line Insulation board, A gate line formed on the insulating substrate, A gate insulating film formed on the gate line, A protective film formed on the gate insulating film, Contact holes formed in the protective film and the gate insulating film, and The connection member formed on the protective film and the gate insulating film. Containing Display panel. In claim 1, The length of the first portion of each signal line is longer toward the edge of the display panel. In claim 2, And a product of a resistance and a capacitance of the first portion of each signal line being constant. In claim 3, At least a portion of the first portion of each signal line has a curved shape and the remaining portion extends straight. A display panel unit comprising a connection area and a display area, A plurality of gate drive integrated circuits for generating a gate signal, and A flexible printed circuit board provided with the gate driving integrated circuit, Including, A plurality of connection lines are located in the connection area of the display panel. The connecting line Insulation board, A gate line formed on the insulating substrate, A gate insulating film formed on the gate line, A protective film formed on the gate insulating film, Contact holes formed in the protective film and the gate insulating film, and The connection member formed on the protective film and the gate insulating film. Containing Display device. In claim 5, A display device having a constant product of resistance and capacitance of each connection line. In claim 6, At least a portion of the connection line has a curved shape and the others extend straight.

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