KR20060016879A - Bias circuit for power saving in mobile-phone - Google Patents

Abstract

The present invention relates to a driving voltage stabilization circuit of a mobile communication terminal, and in particular, a drive for preventing power loss by separating and driving a core circuit and a bias circuit for stabilizing a driving voltage of a core circuit in a transceiver circuit of a mobile communication terminal. It relates to a voltage stabilization circuit. The driving voltage stabilization circuit according to the present invention includes a core circuit determining whether driving is performed according to a core circuit driving voltage; And a bias circuit driven by a separate bias driving voltage and providing stable power to the core circuit. According to the present invention, the bias circuit for stabilizing the applied power source is driven separately from the core circuit, thereby minimizing unnecessary power consumption at a time irrelevant to the actual core circuit driving time.

Mobile communication terminal, driving voltage stabilization circuit, bias circuit

Description

Bias circuit for power saving in mobile-phone             

1 is a voltage stabilization circuit including a core circuit and a bias circuit according to the prior art.

2 is a block diagram of a mobile communication terminal according to the present invention;

3 is a voltage stabilization circuit including a core circuit and a bias circuit according to the present invention.

4 is a view showing a signal waveform according to the driving voltage applied according to the present invention.

The present invention relates to a driving voltage stabilization circuit of a mobile communication terminal, and in particular, a driving for preventing power loss by separating and driving a core circuit and a bias circuit for stabilizing a driving voltage of the core circuit in a transceiver circuit of the mobile communication terminal. It relates to a voltage stabilization circuit.

1 is a voltage stabilization circuit including a core circuit and a bias circuit according to the prior art. As shown, when power is supplied to the core circuit 10 embedded in the terminal system in the prior art, the power is supplied to the Vdd pin that turns on the entire terminal system.

In order to actually drive the core circuit 10 by the supplied power, the power must be stabilized at a constant level. In the existing core circuits 10, such a stabilization circuit, that is, a bias circuit 11 is provided. Is integrated with the core circuit 10. Also, when the core circuit is controlled in the power down mode, which is a mode for reducing power, it can be seen that power is supplied to one pin, that is, the Vpwrdwn pin.

Therefore, after the terminal is driven by Vdd, it can be seen that the core circuit 10 and the bias circuit 11 are both supplied with the same power by Vpwrdwn. However, the bias circuit 11, which is a conventional power supply stabilization block, is embedded together with the core circuit 10, and the block cannot be controlled separately.

Therefore, in the prior art, when the power source Vdd is applied to the entire system and power is supplied to the core circuit 10, that is, when the core circuit 10 is turned on, the core circuit 10 is substantially changed. Power is supplied even when the power does not need to be driven to consume unnecessary power.                         

In other words, in the related art, power is not cut off to the core circuit 10 even during an applied power supply stabilization time irrelevant to actual core circuit 10 driving, and current / power is continuously consumed even during that time. This power consumption occurs both at the time of power-up for the first time in the terminal system and at the time of waking from the sleep mode, resulting in a significant amount of power loss.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and aims at minimizing power consumption at a point irrespective of the actual core circuit driving time by driving a bias circuit that stabilizes an applied power source separately from the core circuit. do.

The driving voltage stabilization circuit according to the present invention for achieving the above object comprises a core circuit for driving whether or not determined according to the core circuit driving voltage; And a bias circuit driven by a separate bias driving voltage and providing stable power to the core circuit.

In the driving voltage stabilization circuit according to the present invention for achieving the above object, the core circuit is characterized in that it comprises a separate core circuit driving voltage terminal.

In the driving voltage stabilization circuit according to the present invention for achieving the above object, the bias circuit is characterized by having a separate bias circuit driving voltage terminal.                         

In the driving voltage stabilization circuit according to the present invention for achieving the above object, the bias circuit is characterized in that it further comprises a capacitor for providing a stable power to the core circuit.

In the driving voltage stabilization circuit according to the present invention for achieving the above object, the capacitor is characterized in that the capacity is determined according to the standby time of the core circuit.

A mobile communication terminal having a driving voltage stabilization circuit according to the present invention for achieving the above object comprises: a core circuit determining whether driving is performed according to a core circuit driving voltage; And a bias circuit including a bias circuit provided with a separate bias driving voltage in order to stabilize the power supplied to the core circuit at a constant level.

In the mobile communication terminal having a driving voltage stabilization circuit according to the present invention for achieving the above object, the core circuit is characterized in that it comprises a separate core circuit driving voltage terminal.

In the mobile communication terminal having a driving voltage stabilization circuit according to the present invention for achieving the above object, the bias circuit is characterized in that it comprises a separate bias circuit driving voltage terminal.

In the mobile communication terminal having a driving voltage stabilization circuit according to the present invention for achieving the above object, the bias circuit is characterized in that it further comprises a capacitor for providing a stable power to the core circuit.                         

In the mobile communication terminal having a driving voltage stabilization circuit according to the present invention for achieving the above object, the capacitor is characterized in that the capacity is determined according to the standby time of the core circuit.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to a user's intention or custom, and the definitions should be made based on the contents throughout the specification.

2 is a block diagram of a mobile communication terminal according to the present invention. In the following description, the mobile communication terminal is intended to include a cellular phone, a personal communication system (PCS), an international mobile communication-2000 (IMT2000) terminal, and the like. I will explain with a general configuration.

Referring to FIG. 2, the control unit (MPU: Micro-processor unit) 100 performs processing and control for voice communication and data communication, which is an overall operation of the mobile terminal, and calculates a waiting time according to the present invention. Determine whether the core circuit driving voltage is applied. In the following description, description of the processing and control of the conventional control unit 100 is omitted.

The read only memory (ROM) 102 stores microcode and various reference data of a program for processing and controlling the control unit 100. Random Access Memory (RAM) 104 is a working memory of the controller 100. Stores temporary data generated during the execution of various programs. Flash ROM 106 stores various updatable storage data such as a phone book.

Key pad 108 includes numeric keys 0-9, menu, cancel (clear), confirm, call (TALK), end (END), Internet access, direction keys (up / down / left). / Right) and a plurality of function keys, and provides key input data corresponding to the key pressed by the user to the controller 100. In particular, the four direction keys are used as shortcuts to directly enter specific menu items (eg, message management (←), phone book (→), top menu list (↑), music box (↓)).

The display 110 displays status information generated during the operation of the mobile communication terminal, a limited number of characters, a large amount of video and still images, and the like. The display unit 100 may use a color liquid crystal display (LCD).

The codec (Coder-Decoder) 112 connected to the control unit 100 and the speaker 116 and the microphone 114 connected to the codec 112 are voice input / output blocks used for phone calls and voice recording. . The codec 112 converts the PCM data provided from the controller 100 into an analog voice signal and transmits the same through the speaker 116 and converts the voice signal received through the microphone 114 into PCM data. Provided to the controller 100.

In addition, the RF unit (Radio Frequency unit) (120) is the frequency of the radio frequency signal received via the antenna 118 is provided to the baseband processing unit 122 by lowering the frequency, the baseband signal from the baseband processing unit 122 The frequency is raised and transmitted through the antenna 118. The baseband processor 122 processes a baseband signal transmitted and received between the RF unit 120 and the controller 100.

For example, in the case of transmission, channel coding and spreading of data to be transmitted are performed, and in the case of reception, the function of despreading and channel decoding of a received signal is performed. . That is, the baseband processor 122 is a block for demodulating various channels (calling channel, traffic channel, etc.) received from the base station or generating various channels (access channel, traffic channel, etc.) transmitted to the base station.

3 is a voltage stabilization circuit including a core circuit and a bias circuit according to the present invention.

As shown, the present invention designs a bias circuit 210 that is independent of the core circuit 200 to stabilize the applied power supply to a certain level, and a power down mode. The core core circuit 200 and the bias circuit 210 can be controlled respectively. Therefore, even when the power supply Vdd is applied, the power supply of the core circuit 200 can be cut off by controlling the values of V core and V bias.

That is, when the terminal driving voltage Vdd is applied, driving of the core circuit 200 and the bias circuit 210 of FIG. 3 is determined according to the set V core and V bias values. For example, even when the power supply Vdd is applied, only the bias enable signal is applied to the bias circuit 210, and the core circuit 200 is not driven when the core enable signal is not applied to the core circuit 200. .

In the present invention, the bias enable signal or the core enable signal refers to a signal for driving the bias circuit 210 or the core circuit 200, and typically uses a “low” value.

Accordingly, when the V bias value is 0, that is, when the bias enable signal is applied, the bias circuit 210 is driven. The driven bias circuit 210 provides the core circuit 200 with a stabilized constant level of voltage along with the external capacitor 220 added to the bias circuit 210.

Meanwhile, in the core circuit 200, when the core enable signal is not applied, that is, when the V core value is “high,” power is not supplied, thereby reducing unnecessary power consumption.

That is, when only the bias enable signal is applied at the “high” state in which both the core circuit 200 and the bias circuit 210 are disabled, power is supplied only to the bias circuit 210. The power stabilization process by the 210 and the capacitor 220 is performed. The waiting time t required for stabilization may be adjusted by the value of the external capacitor 220.

The most representative example of the core circuit 200 according to the present invention may be an Rx ADC in a mobile communication terminal transceiver, and the Tx DAC may also be applied to the circuit. In addition, the UART, D-CA, USB, USIM can also be said to be an example corresponding to the core circuit 200.

When the core circuit 200 is an Rx ADC, when PLL locking, which is a point in time at which transmission / reception frequencies coincide, is performed, the Rx ADC, that is, the core circuit 200 starts driving. Therefore, the power supplied to the Rx ADC 200 until the PLL lock is made corresponds to unnecessary power consumption. In order to prevent this, the power supply to the Rx ADC 200 is cut off until the standby time t.

In other words, when the terminal driving voltage Vdd is applied, power is supplied to the RF unit, and the RF unit is driven, the Rx ADC 200 performs PLL locking. When the PLL locking is performed, the Rx ADC 200 needs power at the time when data is input to the AD converter, that is, the Rx ADC 200. That is, at this point in time, driving of the AD converter circuit, that is, the Rx ADC 200, is started.

The time point is commonly referred to as a waiting time t, and the value of the capacitor is determined according to the waiting time t value. That is, the value of the capacitor is determined so that charging can be made for the time t until the PLL lock is made.

On the other hand, in order to perform the PLL locking and operate the AD converter circuit 200, the driving voltage V core which is an enable signal must be applied to the Rx ADC 200. That is, when the Rx ADC driving voltage is applied, the Rx ADC 200 is driven, and as described above, the bias circuit 210 supplies the stabilized power together with the capacitor 220 to the Rx ADC 200. The power supply by the capacitor 220 is for more stabilized power supply by allowing the power supply with the bias circuit 210.

In the present invention, the control unit determines whether V core and V bias are applied according to the waiting time t. That is, the controller applies only the V bias to the bias circuit 210 until the PLL locking is performed in the Rx ADC 200, and when the PLL locking is performed, the V core is applied together with the V bias and the bias circuit 210 and the Rx ADC ( 200).

Therefore, the voltage of the capacitor 220 is applied to the Rx ADC 200 together with V core to receive more stable power. As a result, the control unit can prevent unnecessary power consumption by blocking the V core during the waiting time t until the PLL locking is performed.

4 is a diagram illustrating a signal waveform according to the driving voltage applied according to the present invention.

As shown in the drawing, when the terminal driving voltage V dd is applied to the initial power-on state, a “low” value is applied to the V bias terminal so that the bias circuit is active, while the “V core” terminal is “ High ”value to apply the core circuit to the sleep state. In addition, the capacitor is charged as the bias circuit is activated (11). At this time, the charging time t is determined by the time until the PLL locking is performed in the case of the Rx ADC.

Once PLL Locking is in place, the core circuit is ready to drive. When the core circuit is actually driven, the controller applies a “low” value to the V core terminal so that the core circuit is activated and both the bias circuit and the core circuit are activated. In the active state of both the bias circuit and the core circuit, the terminal work, that is, broadcast or call transmission / reception work is possible (12).

On the other hand, if the user stops using the terminal and no operation is performed despite a predetermined time, the terminal enters a sleep mode. In sleep mode, a “high” value is applied to both the V bias and V core terminals.

Thus, both the bias circuit and the core circuit are powered off, and the bias circuit returns to its initial state (13). To use the core circuit again in the initial state or to wake up from sleep mode, the state is activated again (14).

As described above, the present invention can prevent unnecessary power from being supplied to the core circuit from the system power on until the actual core circuit needs to be operated. That is, the controller cuts off the V core value in intervals 11, 14, and 17, thereby preventing power consumption.

This means that the present invention has the same power consumption protection effect not only when the driving power is supplied to the first terminal but also when the terminal wakes up from the sleep mode. In FIG. 3, 14 and 17 correspond to sections corresponding to waking from the sleep mode.

That is, the present invention stabilizes the bias circuit with V bias first and then sequentially supplies power to the core circuit even when waking from the sleep mode as when the initial Vdd is applied, so that the power supplied to the core circuit during the period in which the applied power is stabilized. It is possible to bring the effect of saving.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only and not intended to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

As described above, the bias circuit for stabilizing the applied power source is driven separately from the core circuit, thereby minimizing unnecessary power consumption at a point irrespective of the actual core circuit driving time.

Claims (10)

In the driving voltage stabilization circuit for preventing power loss, A core circuit determining whether driving is performed according to a core circuit driving voltage; And And a bias circuit which is driven by a separate bias driving voltage and provides stable power to the core circuit. 2. The driving voltage stabilization circuit according to claim 1, wherein the core circuit includes a separate core circuit driving voltage terminal. 2. The driving voltage stabilization circuit according to claim 1, wherein the bias circuit includes a separate bias circuit driving voltage terminal. The driving voltage stabilization circuit of claim 1, wherein the bias circuit further comprises a capacitor providing stable power to the core circuit. 5. The driving voltage stabilization circuit of claim 4, wherein the capacitor has a capacity determined according to a standby time of the core circuit. In the mobile communication terminal having a driving voltage stabilization circuit for preventing power loss, A core circuit determining whether driving is performed according to a core circuit driving voltage; And And a stabilization circuit comprising a bias circuit provided with a separate bias driving voltage to stabilize the power supplied to the core circuit at a constant level. The mobile communication terminal of claim 6, wherein the core circuit includes a separate core circuit driving voltage terminal. The mobile communication terminal of claim 6, wherein the bias circuit includes a separate bias circuit driving voltage terminal. The mobile communication terminal of claim 6, wherein the bias circuit further comprises a capacitor providing stable power to the core circuit. The mobile communication terminal of claim 9, wherein the capacitor has a capacity determined according to a standby time of the core circuit.

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