KR20060009317A - Recursive bit-stream converter and method for recursive bit-stream conversion - Google Patents

Abstract

Recursive bit-stream converter (Rebic) for converting a multi-bit digital input signal to a single bit digital output signal comprising a digital low pass filter and multi-bit quantizer means in a feedback arrangement and means to serialize the digital words of the quantizer means. To obtain a non-integer Rebic factor the quantizer means comprise at least two quantizers that are successively operative to serialize their digital words to the output of the converter.

Description

Circular bitstream converter and signal conversion method {RECURSIVE BIT-STREAM CONVERTER AND METHOD FOR RECURSIVE BIT-STREAM CONVERSION}

The present invention relates to a recursive bit-stream converter (Rebic) for converting a multi-bit digital input signal into a single bit digital output signal, wherein the converter performs a low pass filtering on the input signal in a feedback loop. Means for generating a digitally filtered word, quantizer means for quantizing the filtered word, and means for applying the quantized filtered word to a low pass filtering means via feedback means, outside of the feedback loop, And means for parallel-to-serial converting the quantized filtered words to produce a single bit digital output signal.

The present invention also relates to a method for converting a multi-bit digital input signal into a single bit digital output signal, wherein the input signal is low pass filtered by a low filter means to form a digital filtered word, and the digital filtered word is quantized. Quantized by conventional means, fed back to a low pass filter means, in which the quantized filtered word is converted into a single bit digital output signal by means of parallel-to-serial conversion means.

An example of such a cyclic bitstream converter is described in Applicant's prior European patent application 01203770.1 (PHNL010676).

A recursive bitstream converter (Rebic) is a generalized digital implementation of a conventional single-bit sigma-delta modulator, where a high precision multi-bit signal is converted into a 1-bit digital signal (bitstream). Is converted. The main purpose of a single bit sigma delta modulator is to reduce the number of bits without substantially reducing the signal to noise ratio. Single bit sigma delta modulators include a loop filter with a single bit quantizer that operates at the clock rate of the bitstream and delivers the output signal at the same sample rate, while Rebic can be subsequently serialized to obtain a single bit output signal. It is characterized by a quantizer that carries a digital word each having a plurality of bits. The number of bits contained in each such word is called the Rebic coefficient q. Rebic's advantages over conventional digital single bit sigma delta modulation are the reduction of high speed circuitry, low power consumption, low interference tone in the bit stream, and increased stability in high order configurations. All these attributes are the result of the multiple bit characteristic of the signal in the inner modulation loop, despite the one bit characteristic of the output signal. The reason for the higher stability is that the quantizer in the Rebic system has many levels of properties. Thus, the Rebic configuration is particularly useful at higher values of Rebic coefficient q. Higher Rebic coefficients, ie, more levels are used in the quantizer, and the more linear behavior of the system is the corresponding stability characteristic of the linear system.

However, a disadvantage of using a Rebic configuration instead of a sigma delta modulator is that some degradation in the signal-to-noise ratio occurs, increasing the value of q. Thus, in applications where stringent requirements for signal-to-noise ratio exist, the cyclic bitstream converter is preferably used with a substantially lower Rebic coefficient q. In this kind of application, the value of the Rebic coefficient is influenced by the compromise, that is, the higher the Rebic coefficient and the more linear the operation, the less intermodulation and less interference tones (in audio applications). On the other hand, a lower Rebic coefficient results in a better signal-to-noise ratio of the converter.

Summary of the Invention

However, since the Rebic coefficient q is the number of levels of the quantizer, this coefficient can have only integer values. The problem with using a Rebic configuration with a low q coefficient is that the steps between two consecutive values of the Rebic coefficient are relatively large. It is therefore an object in particular of the present invention to provide a cyclic bitstream converter having a non-integer effective q coefficient, and therefore the cyclic bitstream converter of the present invention comprises at least two quantizers of bits with different quantizer means. The output words are successively parallel-to-serial converted to produce an output signal, synchronized and applied successively to the feedback means.

In this regard, the expression “continuously” does not mean only that after each serialized word of one of the quantizers in the output signal of the converter, the serialized word of the other quantizer needs to be followed directly. You should know It also includes that more than one serialized word is generated from one quantizer before the other quantizer operates. It also includes that each quantizer is operated in a random sequence.

Since it is an object of the present invention to provide a converter with a non-integer effective Rebic coefficient, the quantizer means comprises two quantizers, where the number of bits of one of these quantizers is higher than the number of bits of the other of these quantizers. If the converter is characterized in terms of unity, the required circuit is the simplest. In particular, the present invention is directed to using a cyclic bitstream converter in code for generating a super audio CD signal, wherein the quantizer means alternately operate upon generating one serialized word in the output signal of the converter. It can be characterized in that it includes a 2-bit quantizer and a 3-bit quantizer. Rebic configurations for application in coders for super audio CDs are of interest because of their low amount of interference tones. However, in such applications, stringent requirements exist for signal ash noise, so only a very small sacrifice in signal-to-noise ratio is allowed compared to conventional single bit sigma delta modulation. It was found that the Rebic coefficient q = 2 could meet the specification, but the coefficient q = 3 showed too low signal to noise ratio. Because of the relatively large steps between q = 2 and q = 3, the intermediate coefficients are of interest. If the two-bit and three-bit quantizers alternate their bits at the output of the converter, the appropriate Rebic coefficient q = 2,5 is obtained. If a higher signal-to-noise ratio is still desired, the effective factor q = 1,5 can be chosen. In that case, in order to supply the output bits, the 1-bit quantizer and the 2-bit quantizer must operate alternately.

The method described in the second paragraph according to the invention is characterized in that the quantizer means comprises at least two quantizers Q ₂ , Q ₃ of different bits and whose output words are parallel-to-serial conversion means P ₂ , P _3. ) Is continuously parallel-to-serial converted into an output signal O, synchronized, and fed back continuously to the low pass filter means.

An advantage of the method according to the invention is that a non-integer Rebic coefficient can be obtained, thus achieving an optimal tradeoff between linearity, and hence stability and signal-to-noise ratio.

The invention will be described with reference to the accompanying drawings.

1 is a first embodiment of a cyclic bitstream converter according to the present invention.

FIG. 2 is a graph for clearly showing the operation of the cyclic bitstream converter of FIG. 1.

3 is a second embodiment of a cyclic bitstream converter according to the present invention.

FIG. 4 is a graph for clearly showing the operation of the cyclic bitstream converter of FIG. 3.

The cyclic bitstream converter of FIG. 1 includes a digital low pass filter F. This filter receives a high precision digital signal of a plurality of bits (e.g., 16 bits) of sample rate f _s / q at input terminal I. Such a digital low pass filter may be similar to the low pass filter described and shown in FIG. 2 of Applicant's European Patent Application 01203770.1 (PHNL010676), which is incorporated herein by reference. The output word of low pass filter F is applied to 2-bit quantizer (mapper) Q ₂ and 3-bit quantizer (mapper) Q ₃ . Two output bits of quantizer Q ₂ are applied to adder B ₀ , through two multipliers M ₁ and M ₂ to adder B ₁ , and through two other multipliers M ₃ and M ₄ to adder B ₂ . Is approved. Likewise, three output bits of quantizer Q ₃ are applied to adder B ₃ , and applied to adder B ₄ through three multipliers M ₅ , M ₆ and M ₇ , and three further multipliers M ₈ , M ₉ and It is applied to adder B ₅ via M ₁₀ .

The configuration of FIG. 1 further includes a switch S having three sections S _a , S _b , S _c that are synchronously switched. Switch section S _a alternately connects the outputs of adders B ₀ and B ₃ to the feedback input I _a of filter F. Switch section S _b alternately connects the outputs of adders B ₁ and B ₄ to the feedback input I _b , and switch section S _c alternately connects the outputs of adders B ₂ and B ₅ to the feedback input I _c of the filter F. Connect. The three feedback signals are denoted by A _0j , A _1j and A _2j , respectively.

When the switch S is in the position as shown in FIG. 1, the 3-bit output of the quantizer Q ₃ is fed back through the multipliers M ₅ -M ₁₀ and adders B ₃ , B ₄ , B ₅ to the feedback input I _a , Feedback to I _b , I _c . The filter F, the quantizer Q ₃ and the three feedback paths constitute a third-order Rebic converter with a Rebic coefficient q = 3 in which only the output bits of the quantizer should be serialized. This is described in the above-mentioned patent application, where the feedback signals A _Oj , A _1j , A _2j have the same meaning. In FIG. 1, the tertiary Rebic configuration is chosen only for convenience of illustration. Indeed, considerably higher orders, e.g., seventh order, can be chosen to obtain better noise shaping and thus higher signal-to-noise ratios.

When the position of switch S is changed, the 2-bit output of quantizer Q ₂ is fed back to the three feedback inputs of filter F through multipliers M ₁ -M ₄ and adders B ₀ -B ₂ . The filter F, the quantizer Q ₂ and the three feedback paths constitute a third order Rebic with q = 2. Two output bits of the quantizer Q ₂ are parallel-to-serial converter P is applied to the _2, 3-bit output of the quantizer Q ₃ is a parallel-to-serial converter is applied to P _3. Adder A combines the output bits of the two parallel-to-serial converters. Clock pulses of clock frequency f _s are applied to the two parallel-to-serial converters via switch R. Clock pulses f _s and pulses for switches R and S are derived from a pulse generator (not shown) that is synchronized with the sample rate f _s / q of the input signal. The time relationship between the pulse and the signal is shown in FIG.

In this figure, upper row 2 _a represents a series of clock pulses at rate f _s applied to switch R, and second row 2 _b represents a series of clock pulses at rate f _s / q used to digitize the input signal. Indicates. It will be apparent that five periods of the clock pulses in row 2 _a correspond to two periods of the clock pulses in row 2 _b , and therefore q = 2,5. Row 2 _c represents the 3-bit word generated by quantizer Q ₃ . These words are generated at the same rate f _s / q as the rate of the input signal and filter F. As shown below, half of these output words will be used to form the output signal. Unused output words of quantizer Q ₃ are indicated by a dotted line. These words are generated by Q ₃ when its output is disconnected from the feedback path for low pass filter F.

Row 2 _d represents a 2-bit word from quantizer Q ₂ and also has a rate f _s / q. Again, the dotted line represents the unused word, that is, the word generated by quantizer Q ₂ when the quantizer output is disconnected from the feedback path to filter F. Both the use of the quantizer Q ₃ and unused output word is a 3-bit parallel-to-serial converter is stored in the P _3. The used word is then clocked out to adder A at rate f _s . Similarly, the used and unused output words of quantizer Q ₂ are stored in a 2-bit parallel-to-serial converter, and only used words are clocked out to adder A at rate f _s .

Row 2 _f of FIG. 2 shows the switching signal that controls switch S. FIG. If this signal is high, the output word of Q ₃ is used to form a feedback to filter F, and if this signal is low, the output word of Q ₂ is used for this purpose. Row 2 _g shows the signal controlling switch R. If this signal is high, three clock pulses of rate f _s are applied to the 3-bit parallel-to-serial converter P ₃ to shift its contents to output O, and if this signal is low, two clock pulses are two bits. Is applied to the parallel-to-serial converter P ₂ to shift its contents to the output. Thus, the used output words of quantizers Q ₂ and Q ₃ are alternately serialized and applied to the output O of the converter at rate f _s . Row 2 _e shows the bits at the output O of the converter, represented by the word from which the bits are derived. From this row, it can be seen that the bit rate at the output O is equal to f _s, and alternately, three bits are generated from the quantizer Q ₃ and two bits are generated from the quantizer Q ₂ . Therefore, the effective Rebic coefficient q of the converter is 2,5.

Different bit quantizers can obtain different non-integer Rebic coefficients. Preferably, when the required q coefficient is between integers n and n + 1, an n bit quantizer and an n + 1 bit quantizer are used because the circuit is the simplest. The output sequence need not be generated alternately from the two quantizers. For example, if an effective Rebic coefficient q = 2 ms is required, one serialized output word of the 3-bit quantizer may be followed by two serialized output words of the 2-bit quantizer. This can be implemented by the configuration as shown in FIG. 1, only the switching signals for the switches R and S need to be modified. Instead of a fixed sequence of switching of the output words of the quantizer, a random sequence can also accomplish the task.

The circular bitstream converter of FIG. 3 has a number of parts similar to those of FIG. 1, which parts have the same reference numerals as in FIG. 1. In some cases, the sample rate of the output signal is preferably the same as the sample rate of the input signal. Thus, an important difference from the converter of FIG. 1 is that the input signal of the converter of FIG. 3 has a sample rate by the Rebic coefficient q which is higher than the sample rate f _s , ie, the input sample rate in the converter of FIG. 1. Therefore, all parts of converter 3 must be able to operate at this higher sample rate.

Instead of the two-position switches S _a , S _b , S _c of FIG. 1, the transducer of FIG. 3 has five position switches V _a , V _b , V _c . In position 1, these switches connect the outputs of adders B _o , B ₁ , B ₂ to the feedback inputs I _a , I _b , I _c of filter F, respectively. In position 4, these switches connect the outputs of adders B ₃ , B ₄ , B ₅ to their respective feedback inputs. Positions 2, 3 and 5 of these switches are idle.

Parallel of the quantizer output word-serial conversion for a single-bit shift register X _1, and by the X ₂ performed on the quantizer Q _2, a single-bit shift register Y _1, Y _2, a quantizer Q ₃ by Y ₃ Is performed. The second five-position switch W connects the outputs of the shift registers X ₁ , X ₂ , Y ₁ , Y ₂ , Y ₃ to the output O of the converter, respectively. The two five-position switches V and W switch synchronously with a phase shift at rate f _s so that when switch V is in position 1, switch W is in position 4.

The operation of the transducer of FIG. 3 is clarified in FIG. The first row of this figure shows the sequence of clock pulses at rate f _s in which the entire converter of FIG. 3 operates. The vertical stripes in row 4 _b represent the 3-bit output words of quantizer Q ₃ , and the vertical stripes in row 4 _c represent the 2-bit output words of quantizer Q ₂ . Its dotted stripes are output words of Q ₂ and Q ₃ that are not used for generation of the output signal. Row 4 _d shows the output bits at the output O of the converter. 4, the words shown in rows _4b and _4c from which bits of the output signal are derived are shown. Row 4 _e shows a sequence of positions of the 5 position switch V and row 4 _f shows a sequence of positions of the 5 position switch W. FIG.

At position 1 of switch V, two output bits of quantizer Q ₂ are stored in two shift register positions X ₁ a and X ₂ a. At the same time, since the third bit of quantizer Q ₃ is shifted from shift register position Y ₃ b to position Y ₃ c and switch W is in position 4, the second bit of quantizer Q ₃ is shift register position Y ₂ b. Is read from the output O.

In position 2 of switch V, the two Q ₂ bits in shift register positions X ₁ a and X ₂ a are shifted to positions X ₁ b and X ₂ b, respectively. At the same time, since switch W is in position 5, the third bit from quantizer Q ₃ is read into output O from shift register position Y ₃ c.

At position 3 of switch V (= position 1 of switch W), the first bit from Q ₂ is read into output 0 from shift register position X ₁ b and the second bit from Q ₂ is X from position X ₂ b Shifted to ₂ c.

In position 4 of switch V (= position 2 of switch W), the three output bits of quantizer Q ₃ are stored in three shift register positions Y ₁ a, Y ₂ a, Y ₃ a, respectively.

Finally, in position 5 of switch V (= position 3 of switch W), the first Q ₃ bits in position Y ₁ a are read into output O, and the second and third bits are positions Y ₂ a and Y Shift from ₃ a to positions Y ₂ b and Y ₃ b, respectively. Thereafter, the periodic sequence is repeated.

Claims (4)

In a recursive bit-stream converter that converts a multi-bit digital input signal into a single bit digital output signal, In a feedback loop, means (F) for low pass filtering the input signal to generate a digitally filtered word, quantizer means for quantizing the filtered word, and quantized filtered word for feedback means (M ₁ -M). Means for applying to the low pass filtering means (F) via ₁₀ , B ₀ -B ₅ , Outside of the feedback loop, further comprising means for parallel-to-serial converting the quantized filtered words to produce the single bit digital output signal, The quantizer means comprises at least two quantizers Q ₂ , Q ₃ of different bits, the output words of which are successively parallel-to-serial converted (P ₂ , P ₃ ) to produce an output signal O and And are synchronized and continuously applied to the feedback means. Circular Bitstream Converter. The method of claim 1, The quantizer means comprises two quantizers Q ₂ , Q ₃ , wherein the number of bits in one of these quantizers is one unity higher than the number of bits in the other of these quantizers. converter. The method of claim 2, The converter is for use in a coder for a Super Audio CD, the quantizer means (Q ₂ , Q ₃ ) generating one serialized word in the output signal (O) of the converter. And a 2-bit quantizer and a 3-bit quantizer that alternately operate on the cyclic bitstream converter. A method of converting a multiple bit digital input signal into a single bit digital output signal, The input signal is low pass filtered by the row filter means F to be a digitally filtered word, the digital filtered word is quantized by the quantizer means, and feedback means M ₁ -M ₁₀ , B ₀ -B ₅ ) is fed back to the low pass filter means, In the method, the quantized filtered word is converted into the single bit digital output signal by parallel to serial conversion means, The quantizer means comprises at least two quantizers Q ₂ , Q ₃ of different bits, the output words of which are successively outputted by the parallel-to-serial conversion means P ₂ , P ₃ . Parallel-to-serial conversion, and synchronously fed back to the low pass filter means. Signal conversion method.

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