KR20060007240A - Apparatus and method for clock switching - Google Patents

Abstract

The present invention relates to a clock switching apparatus and method.

The clock switching device according to the present invention divides a master clock and outputs a plurality of clock signals having different frequencies, and has a frequency having a maximum common divisor of the frequencies of clock signals output from the first divider. A second division unit for outputting a signal, a synchronization unit for synchronizing a control signal to a synchronization signal, and a selection unit for selecting and outputting one of clock signals output from the first division unit according to the synchronized control signal.

According to the present invention, generation of glitch noise can be suppressed when switching clock signals.

Clock, Switching, Glitch, Divider

Description

Apparatus and method for clock switching

1 is a view showing a conventional clock switching device.

FIG. 2 is a timing chart according to the operation of the clock switching device of FIG. 1.

3 is a diagram illustrating a clock switching device according to an embodiment of the present invention.

4 is an operation timing chart of a clock switching device according to an embodiment of the present invention.

5 is a logic circuit diagram of a clock switching device according to an embodiment of the present invention.

6 is a timing chart according to the operation of the logic circuit of FIG. 5.

7 is a flowchart illustrating a clock switching process according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

310: clock source 320: first divider

330: selection unit 340: second dispensing unit

350: synchronization unit

The present invention relates to a clock switching apparatus and method, and more particularly to a clock switching apparatus and method for preventing the generation of glitches in the switching of the clock signal.

Clock generators are used in the overall circuit design field where clock signals of a certain frequency are required, such as semiconductor fields or industrial electronics fields. In some cases, a clock switching device which divides one master clock into a plurality of clocks and selects and outputs one of the required clocks is used.

1 is a view showing a conventional clock switching device.

The illustrated clock switching device 130 selects and outputs one of a division unit 120 for dividing a master clock output from a clock source 110 and a clock signal divided from the division unit 120. ).

When the master clock having a specific frequency is output from the first clock source 110, the divider 120 divides the master clock and outputs clock signals having the new frequency (clock signals 1 to N).

The clock signals are input to the selector 130, and the selector 130 selects and outputs one of the clock signals. The clock signal to be selected by the selector 130 is determined by a control signal input to the selector 130. Therefore, when a control signal for selecting another clock signal is input to the selector 130 which outputs a specific clock signal, the selector 130 switches the output signal.

In the related art, the control signal is not synchronized with each clock signal input to the selector 130. When the clock signal is switched by the unsynchronized control signal, glitch noise may occur in the output signal, which will be described with reference to FIG. 2.

FIG. 2 is a timing chart according to the operation of the clock switching device of FIG. 1.

The clock signal 1 210 and the clock signal 2 220 are signals generated by the division unit 120 dividing the master clock. The control signal 230 is a signal for controlling the selector 130 to select a specific clock signal. The output signal 240 is a signal that the selector 130 selects and outputs from the clock signal 1 210 and the clock signal 2 220.

According to the illustrated timing chart, the first clock signal 1 210 is selected by the selector 130 and output.

When the control signal 230 for outputting the clock signal 2 220 at the time t1 is input, the selector 130 selects and outputs the clock signal 2 220 from the time t1 (output signal switching). Referring to the output signal 240 output from the selector 130, the clock signal 1 210 and the control signal 230 at the time (time t1) at which the selector 130 switches the output signal 240. It can be seen that the glitch noise 250 having a frequency different from that of the clock signal 2 220 is output.

Since the glitch noise often has frequencies that the device cannot recognize, malfunction of the device may be caused by such glitch noise. Accordingly, a technique for preventing generation of glitch noise in switching output signals has been required.

It is an object of the present invention to prevent the generation of glitch noise when switching clock signals.

The objects of the present invention are not limited to the above-mentioned objects, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a clock signal switching device according to an embodiment of the present invention divides a master clock to output a plurality of clock signals having different frequencies, and divides a predetermined clock signal to divide the clock signal. A second divider for outputting a synchronization signal having a frequency of the greatest common divisor of the frequencies of the signals, a synchronizer for synchronizing a control signal to the synchronization signal, and selecting and outputting one of the clock signals according to the synchronized control signal It includes a selection unit.

In order to achieve the above object, the clock signal switching method according to an embodiment of the present invention by dividing the master clock to output a plurality of clock signals having different frequencies, the frequency of the maximum common divisor of the frequency of the clock signals Outputting a synchronization signal, synchronizing a control signal to the synchronization signal, and selecting and outputting one of the clock signals according to the synchronized control signal.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and those of ordinary skill in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a clock switching device according to an embodiment of the present invention.

The illustrated clock switching device divides a master clock to generate a plurality of clock signals (clock signals 1 to clock signal N), one of the first division unit 320 and clock signals (clock signals 1 to clock signal N). A selector 330 for selecting and outputting a clock signal of a second signal and a clock signal having a frequency equal to a maximum common divisor of the frequencies of the clock signals (clock signals 1 to N) (hereinafter referred to as a synchronization signal) The division unit 340 and the synchronization unit 350 to synchronize the control signal to the synchronization signal.

When the master clock is output from the clock source 310, the first division unit 320 divides the clock signal into clock signals (clock signals 1 to N) having various frequencies.

The second divider 340 divides the master clock to output a synchronization signal. The synchronization signal is a signal that allows the control signal to be synchronized with each clock signal (clock signals 1 to clock signal N) input to the selector 330. To this end, the frequency of the synchronization signal has a maximum common divisor of the frequencies of the clock signals (clock signals 1 to clock signal N) input to the selector 330.

For example, if two clock signals are input to the selector 330, one of which has a frequency of 10 MHz and the other has a frequency of 20 MHz, the second divider 340 has a frequency of 10 MHz which is the greatest common divisor of 10 MHz and 20 MHz. It can be designed to output a synchronization signal having a.

The second dispenser 340 may be designed independently of the first dispenser 320. In this case, the second division unit 340 directly receives the master clock and divides it to output a synchronization signal.

However, the present invention is not limited thereto, and the first dispenser 320 may serve as the second dispenser 340 even if the second dispenser 340 is not designed. For example, when the frequency of the synchronization signal to be output by the second division unit 340 is the same as the frequency of the specific clock signal output from the first division unit 320, the clock signal is input to the synchronization unit 350. The design of the dividing unit 340 can be omitted.

In addition, the second division part 340 may be designed to be dependent on the first division part 320, and one embodiment is shown as the first circuit part 510 and the fourth circuit part 540 of FIG. 5.

The synchronization unit 350 synchronizes the control signal with the synchronization signal output by the second division unit 340. Since the frequency of the synchronization signal is the greatest common divisor of the frequencies of the clock signals input to the selector 330, the control signal synchronized to the synchronization signal may be synchronized to the clock signals input to the selector 330. The selector 330 selects and outputs one of a plurality of input clock signals according to the synchronized control signal.

The control signal may be one or more signals according to the number of clock signals input to the selector 330.

4 is an operation timing chart of a clock switching device according to an embodiment of the present invention.

In the present embodiment and the following embodiments the control signal will be described to be synchronized to the synchronization signal at the rising edge (rising edge) of the synchronization signal, but the present invention is not limited to this, the control signal at the falling edge (falling edge) of the synchronization signal It can also be synchronized.

The clock signal 1 410 and the clock signal 2 420 are signals that the first divider 320 divides and outputs a master clock. The control signal 430 is a signal for controlling the clock signal switching of the selector 330. The synchronization signal 440 is a signal output from the second divider 340 to synchronize the control signal 430 to the clock signals 410 and 420. The synchronized control signal 450 is a signal in which the control signal 430 is synchronized with the synchronization signal 440. The output signal 460 is a signal that the selector 330 selects and outputs from the clock signal 1 410 and the clock signal 2 420 according to the control of the synchronized control signal 450.

As shown, since the frequency of clock signal 1 410 is twice the frequency of clock signal 2 420, the frequency having the greatest common divisor of the two clock signal frequencies is the same as the frequency of clock signal 2 420. Accordingly, the synchronization signal 440 output by the second divider 340 is the same as the clock signal 2 420, and in this case, the first divider 320 takes the role of the second divider 340. You may.

In addition, the output signal 460 illustrated indicates that the selector 330 outputs the first clock signal 1 410.

When the control signal 430 for outputting the clock signal 2 420 is input at the time t1, the synchronizer 350 synchronizes the input control signal 430 with the synchronization signal 440. Since the frequency of the synchronization signal 440 is the greatest common divisor of the frequencies of the clock signals 410 and 420, the control signal 450 synchronized to the synchronization signal 440 may be synchronized to the clock signals 410 and 420. have. Looking at the timing chart shown, it can be seen that the rising edges of the synchronization signals 440 are synchronized with the rising edges of the respective clock signals 410 and 420.

The control signal 430 is output at the time t2 (at the rising edge of the synchronization signal 440) and is output as a synchronized control signal 450. The selector 330 is a clock signal by the synchronized control signal 450. 2 (420) is selected and output.

Referring to the output signal 460 finally output from the selector 330 as shown, the glitch noise as in the prior art (for example, Figure 2) does not occur.

5 is a logic circuit diagram of a clock switching device according to an embodiment of the present invention.

In the illustrated circuit diagram, the first circuit unit 510 and the second circuit unit 520 serve as the first divider 320, the third circuit unit 530 serves as the selector 330, and the fourth circuit unit. The 540 serves as the second divider 340 together with the first circuit 510, and the fifth circuit 550 serves as the synchronizer 350.

The flip-flop included in each circuit represents a D-flop flop.                     

In the input terminal 560, a control signal 1 and a control signal 2 for controlling switching of a preset signal, a clear signal, a master clock, and a clock signal of the third circuit unit 530 to set an initial value of each flip-flop are input. do.

The operation of the circuit diagram shown will be described with the timing chart of FIG.

Clock signal 1 610 is the same signal as the master clock.

The first circuit unit 510 divides the master clock to output a clock signal 3 630 whose frequency is 1/3 of the master clock. On the other hand, the second circuit unit 520 divides the master clock and outputs a clock signal 2 620 having a frequency 1/2 of the master clock. For example, when the master clock is a 27 MHz signal, the first circuit unit 510 outputs a 9 MHz clock signal and the second circuit 520 outputs a clock signal of 13.5 MHz.

Three clock signals 610 to 630 are input to the third circuit unit 530, and the third circuit unit 530 selects and outputs one clock signal according to the control signal 1 640 and the control signal 2 650. do. Table 1 shows the output signal output from the third circuit unit 530 according to each control signal (640.650).

Table 1

Control signal 1 Control signal 2 Output signal Low Low Clock signal 3 Low Low Clock signal 2 High Low Clock signal 1

Meanwhile, since the signal having the frequency of the greatest common divisor of the frequencies of the clock signals 610 to 630 input to the third circuit unit 530 is a signal equal to 1/6 of the master clock frequency, the second division unit 340 is a master. The clock must be divided by 1/6. To this end, the logic circuit shown in FIG. 1 divides the clock signal 630 divided by 1/3 of the master clock by the first circuit unit 510 into 1/2 again by the fourth circuit unit 540. Therefore, the synchronization signal 660 divided by the fourth circuit unit 540 becomes a clock signal obtained by dividing the master clock by 1/6. That is, when the master clock is a 27 MHz signal, the synchronization signal 660 becomes 4.5 MHz.

As such, the second dispenser 340 may be designed to be dependent on the first dispenser 320.

The fifth circuit unit 550 synchronizes the control signal 1 640 and the control signal 2 650 with the synchronization signal 660. Referring to the illustrated timing chart, since the first control signal 1 640 is high and the control signal 2 650 is low, the output signal 690 becomes the clock signal 1 610.

When the control signal 1 630 is turned low so that the third circuit unit 530 outputs the clock signal 3 630 at time t1, the fifth circuit unit 550 is at the rising edge of the synchronization signal 660. (Time t2) synchronize it. Accordingly, the synchronized control signal 1 670 is input to the third circuit unit 530 to switch the output signal at time t2. That is, the output signal 690 is switched to the clock signal 3 (630) from time t2.

According to the illustrated timing chart, in order to switch the output signal 690 to the clock signal 2 620, the control signal 2 650 is turned high at time t3. The fifth circuit portion 550 also synchronizes on the rising edge of the synchronization signal 660 (time t4). Accordingly, the synchronized control signal 2 680 is input to the third circuit unit 530 to switch the output signal at time t4.

As described above, according to the present invention, the glitch noise as described above does not occur when the output signal is switched.

7 is a flowchart illustrating a clock signal switching process according to an embodiment of the present invention.

When the first master clock is input (S110), the first division unit 320 divides it and outputs a plurality of clock signals having different frequencies (S120). Each clock signal is input to the selector 330.

Meanwhile, the second divider 340 outputs a synchronization signal having a frequency of a maximum common divisor of the frequencies of the clock signals input to the selector 330 (S130). The synchronization signal may be generated by directly dividing the master clock, or may be generated by dividing some of the clock signals output from the first division unit 320.

When a control signal for controlling the selector 330 to select and output a specific clock signal is input (S140), the synchronizer 350 synchronizes the input control signal with the synchronization signal. The control signal synchronized with the synchronization signal may be synchronized with each clock signal input to the selector 330, and the selector 330 selects and outputs a specific clock signal according to the synchronized control signal (S160).

Specific operations according to each step of the illustrated process have already been described with reference to FIGS. 3 to 6.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You can understand that there is. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the clock switching apparatus and method of the present invention as described above it is possible to suppress the generation of glitch noise when switching the clock signal.

Claims (4)

A first divider for dividing the master clock to output a plurality of clock signals having different frequencies; A second divider for dividing a predetermined clock signal to output a synchronization signal having a frequency of a maximum common divisor of the frequencies of the clock signals; A synchronization unit for synchronizing a control signal with the synchronization signal; And And a selector configured to select and output one of the clock signals according to the synchronized control signal. The clock switching device of claim 1, wherein the synchronization signal is generated by dividing a clock signal output from the master clock or the first divider. Dividing the master clock to output a plurality of clock signals having different frequencies; Outputting a synchronization signal having a frequency of a maximum common divisor of the frequencies of the clock signals; Synchronizing a control signal to the synchronization signal; And Selecting and outputting one of the clock signals according to the synchronized control signal. The clock switching method of claim 3, wherein the synchronization signal is generated by dividing a clock signal divided from the master clock or the master clock.

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