KR20060002110A - Frequency synthesizer having the ultra-fast switching characteristic - Google Patents

Abstract

Using a programmable divider and digital-to-analog converter (DAC) control circuit, a frequency with ultra-fast switching characteristics for synchronizing with the reference frequency whenever the input division command changes, enabling frequency synthesis with ultra-fast switching operation. A synthesizer is disclosed. Frequency synthesizer according to the present invention can be widely used in communication, electronics, medical, circuits, measuring instruments, etc. requiring high-speed frequency synthesis, ultra-high speed information communication applying frequency hopping in the communication or electronics industry It will be widely used in the field and can be very useful as the most important device in the fast frequency-hopping spread spectrum system which is the most representative of military communication to withstand radio interference.

Description

Frequency Synthesizer having the Ultra-fast Switching Characteristic}

1 is a system block diagram showing the structure of a frequency synthesizer with ultrafast switching characteristics according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a digital-to-analog converter (DAC) control circuit in FIG. 1.

3 is a block diagram illustrating timing synchronization in a frequency synthesizer having ultrafast switching characteristics according to the present invention.

4 is a waveform diagram of the computer simulation result when there is no synchronization circuit in the frequency synthesizer according to the present invention.

5 is a waveform diagram of a computer simulation result when a synchronization circuit is formed in the frequency synthesizer according to the present invention.

 6 is a graph illustrating voltage waveforms according to various frequency synthesizing commands in the frequency synthesizer according to the present invention.

7 is a voltage comparison waveform of a frequency synthesizer and a general closed frequency synthesizer according to the present invention.

<Description of the code for the main part>

112: phase detector 113: charge pump

114 loop filter 115 adder

116: voltage controlled oscillator 208: programmable divider

211: digital-to-analog converter (DAC) control circuit 213: digital-to-analog converter (DAC)

214: synchronous circuit 215, 216: D-flip flop

217 detection unit 218 digital adder

219: digital subtractor 222: duty ratio converter

223: MUX

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer having an ultra-fast switching characteristic. In particular, a programmable frequency divider and a digital-to-analog converter (DAC) control circuit are used to synchronize the reference frequency with each change of an input division command so as to synchronize with a reference frequency. The present invention relates to a frequency synthesizer having an ultra-fast switching characteristic for enabling frequency synthesis.

In general, a frequency synthesizer is classified into a closed frequency synthesizer and an open structure. A frequency synthesizer using a phase locked loop (PLL) is not only a typical frequency synthesizer in a closed loop, but also the most widely used method, and is most excellent in price, variety and flexibility. In addition, spurious noise is relatively low compared to other methods. However, the switching speed is low due to the closed structure.

An open loop frequency synthesizer is a method of generating a desired frequency by directly applying a digital frequency synthesis command to a voltage controlled oscillator (VCO). That is, in the open frequency synthesizer, when the frequency synthesis command is applied to the digital-to-analog converter (DAC) via a digital-to-analog converter (DAC) control circuit, the voltage corresponding to the synthesis command is loop filtered. In addition to the voltage of, it drives the voltage controlled oscillator. The digital-analog converter control circuit is a circuit for controlling the voltage versus frequency relationship of the voltage controlled oscillator. Thus, the frequency synthesizing command becomes the voltage information corresponding thereto by the digital-to-analog converter (DAC) control circuit, and is again output by the digital-to-analog converter (DAC) to the desired voltage. Thus, each time a new synthesis command comes in, it can switch at high speed.

Since this method is not closed loop type, it can operate at high speed, but it is very unstable in terms of stability, so it is difficult to use it because of large phase noise and frequency offset.

However, the structure of the closed frequency synthesizer alone is limited in terms of switching speed, and even though the loop filter parameters are optimized, there is a trade-off between overshoot and settling time. There is a problem that the ultra-fast switching operation is difficult. In other words, as the overshoot increases, the settling time decreases, but the phase noise increases, resulting in loss of frequency stability. On the other hand, reducing the overshoot can reduce the phase noise and produce a stable frequency, but the fast settling time is difficult due to the increased settling time.

The present invention has been invented to solve the above problems, in designing a frequency synthesizer, an open loop form of synthesizing frequency at a very high speed by directly applying a digital frequency synthesis command to a voltage controlled oscillator (VCO). The purpose of the present invention is to provide a frequency synthesizer having a super fast switching characteristic that synthesizes the frequency at a stable and ultra high speed by using a frequency synthesizer method mixed with a phase locked loop (PLL) which is a stable closed frequency synthesizer. do.

The present invention for achieving the above object;

A phase detector 112 for receiving a reference frequency and a synchronization signal and detecting a phase difference between the two signals; A charge pump 113 for outputting the signal output from the phase detector 112 as one signal; A loop filter 114 formed at an output side of the charge pump 113 and configured to pass only a low band signal; A frequency synthesizer formed at the output side of the loop filter 114 and including an adder 115 for adding and outputting an input signal and a voltage controlled oscillator 116 for outputting a required frequency band connected to the output side of the adder 115. To

A programmable divider 208 which receives a frequency synthesizing command and divides a desired output frequency by a program by the value of the frequency synthesizing command;

A DAC control circuit that detects a time point at which the frequency synthesis command is changed by receiving the frequency synthesis command, accumulates the difference between the control signal and the previously inputted frequency synthesis command and the current input frequency synthesis command, and outputs the control signal accordingly. 211;

When the frequency synthesizing command is not changed by the control signal of the DAC control circuit 211, the signal divided by the programmable divider 208 is transmitted to the phase detector 112 to initialize the frequency dividing counter, and the frequency synthesizing command is changed. At a time point, a synchronization circuit 214 for transmitting a signal synchronized with the reference frequency to the phase detector 112 and the programmable divider 208; And

And a DAC 213 for receiving a control signal from the DAC control circuit 211 and outputting a DC voltage corresponding to the accumulated value of the frequency synthesizing command to the voltage controlled oscillator 116.

Here, the DAC control circuit 211 includes an XOR gate detecting unit 217 for detecting a point of time when the frequency synthesizing command changes and transmitting it to the synchronization circuit 214; A first D-flip-flop 215 connected to an output terminal of the detector 217 to transmit an input frequency synthesis command to the digital subtractor 219 when the output of the detector 217 is turned on; A digital adder 218 for adding an input frequency synthesis command and a signal transmitted to the DAC 213; A second value for transferring to the DAC 213 the output of the detector 217 when the output of the digital adder 218 is subtracted from the frequency synthesis command in the previous state, which is the output of the first D-flop flop; And D-flip-flop 216.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a system block diagram showing the structure of a frequency synthesizer having ultrafast switching characteristics according to the present invention, and FIG. 2 is a block diagram showing the configuration of a digital-to-analog converter (DAC) control circuit in FIG. In addition, when the division command is changed, an additional voltage applied to the voltage controlled oscillator is applied at a very high speed. FIG. 3 is a voltage control circuit and a frequency added to a general closed frequency synthesizer in a frequency synthesizer having an ultrafast switching characteristic according to the present invention. A block diagram for explaining timing synchronization according to the synthesis instruction.

The frequency synthesizer according to the present invention is a voltage controlled oscillator (VCO) 116 of a phase locked loop (PLL) 100 used in a frequency synthesizer of a closed loop as shown in FIG. Is combined with a digital-to-analog converter (hereinafter referred to as DAC) control circuit 211 used in an open frequency synthesizer and an open structure driven through the DAC 213 to achieve stable and ultra-fast frequency synthesis. It is to provide a hybrid frequency synthesizer.

That is, referring to FIG. 1, the frequency synthesizer according to the present invention is configured such that a reference frequency is input to a phase detector 112 and a synchronization circuit 214. As the phase detector 112, a '3-state frequency phase detector' is used, and the phase detector 112 calculates a phase difference between the input reference frequency and the two digital input signals output from the synchronization circuit 214, thereby increasing the phase difference. The Up or Down signal is output to the charge pump 113. The charge pump 113 serves to make the signal output from the phase detector 112 into one signal and is composed of a complementary metal oxide semiconductor (CMOS). The loop filter 114 formed on the output side of the charge pump 113 is a secondary low-pass filter composed of an analog passive element R and a capacitor C during output of the charge pump 113. Pass only low-band signals. The adder 115 formed on the output side of the loop filter 114 is an analog adder designed as an operational amplifier, and the output of the loop filter 114 and the output of the DAC 213 are added to the voltage controlled oscillator (VCO) 116. ) To output the desired frequency. In a typical closed frequency synthesizer, the voltage output of the loop filter in which the voltage rise and fall time occupies most of the input voltage settling time when the frequency division command changes in the frequency control oscillator (VCO) 116 frequency output. Determined by However, in the ultra-high frequency synthesizer according to the present invention, since the voltage increase or decrease is directly input from the DAC 213 through the DAC control circuit 211 through the adder 115, the voltage rise and fall time can be reduced.

In the frequency synthesizer according to the present invention, a frequency synthesizing command is simultaneously input to the programmable divider 208 and the DAC control circuit 211. Will be divided by the value of. The frequency synthesizing command input to the DAC control circuit 211 is converted into a DC voltage by the DAC 213. Here, the synchronization circuit 214 formed at the output terminal of the DAC control circuit 211 has a phase detector (PB) that divides the signal divided by the programmable divider 208 in the same frequency synthesis command section by the control signal of the DAC control circuit 211. 112 as it is, and when the frequency synthesizing command is changed, the frequency division counter is initialized to transmit a signal synchronized with the reference frequency to the phase detector 112 and the programmable divider 208.

If the synchronization process is not considered, the phase difference generated by the wrong division counter at the time when the frequency synthesizing command is changed increases the settling time of the voltage input to the voltage controlled oscillator 116. However, by the synchronization process of the ultra-high frequency synthesizer according to the present invention it is possible to eliminate the phase difference caused by the wrong division counter.

Here, as shown in FIG. 2, the DAC control circuit 211 for calculating a difference value of the frequency synthesis command and generating a voltage according thereto may transmit a time point at which the input frequency synthesis command changes to the detector 217 configured as an XOR gate. It detects and transfers it to the synchronization circuit 214. That is, the first D-flip flop (hereinafter referred to as D-FF) 215 connected to the output terminal of the detector 217 may execute the inputted frequency synthesis command when the output of the detector 217 is turned on. Pass to digital subtractor 219. In addition, the digital adder 218 adds the current frequency synthesizing command and the signal transmitted to the DAC 213, and the second D-FF 216 subtracts the frequency synthesizing command of the previous state from the output of the digital adder 218. To the DAC 213. When the output of the detector 217 is turned on, the second D-FF 216 transfers the output of the digital subtractor 219 to the DAC 213. Therefore, the DAC control circuit 211 accumulates the difference between the previously inputted frequency synthesizing command and the current frequency synthesizing command, and the DAC 213 operating under the control of the DAC control circuit 211 operates at the frequency. The DC voltage corresponding to the accumulated value of the change amount of the synthesis command is output.

In addition, the synchronization circuit for generating a synchronization signal in the frequency synthesizer according to the present invention, as shown in Figure 3, the duty ratio for changing the duty ratio of the reference frequency (duty ratio) from 50% to about 90% as input to the reference frequency A MUX 223 is formed on the output side of the converter (Duty ratio converter 222.) The signal of the detector 217 of the DAC control circuit 211, which determines whether or not the frequency synthesizing command is changed, is a D-FF ( 221. When a signal indicating that the frequency synthesizing command is changed by the detector 217 is input to the 'preset' of the D-FF 221, the select terminal of the Mux 223 becomes High. The output of the duty ratio converter 222 is input to the phase detector 112. In addition, the output of the D-FF 221 becomes low and the Mux 223 is programmable in a situation where the frequency synthesizing instruction does not change. The output of divider 208 is passed to phase detector 112.

The frequency synthesizer according to the present invention combines an open structure with fast switching characteristics in the stability of a phase locked loop (PLL). When the steady state is reached by the initial frequency synthesis command, the voltage of the loop filter actually increases or decreases slightly, but does not change any more. This is because the voltage required in the process of changing the frequency synthesis command is provided by the auxiliary voltage provided by the DAC 213. To generate this auxiliary voltage, an appropriate digital word value must be applied to the DAC 213. In the present invention, the input value of the DAC 213 is calculated using the DAC control circuit 211 as shown in FIG. 2 to control the DAC 213. In other words, the input voltage added through the adder 115 in the DAC 213 through the DAC control circuit 211 to reduce the voltage rise and fall time that occupies most of the input voltage settling time when the division command changes. Because it directly inputs, voltage rise and fall time can be reduced. In addition, the overshoot may be reduced by using the synchronization circuit 214 associated with the DAC control circuit 211 to remove the phase difference due to the wrong division occurring when the frequency synthesis command changes.

, D/A 컨버터 인가전압은 5.12V로 설정하였다.This structure of the present invention is intended to minimize overshoot and settling time that occur in a closed loop. That is, the internal counter of the programmable divider maintains and counts the value before the change even when the frequency synthesis instruction changes. Thus, when the frequency synchronizing instruction changes, the synchronization block initializes the counter of the programmable divider to suppress the generation of phase difference. Computer simulations were performed to show the operating characteristics of the frequency synthesizer of the present invention. The experimental conditions are the reference frequency 100kHz, the gain of the voltage controlled oscillator is 5MHz / V, the gain of the phase detector is 1mA / 2, the natural frequency ω _n is 1kHz, and the braking factor ζ is 1 /.

, D / A converter applied voltage was set to 5.12V.

  4 is a waveform diagram of the computer simulation result when there is no synchronization circuit in the frequency synthesizer. In the drawing, 'SEL' is the select input of the Mux 223 inside the synchronization block, 'IN' is the digital waveform input from the voltage controlled oscillator to the programmable divider 208, and 'V_in' is the phase detector 112. Input, 'V_ref' is the reference frequency. When the frequency synthesis command changes from 50 to 100, as shown in FIG. 4, the output waveform of the VCO is divided 50 times, and at the next 25 times, the synthesis command changes to further divide 100-25 = 75 times. It was. Therefore, a large time difference from V_ref (reference frequency) causes a phase difference, and the input voltage of the VCO causes an overshoot, which leads to a long time to reach a steady state.

  FIG. 5 is a simulation result when a synchronization circuit is formed in a frequency synthesizer, and is set and observed in the same manner as the experimental environment of FIG. 4. If the dispense command is changed after dispensing the output of the VCO 50 times, the dispensing is completed and restarted at the point synchronized with the reference frequency regardless of the frequency of dispensing during this time.

  6 is a waveform illustrating the input voltage (top) of the VCO and the output voltage (bottom) of the D / A converter in order to observe the switching time using the synchronous circuit as shown in FIG. 5. As shown in the figure, when the frequency synthesis command changes, the D / A converter provides the corresponding voltage and the VCO's input voltage is immediately shifted to the voltage corresponding to the synthesis command. That is, it can be seen that the frequency to be generated is immediately output to the input frequency synthesis command.

 Figure 7 is a waveform comparing the VCO input voltage of the general closed frequency synthesizer (top) and the frequency synthesizer (bottom) according to the present invention. As shown in the figure, when the frequency synthesizing command is changed, in the conventional closed frequency synthesizer, the settling time of the corresponding VCO input voltage is long due to the characteristic of the closed structure, whereas the switching function is slow, whereas in the frequency synthesizer according to the present invention, D / By the voltage compensation of the A converter, it can be confirmed that it is short and operates at a very high speed. In other words, ultra-fast frequency synthesis is possible.

The frequency synthesizer according to the present invention can be widely used in communication, electronics, medical, circuits, instruments, and the like, which require high-speed frequency synthesis. In particular, it will be widely used in the field of high-speed information communication that uses frequency hopping in the communication or electronics industry, and in the fast frequency-hopping spread spectrum system, which is the most representative of military communication to withstand radio interference. As the most important device can be used very usefully.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be improved or modified by those skilled in the art within the scope of the technical idea of the present invention.

Claims (2)

A phase detector 112 for receiving a reference frequency and a synchronization signal and detecting a phase difference between the two signals; A charge pump 113 for outputting the signal output from the phase detector 112 as one signal; A loop filter 114 formed at an output side of the charge pump 113 and configured to pass only a low band signal; An adder 115 formed at an output side of the loop filter 114 and connected to an output side of the adder 115 for outputting an input signal, and a voltage controlled oscillator 116 for outputting a required frequency band; In frequency synthesizer, A programmable divider 208 which receives a frequency synthesizing command and divides a desired output frequency by a program by the value of the frequency synthesizing command; A DAC control that detects a time point at which the frequency synthesis command is changed by receiving the frequency synthesis command, accumulates a difference between the control signal and a previously inputted frequency synthesis command and a current input frequency synthesis command, and outputs a control signal accordingly. Circuit 211; When the frequency synthesizing command does not change according to the control signal of the DAC control circuit 211, a signal divided by the programmable divider 208 is transmitted to the phase detector 112 to initialize the frequency dividing counter. A synchronizing circuit 214 for transmitting a signal synchronized with the reference frequency to the phase detector 112 and the programmable divider 208 at the time the synthesis command changes; And Ultra fast switching, characterized in that it comprises a DAC (213) for receiving the control signal of the DAC control circuit 211 and outputs a DC voltage corresponding to the accumulated value of the frequency synthesis command to the voltage control oscillator 116 Frequency synthesizer with characteristics. 2. The apparatus of claim 1, wherein the DAC control circuit (211) comprises an XOR gate detecting unit (217) for detecting a point of time at which the frequency synthesizing command changes and transmitting it to the synchronization circuit (214); A first D-flip-flop 215 connected to an output terminal of the detector 217 to transfer an inputted frequency synthesis command to the digital subtractor 219 when the output of the detector 217 is turned on; A digital adder 218 for adding an input frequency synthesis command and a signal transmitted to the DAC 213; If the output of the detector 217 is turned on, the value obtained by subtracting the frequency synthesis command of the previous state, which is the output of the first D-flip-flop, from the output signal of the digital adder 218 is transmitted to the DAC 213. And a second D-flip-flop (216) for the frequency synthesizer with ultra-fast switching characteristics.

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