KR20060001086A - An internal signal generator for a semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal signal generator of a semiconductor memory. In particular, a control signal for a read / write operation generated by a signal input from an external controller is controlled by a signal indicating an active state of the memory. If not, the present invention relates to an internal signal generator that does not generate a control signal for read / write operation.

Description

An internal signal generator for a semiconductor memory

1 shows a conventional internal signal generator for a semiconductor memory.

2 shows an internal signal generator for a semiconductor memory according to the present invention.

3A shows a signal waveform according to the operation of a conventional circuit.

Figure 3b shows a signal waveform according to the operation of the circuit of the present invention.

Explanation of symbols on main parts of drawing

200: decoding unit

210: latch type voltage generator

220: output driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal signal generator of a semiconductor memory. In particular, a control signal for a read / write operation generated by a signal input from an external controller is controlled by a signal indicating an active state of the memory. If not, the present invention relates to an internal signal generator that does not generate a control signal for read / write operation.

In general, a conventional internal signal generator receives a plurality of signals input from an external controller and outputs a read / write related control signal regardless of an active state of a memory cell.

Hereinafter, a detailed description will be made with reference to FIG. 1, which illustrates a conventional internal signal generator for a semiconductor memory.

In FIG. 1, in0, in1, in2, and in3 represent signals of signals such as / CS or CS, / RAS or RAS, / CAS or CAS, and / WE or WE, which are input from an external controller, and output signals of an internal signal generator. Out1 indicates pulsed read / write related control signal generated by enable when CASP6_RD: read command, enable when WTP6: write command, enable when CASP6: read or write.

The internal signal generator of FIG. 1 includes a decoder 100 for receiving input signals in0, in1, in2, and in3 input from an external controller, and a latch-type voltage generator 110 for receiving an output signal of the decoder 100. And an output driver 120 for receiving the output signal of the latch type voltage generator 110 and outputting the delayed signal.

The decoding unit 100 includes a first end means 101 for receiving two external input signals in0 and in1, and a second end means 102 for receiving two external input signals in2 and in3. Receives output signals of the first NAND gate 103 and the first NAND gate 103 for receiving the output signals of the first and second means 101 and the second end means 102, and outputs the first output signal in. And a transmission gate 105 which receives the output signals of the inverter 104 and the first NAND gate 103 and outputs the inverted second output signal inb of the first output signal in.

The latch type voltage generator 110 includes a first PMOS transistor 111, a first NMOS transistor 112, a second NMOS transistor 113, and a third NMOS transistor 114 that are configured in series between a power supply voltage VDD and a ground VSS. Equipped with

A second PMOS transistor 115, a fourth NMOS transistor 116, and a fifth NMOS transistor 117 are provided between the power supply voltage VDD and the connection node of the second NMOS transistor 113 and the third NMOS transistor 114. .

The connection node of the first PMOS transistor 111 and the first NMOS transistor 112 is the first output node, and the connection node of the second PMOS transistor 115 and the fourth NMOS transistor 116 is the second output node. A third PMOS transistor 118 is provided between the VDD and the first output node, and a fourth PMOS transistor 119 is provided between the power supply voltage VDD and the second output node.

The first output node is connected to the common gate of the second PMOS transistor 115 and the fourth NMOS transistor 116, and the second output node is connected to the common gate of the first PMOS transistor 111 and the first NMOS transistor 112.

The output driver 130 is composed of an inverter chain composed of an even number of inverters, and receives a read / write related control signal out1 of the second output node and outputs the delayed signal.

In operation, the four input signals (in0, in1, in2, in3) are respectively output to the first and second output signals in and out of phase having a high level or a low level through the decoding unit 100 and the second. Output the output signal inb.

The latch type voltage generator 110 receives the enable signal clkp2 to the gate of the third NMOS transistor 114 and operates the circuit normally. The latch type voltage generator 110 receives the first output signal in to the gate of the fifth NMOS transistor 117. The second output signal inb is received through the gate of the second NMOS transistor 113.

When the low level enable signal clkp2 is input, the third PMOS transistor 118 and the fourth PMOS transistor 119 that receive the enable signal clkp2 are turned on to turn the first output node and the second output node high level. Keep it at

When the high level enable signal clkp2 is input, the latch type voltage generator 110 operates normally. When the first output signal in is high level and the second output signal is low level, the fourth NMOS transistor When 116 and the fifth NMOS transistor 117 are turned on to transition the second output node to a low level, the first output signal in is at a low level, and the second output signal inb is at a high level, The first NMOS transistor 111 and the second NMOS transistor 112 are turned on to transition the first output node to a low level.

Any pulse output to the second output node by the operation is used as the read / write related control signal out1 and is output after a delay through the inverter provided in the output driver 120.

The above-described read / write operation should be performed in the active state of the memory. However, in the related art, when the input signals in0, in1, in2, and in3 are input even when the memory is not in the active state, the read / write related control signal out1 is generated.                         

This operation also affects the performance of the read / write operation after the transition from the idle state to the active state, causing a problem of potential failure.

The present invention has been proposed to solve the above-mentioned problem, and the control signal for read / write operation output from the internal signal generator is subjected to the control of a signal indicating the active state of the memory so that the read / when the memory is not active. An internal signal generator for preventing a control signal for writing operation is provided.

An internal signal generator of a semiconductor memory according to an embodiment of the present invention includes a decoding unit for receiving a plurality of signals input from an external controller, a latch type voltage generator for receiving an output signal of the decoding unit, and outputting a read / write related control signal; An output driver, the output driver operates by a control signal, and selectively outputs an output signal of the latch type voltage generator input according to a state of the control signal, and the output driver is configured to output the latch type voltage generator A first inverter for receiving an output signal and an end means for receiving the output signal and the control signal of the first inverter, and outputting the latch-type voltage generator by the control signal in the disabled state when the memory is active; Pass the signal, and the control of the enabled state if the memory is idle A control signal input to the output driver has a high level in the disable state, a low level in the disable state, and is present in each bank of the memory; The signal is enabled by the active signal and is disabled when the signal disabled by the precharge signal is enabled.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates an internal signal generator for a memory device according to the present invention.

The internal signal generator of the present invention includes a decoding unit 200 for receiving input signals in0, in1, in2, and in3 input from an external controller, and a latch type voltage generator 210 for receiving an output signal of the decoding unit 200. And an output driver 220 for selectively outputting the output signal of the latch type voltage generator 210.

The decoding unit 200 includes a first end means 201 for receiving two external input signals in0 and in1 and a second end means 202 for receiving two external input signals in2 and in3. Receives output signals of the first NAND gate 203 and the first NAND gate 203 that receive the output signals of the first and second means 201 and the second end means 202 and outputs the first output signal in. And a transmission gate 205 which receives the output signals of the inverter 204 and the first NAND gate 203 and outputs the inverted second output signal inb of the first output signal in.

The latch type voltage generator 210 includes a first PMOS transistor 211, a first NMOS transistor 212, a second NMOS transistor 213, and a third NMOS transistor 214 that are configured in series between a power supply voltage VDD and a ground VSS. Equipped with                     

A second PMOS transistor 215, a fourth NMOS transistor 216, and a fifth NMOS transistor 217, which are configured in series between the power supply voltage VDD and the connection node of the second NMOS transistor 213 and the third NMOS transistor 214. .

The connection node of the first PMOS transistor 211 and the first NMOS transistor 212 is the first output node, the connection node of the second PMOS transistor 215 and the fourth NMOS transistor 216 is the second output node, the power supply voltage A fourth PMOS transistor 219 is further provided between the VDD and the first output node, and between the third PMOS transistor 218 and the power supply voltage VDD and the second output node.

The first output node is connected to the common gate of the second PMOS transistor 215 and the fourth NMOS transistor 216, and the second output node is connected to the common gate of the first PMOS transistor 211 and the first NMOS transistor 212.

The output driver 220 includes an inverter 221 that receives the output signal of the latch type voltage generator 210 and an end means 222 that receives the output signal and the control signal rasriedb of the inverter 221.

The control signal rasidleb input to the output driver 220 has active information and precharge information of the semiconductor memory, has a disable state having a high level when the active state is active, and has a low level when the precharge is idle. It has an enable state and is present in each bank of the memory and is disabled when any one of the signals (rast10) that are enabled by the active signal and disabled by the precharge signal is enabled.

In operation, the four input signals (in0, in1, in2, in3) are respectively output to the first and second output signals in and out of phase having a high level or a low level through the decoding unit 200 and the second. Output the output signal inb.

The latch type voltage generator 210 receives the enable signal clkp2 to the gate of the third NMOS transistor 214 and operates the circuit normally. The latch type voltage generator 210 receives the first output signal in to the gate of the fifth NMOS transistor 217. The second output signal inb is received through the gate of the second NMOS transistor 213.

When the low level enable signal clkp2 is input, the third PMOS transistor 218 and the fourth PMOS transistor 219 which receive the enable signal clkp2 are turned on to turn the first output node and the second output node high level. Keep it at

When the high level enable signal clkp2 is input, the latch type voltage generator 210 operates normally. When the input first output signal in is high level and the second output signal is low level, the fourth NMOS transistor is applied. 216 and the fifth NMOS transistor 217 are turned on to transition the second output node to a low level, the first output signal in is at a low level, and the second output signal inb is at a high level. The first NMOS transistor 211 and the second NMOS transistor 212 are turned on to transition the first output node to a low level.

The read / write related control signal out2 outputted to the second output node by the operation is input to the output driver 220, so that the output driver 220 has a high level control signal, that is, the semiconductor memory is active. In this state, the exit signal out2 of the latch-type voltage generator 220 is passed through the end means 222, and the control signal rasileb is low level, that is, an idle state in which the semiconductor memory is in a precharge state. , The output signal out2 of the latch type voltage generator 220 is cut off.

Next, after examining the difference between the conventional circuit and the circuit of the present invention, the superiority of the circuit of the present invention will be described.

While the conventional circuit shown in FIG. 1 is not controlled by a signal having active information, in the case of the present invention shown in FIG. 2, a control signal (rasidleb) having active information is received by the output driver 220 to receive a control signal. Output signal is output only in the active state.

3A and 3B show signal waveforms of the conventional circuit and the circuit of the present invention.

3A illustrates a signal waveform according to the operation of a conventional circuit, and it can be seen that the output signal out1 is output by the input signals in0, in1, in2, and in3 regardless of the active state of the memory. .

3B illustrates a signal waveform according to the operation of the circuit of the present invention. As shown in FIG. 3B, the input signals in0, in1, in2, and in3 are only provided when the rasleb having the active information is at a high level. The output signal out2 is output by

Due to this difference, the circuit of the present invention does not output a read / write related signal in the idle state, so that the read / write operation in the next active state can be smoothed.

As can be seen from the above, in the case of using the internal signal generator according to the present invention, the read / write related signals generated in the idle state of the memory are blocked and the read / write operation is performed only in the active state. Provides read / write operation.

Claims (5)

A decoder for receiving a plurality of signals input from an external controller and an internal signal generator for a memory device including a latch type voltage generator and an output driver for receiving output signals of the decoder and outputting read / write related control signals. In The output driver is operated by a control signal, And an output signal of the latch type voltage generator which is input according to the state of the control signal. The method of claim 1, The output driver A first inverter for receiving an output signal of the latch type voltage generator, an end means for receiving an output signal of the first inverter and the control signal,  If the memory is active, the output signal of the latch-type voltage generator is passed by the control signal in the disabled state. If the memory is in the idle state, the output signal of the latch-type voltage generator is blocked by the control signal in the enabled state. Internal signal generator, characterized in that. The method according to claim 1 or 2, The control signal input to the output driver is Has a high level when disabled, has a low level when enabled, And an internal signal generator, which is present in each bank of the memory and is enabled by an active signal and is disabled when a signal disabled by the precharge signal is enabled. The method of claim 1, The decoding unit First end means for receiving two signals input from the external controller and second end means for receiving another two signals; A first NAND gate configured to receive output signals of the first and second means; 3 An inverter configured to receive an output signal of the first NAND gate and output a first output signal; And a transmission gate receiving the output signal of the first NAND gate and outputting an inverted second output signal of the first output signal. The method of claim 1, The latch type voltage generator includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor configured in series between a power supply voltage and a ground. A second PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor configured in series between the power supply voltage and the connection node of the second NMOS transistor and the third NMOS transistor; A connection node of the first PMOS transistor and the first NMOS transistor is a first output node, a connection node of the second PMOS transistor and the fourth NMOS transistor is a second output node, And further comprising a third PMOS transistor between the power supply voltage and the first output node and a fourth PMOS transistor between the power supply voltage and the second output node. The first output node is connected to the common gate of the second PMOS transistor and the fourth NMOS transistor, The second output node is connected to the common gate of the first PMOS transistor and the first NMOS transistor, Enable the gate of the third NMOS transistor and the third PMOS transistor and the fourth PMOS transistor, receive a first output signal of the decoding unit to a gate of the fifth NMOS transistor, and receive the first output signal of the decoding unit into a gate of the second NMOS transistor Receiving a second output signal. And the second output node is connected to an input terminal of the output driver.

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