KR20060000899A - Method for fabricating semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a process of forming MOS transistors and landing plug contacts in a semiconductor memory device manufacturing process, and more particularly, to a process of forming a gate electrode sidewall spacer. The present invention provides a method of manufacturing a semiconductor memory device capable of securing a gap fill margin of an interlayer insulating film (landing plug contact oxide) deposited after the gate electrode pattern is formed while maintaining the gap fill capability level and cell spacer thickness of the current interlayer insulating film deposition process. The purpose is to provide. The present invention proposes a method of performing the cell spacer insulating film deposition process after the deposition of the interlayer insulating film (landing plug contact oxide film) deposited after the gate electrode pattern formation. In this case, since the landing plug contact oxide film deposition process is performed while the cell spacer insulating film is not deposited, a space corresponding to twice the thickness of the cell spacer insulating film can be secured, and thus a gap fill margin when the landing plug contact oxide film is deposited. Can be secured.

Gate electrode, cell spacer insulating film, landing plug contact, interlayer insulating film, gap fill

Description

Method of manufacturing semiconductor memory device {METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE}             

1A to 1G are cross-sectional views (cell regions) showing a DRAM manufacturing process according to the prior art.

2A to 2G are cross-sectional views (cell regions) showing a DRAM manufacturing process according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

27: gate spacer oxide film

28: gate spacer nitride film

29: cell spacer nitride film

30: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a process of forming MOS transistors and landing plug contacts in a semiconductor memory device manufacturing process, and more particularly, to a process of forming a gate electrode sidewall spacer.

Recently, as the design rules of semiconductor memory devices are rapidly reduced to the level of 100 nm or less, the line width of the gate electrode and the space between the gate electrodes are also significantly reduced.

As a result, doped polysilicon, which has been widely used as a traditional gate electrode material, has shown its application limit due to its high resistance value, and has applied silicide / polysilicon or metal / polysilicon stack structure. That is, the height of the gate electrode itself is inevitably increased compared to the conventional.

As a result, the height ratio of the gate electrode itself increases and the space between the gate electrodes decreases with high integration, so the aspect ratio of the space between the gate electrodes increases rapidly. The increase in the aspect ratio of the space between the gate electrodes becomes a factor in deteriorating the gap fill property when the interlayer insulating film is deposited after the gate electrode is formed, and voids formed in the interlayer insulating film due to the deterioration of the gap fill property cause a failure in forming subsequent landing plug contacts. There was a problem.

As mentioned above, the process limitation in terms of the interlayer insulating film gapfill margin has emerged as a key issue that can ultimately limit the development of the next generation of highly integrated memory devices. Therefore, there is a need for an alternative solution to effectively solve this problem.

1A to 1G are cross-sectional views (cell regions) showing a DRAM manufacturing process according to the prior art.

In the DRAM manufacturing process according to the related art, first, as shown in FIG. 1A, an isolation region 2 is formed on a silicon substrate 1 to define an active region, and a conventional process is performed to implant wells and channels. After sequentially performing the process, a gate oxide film 3 is grown on the surface of the active region, and a doped polysilicon film 4, a tungsten silicide film 5, and a hard mask nitride film 6 are sequentially deposited on the entire structure. .

Subsequently, as shown in FIG. 1B, a photolithography process and a dry etching process using a gate electrode mask are performed to form a gate electrode pattern, and a conventional gate reoxidation process and LDD ion implantation are performed.

Next, as shown in FIG. 1C, the gate spacer oxide film 7 and the gate spacer nitride film 8 are sequentially deposited along the entire structure surface.

Subsequently, the peripheral circuit region (not shown) is subjected to the peripheral circuit spacer oxide film deposition and the spacer etching process, the peripheral circuit source / drain ion implantation process, and the like to complete the peripheral circuit transistor forming process, as shown in FIG. 1D. As described above, the cell spacer nitride layer 9 is deposited on the entire structure, the interlayer dielectric layer 10 is deposited on the entire structure to form a gap fill, and then the interlayer dielectric layer 10 is planarized through a CMP process, and the hard mask is formed thereon. The nitride film 11 is deposited.

Subsequently, as shown in FIG. 1E, the contact region is opened by performing a photolithography and an etching process using a landing plug contact mask (T-shaped or I-shaped mask) to open the cell spacer nitride film 9, the gate spacer nitride film 8, A cell spacer etching process is performed on the gate spacer oxide layer 7 to form a cell spacer.

Next, as shown in FIG. 1F, a conventional cell source / drain ion implantation is performed, and a polysilicon film 12 for landing plug contact is deposited on the entire structure.

Subsequently, as illustrated in FIG. 1G, planarization is performed through the etch back process and the CMP process until the hard mask nitride film 6 is exposed to remove all films on the gate electrode pattern.

Through the above process, even the landing plug contact is formed, and since the subsequent processes are not considered, the description thereof will be omitted.

Looking at the above-described prior art, it can be seen that the cell spacer stack structure acts as the most direct process variable in terms of the gap fill margin of the interlayer insulating film 10. Therefore, while the width of the cell spacer stack structure is as small as possible in the gap-filled aspect, there is a limit in reducing the width because the width of the spacer has a great effect on the characteristics of the MOS transistor.

On the other hand, improving the hardware capability of the interlayer insulating film gapfill process itself may also be a way to secure a gapfill margin, but it requires a lot of time and effort technically, and will increase the cost of new equipment. .

Therefore, a technical improvement in the manufacturing process that can maximize the process margin at the gap fill capability level of the current interlayer dielectric deposition process while maintaining the thickness of the cell spacer is the most realistic alternative.

The present invention has been proposed to solve the above problems of the prior art, an interlayer insulating film (landing plug contact) deposited after the gate electrode pattern is formed while maintaining the gap fill capability level and the thickness of the cell spacer of the current interlayer insulating film deposition process. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device capable of securing a gap fill margin of an oxide film).

According to an aspect of the present invention for achieving the above technical problem, forming a gate electrode pattern including a gate oxide film, a gate electrode conductive film, a hard mask insulating film on the substrate; Performing LDD ion implantation on the substrate on which the gate electrode pattern is formed; Forming a gate spacer insulating layer along an entire surface of the structure on which the gate electrode pattern is formed; Forming an interlayer insulating film on the entire structure of the gate spacer insulating film; Selectively etching the interlayer dielectric layer of a landing plug contact forming region; Forming a cell spacer insulating film along the entire structure surface of the interlayer insulating film selectively etched; Etching the entire surface of the exposed cell spacer insulating film and the gate spacer insulating film to form a cell spacer; Performing cell source / drain ion implantation on the substrate on which the cell spacer is formed; And forming a landing plug contact embedded in a gap between the gate electrode patterns.                     

According to the present invention, after the step of forming the gate spacer insulating film, forming a peripheral circuit spacer on the sidewall of the gate electrode pattern of the peripheral circuit region, and the source / circuit for the peripheral circuit region where the peripheral circuit spacer is formed. The method further includes performing drain ion implantation.

Preferably, the gate spacer insulating film has an oxide / nitride stack structure.

Further, the cell spacer insulating film is a nitride film, and the peripheral circuit spacer insulating film is an oxide film.

Preferably, the forming of the gate spacer insulating layer may include forming a gate spacer oxide layer having a thickness of about 80 to 120 을 along an entire structure surface on which the gate electrode pattern is formed, and along the entire structure surface on which the gate spacer oxide layer is formed. Forming a gate spacer nitride film having a thickness of 90 to 150 kHz.

The present invention proposes a method of performing the cell spacer insulating film deposition process after the deposition of the interlayer insulating film (landing plug contact oxide film) deposited after the gate electrode pattern formation. In this case, since the landing plug contact oxide film deposition process is performed while the cell spacer insulating film is not deposited, a space corresponding to twice the thickness of the cell spacer insulating film can be secured, and thus a gap fill margin when the landing plug contact oxide film is deposited. Can be secured.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2A to 2G are cross-sectional views (cell areas) illustrating a DRAM manufacturing process according to an embodiment of the present invention.

In the DRAM fabrication process according to the present embodiment, an isolation region 22 is formed on a silicon substrate 21 to define an active region, and a conventional process is performed to sequentially perform well and channel related ion implantation processes. A gate oxide film 23 having a thickness of 30 to 50 GPa is grown on the surface of the active region, and a doped polysilicon film 24 having a thickness of 600 to 1000 GPa is formed on the entire structure, a tungsten silicide film 25 having a thickness of 1000 to 1500 GPa, and 2000 to 2000 A 2500 nm thick hard mask nitride film 26 is deposited one after the other. Next, a photolithography process and a dry etching process using a gate electrode mask are performed to form a gate electrode pattern, and a conventional gate reoxidation process and LDD ion implantation are performed. Subsequently, the gate spacer oxide film 27 and the gate spacer nitride film 28 having a thickness of 90 to 150 s are deposited sequentially along the entire structure surface.

Subsequently, the peripheral circuit region (not shown) is subjected to the peripheral circuit spacer oxide film deposition, the spacer etching process, the peripheral circuit source / drain ion implantation process, and the like to complete the peripheral circuit transistor forming process, as shown in FIG. 2B. As described above, the interlayer insulating layer 30 is deposited on the entire structure to form a gap fill. Then, the interlayer insulating layer 30 is planarized through a CMP process, and the hard mask nitride layer 31 is deposited on the interlayer insulating layer 30.                     

Subsequently, as shown in FIG. 2C, a contact and an etching process using a landing plug contact mask (T-shaped or I-shaped mask) are performed to open the contact region.

Next, as shown in FIG. 2D, a cell spacer nitride film 29 having a thickness of 100 to 200 Å is deposited along the entire structure surface.

Subsequently, as shown in FIG. 2E, the cell spacer nitride film 29, the gate spacer nitride film 28, and the gate spacer oxide film 27 exposed through the entire dry etching are etched to form a cell spacer.

Subsequently, as shown in FIG. 2F, conventional cell source / drain ion implantation is performed, and a polysilicon film 32 for landing plug contact having a thickness of 2000 to 3000 Å is deposited on the entire structure.

Subsequently, as shown in FIG. 2G, planarization is performed until the hard mask nitride layer 26 is exposed through the etch back process and the CMP process to remove all the films on the gate electrode pattern.

Through the above process, even the landing plug contact is formed, and since the subsequent processes are not considered, the description thereof will be omitted.

In the process of the above-described embodiment, since the cell spacer nitride layer 29 is deposited after the landing plug contact is opened, a gap fill margin during deposition of the interlayer dielectric layer 30 can be secured. In addition, the cell spacer nitride layer 29 blocks the bridge of the polysilicon layer 32 for landing plug contact due to voids in the interlayer insulating layer 30 that may exist.                     

On the other hand, since the process of the above-described embodiment changes only the process sequence without adding a new process, effective process margin improvement while eliminating the cost increase due to the introduction of a new interlayer dielectric deposition equipment or the change of device characteristics due to the change of the thickness of the cell spacer There is an advantage to achieve this.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, an example in which a spacer having an oxide / nitride / nitride (ON) structure is applied in a cell region and an oxide / nitride / oxide (ONO) structure spacer is applied in a peripheral circuit region has been described as an example. The present invention is applicable to all semiconductor memory device manufacturing processes that apply a separate cell spacer insulating film regardless of the type of the insulating film forming the spacer and the stacked structure.

In addition, since the stacked structure of the gate electrode pattern applied in the above-described embodiment is not directly related to the technical principle of the present invention, the present invention may be applied to other gate electrode pattern structures.

The present invention as described above can secure a gap fill process margin when the landing plug contact oxide film is deposited while excluding the deterioration of the device characteristics and the cost increase of the device, thereby improving the reliability and yield of the semiconductor memory device.

Claims (6)

Forming a gate electrode pattern including a gate oxide film, a gate electrode conductive film, and a hard mask insulating film on the substrate; Performing LDD ion implantation on the substrate on which the gate electrode pattern is formed; Forming a gate spacer insulating layer along an entire surface of the structure on which the gate electrode pattern is formed; Forming an interlayer insulating film on the entire structure of the gate spacer insulating film; Selectively etching the interlayer dielectric layer of a landing plug contact forming region; Forming a cell spacer insulating film along the entire structure surface of the interlayer insulating film selectively etched; Etching the entire surface of the exposed cell spacer insulating film and the gate spacer insulating film to form a cell spacer; Performing cell source / drain ion implantation on the substrate on which the cell spacer is formed; And Forming a landing plug contact embedded in a gap between the gate electrode patterns Semiconductor memory device manufacturing method comprising a. The method of claim 1, After the step of forming the gate spacer insulating film, Forming a peripheral circuit spacer on sidewalls of the gate electrode pattern in the peripheral circuit region; And performing source / drain ion implantation into the peripheral circuit region where the peripheral circuit spacer is formed. The method of claim 2, And the gate spacer insulating layer has an oxide / nitride layer structure. The method of claim 3, And the cell spacer insulating film is a nitride film. The method of claim 3, And the peripheral circuit spacer insulating film is an oxide film. The method of claim 3, Forming the gate spacer insulating film, Forming a gate spacer oxide film having a thickness of about 80 to about 120 을 along an entire structure surface on which the gate electrode pattern is formed; Forming a gate spacer nitride film having a thickness of 90 to 150 Å along the entire structure surface of the gate spacer oxide film.

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