KR20050121601A - Cmos thin film transitor and method of fabricating thereof - Google Patents
Cmos thin film transitor and method of fabricating thereof Download PDFInfo
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- KR20050121601A KR20050121601A KR1020040046773A KR20040046773A KR20050121601A KR 20050121601 A KR20050121601 A KR 20050121601A KR 1020040046773 A KR1020040046773 A KR 1020040046773A KR 20040046773 A KR20040046773 A KR 20040046773A KR 20050121601 A KR20050121601 A KR 20050121601A
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- 239000010409 thin film Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000012535 impurity Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 61
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 3
- 230000001133 acceleration Effects 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 claims description 3
- 230000008025 crystallization Effects 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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Abstract
CMOS 박막트랜지스터 및 그의 제조 방법을 제공한다. 상기 방법은 절연 기판 상에 비정질 실리콘층을 형성하는 단계, 상기 비정질 실리콘층에 제 1 불순물로 채널 도핑을 실시하는 단계, 상기 채널 도핑된 비정질 실리콘층을 결정화하고 패터닝하여 제 1 및 제 2 반도체층 패턴을 형성하는 단계, 상기 제 1 및 제 2 반도체층 패턴 상에 제 1 포토레지스트를 증착하고 패터닝한 후 상기 제 2 반도체층 패턴 상에 제 2 불순물로 도핑을 실시하여 소오스/드레인 영역을 정의하는 단계 및 상기 제 1 포토레지스트를 제거하고 제 2 포토레지스트를 상기 제 1 및 제 2 반도체층 패턴 상에 증착하고 패터닝한 후 제 1 반도체층 상에 제 3 불순물로 도핑을 실시하여 소오스/드레인 영역을 정의하는 단계를 포함한다. 상기 방법에 의하여 제조되는 CMOS 박막트랜지스터는 액정 표시 소자 또는 유기 전계 발광 소자에 사용된다. 불순물의 도핑시 반도체층 채널부의 포토레지스트 패턴을 하프 톤(half tone) 이나 오픈(open)으로 하여 도핑함으로써 마스크수를 줄이고 또한 공정을 단순화시키는 CMOS 박막트랜지스터의 제조 방법을 제공하는 이점이 있다. Provided are a CMOS thin film transistor and a method of manufacturing the same. The method includes forming an amorphous silicon layer on an insulating substrate, performing channel doping of the amorphous silicon layer with a first impurity, crystallizing and patterning the channel doped amorphous silicon layer to form a first and second semiconductor layer. Forming a pattern, depositing and patterning a first photoresist on the first and second semiconductor layer patterns, and then doping with a second impurity on the second semiconductor layer pattern to define a source / drain region. And removing the first photoresist, depositing and patterning a second photoresist on the first and second semiconductor layer patterns, and then doping with a third impurity on the first semiconductor layer to form a source / drain region. Defining steps. The CMOS thin film transistor manufactured by the above method is used for a liquid crystal display device or an organic electroluminescent device. The doping of the photoresist pattern of the semiconductor layer channel portion in half tone or open at the time of doping of an impurity has an advantage of providing a method of manufacturing a CMOS thin film transistor which reduces the number of masks and simplifies the process.
Description
본 발명은 CMOS 박막트랜지스터 및 그의 제조 방법에 관한 것으로, 보다 상세하게는 마스크 수를 감소시켜 공정을 단순화할 수 있는 채널 도핑이 된 CMOS 박막트랜지스터의 제조 방법 및 상기 방법에 의해 제조되는 CMOS 박막트랜지스터에 관한 것이다. The present invention relates to a CMOS thin film transistor and a method for manufacturing the same, and more particularly, to a method of manufacturing a channel doped CMOS thin film transistor that can simplify the process by reducing the number of masks and a CMOS thin film transistor manufactured by the method It is about.
통상적으로 CMOS 박막트랜지스터를 제작함에 있어서, P형 박막트랜지스터와 N형 박막드랜지스터를 동시에 형성하므로 채널부를 각각 다른 형의 불순물로 도핑하여 CMOS 박막트랜지스터를 제작한다. In general, in manufacturing a CMOS thin film transistor, since a P-type thin film transistor and an N-type thin film transistor are simultaneously formed, a CMOS thin film transistor is manufactured by doping channel portions with impurities of different types.
도 1a 내지 도 1f는 종래의 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들이다. 1A to 1F are process diagrams for describing a method of manufacturing a conventional CMOS thin film transistor.
도 1a를 참조하면, P형 박막트랜지스터가 형성될 영역(10a)과 N형 박막트랜지스터가 형성될 영역(10b)을 구비한 절연 기판(10) 상에 비정질 실리콘층을 형성한 후 결정화하여 폴리실리콘층을 형성한다. 상기 폴리실리콘층을 제 1 마스크(도시하지 않음)를 사용하여 P형 및 N형 박막트랜지스터 영역(10a, 10b)에 제 1 반도체층 패턴(11a) 및 제 2 반도체층 패턴(11b)을 각각 형성한다. Referring to FIG. 1A, an amorphous silicon layer is formed on an insulating substrate 10 having a region 10a where a P-type thin film transistor is to be formed and a region 10b where an N-type thin film transistor is to be formed, and then crystallized to form polysilicon. Form a layer. A first semiconductor layer pattern 11a and a second semiconductor layer pattern 11b are formed in the P-type and N-type thin film transistor regions 10a and 10b using the polysilicon layer using a first mask (not shown), respectively. do.
도 1b를 참조하면, 상기 제 1 반도체층 패턴(11a)이 노출되도록 제 2 마스크(12)를 증착한 다음 N형의 저농도 채널 도핑을 실시한다. Referring to FIG. 1B, a second mask 12 is deposited to expose the first semiconductor layer pattern 11a and then N-type low concentration channel doping is performed.
도 1c를 참조하면, 상기 제 2 마스크(12)를 제거한 후 상기 제 2 반도체층 패턴(11b)이 노출되도록 제 3 마스크(13)를 증착한 다음 P형의 저농도 채널 도핑을 실시한다. Referring to FIG. 1C, after removing the second mask 12, the third mask 13 is deposited to expose the second semiconductor layer pattern 11b, and then P-type low concentration channel doping is performed.
도 1d를 참조하면, 상기 제 3 마스크(13)를 제거한 다음 상기 제 1 및 제 2 반도체층 패턴(11a, 11b) 상에 기판 전면에 걸쳐 게이트 절연막(14)을 형성한다. 이어서, 상기 게이트 절연막(14) 상에 게이트 전극 물질을 형성하고 제 4 마스크(도시하지 않음)를 사용하여 각각의 게이트 전극(15a, 15b)을 형성한다. Referring to FIG. 1D, the gate insulating layer 14 is formed over the entire surface of the first and second semiconductor layer patterns 11a and 11b after removing the third mask 13. Subsequently, a gate electrode material is formed on the gate insulating layer 14, and respective gate electrodes 15a and 15b are formed using a fourth mask (not shown).
도 1e를 참조하면, P형 박막트랜지스터 영역(10a)의 소오스/드레인 영역(17a, 17b)을 형성하기 위하여 게이트 전극(15a) 및 N형 박막트랜지스터 영역(10b)을 제 5 마스크(16)로 증착한 다음 P형의 고농도 불순물을 주입한다. Referring to FIG. 1E, the gate electrode 15a and the N-type thin film transistor region 10b are moved to the fifth mask 16 to form the source / drain regions 17a and 17b of the P-type thin film transistor region 10a. After deposition, a high concentration of impurities of P type is injected.
도 1f를 참조하면, 상기 제 5 마스크(16)를 제거하고 N형 박막트랜지스터 영역(10b)의 소오스/드레인 영역(19a, 19b)을 형성하기 위하여 게이트 전극(15b) 및 P형 박막트랜지스터 영역(10a)을 제 6 마스크(18)로 증착한 다음 N형의 고농도 불순물을 주입한다. 이어서, 제 6 마스크(18)를 제거하고 절연 기판 전면에 걸쳐 소오스/드레인 영역(17a, 17b, 19a, 19b)을 노출시키는 콘택홀에 소오스/드레인 전극을 형성하여 CMOS 박막트랜지스터를 완성한다. Referring to FIG. 1F, the gate electrode 15b and the P-type thin film transistor region (ie, to remove the fifth mask 16 and form source / drain regions 19a and 19b of the N-type thin film transistor region 10b) are described. 10a) is deposited with a sixth mask 18 and then implanted with N-type high concentration impurities. Subsequently, the CMOS thin film transistor is completed by removing the sixth mask 18 and forming a source / drain electrode in a contact hole exposing the source / drain regions 17a, 17b, 19a, and 19b over the entire insulating substrate.
상기한 바와 같이 종래의 CMOS 박막트랜지스터를 제조하는 방법은 P형 및 N형 박막트랜지스터의 채널 부분을 각각 도핑하여야 하므로 마스크가 많이 필요하며 또한 이로 인한 전체적인 공정도 복잡하게 되는 문제점이 있다. As described above, in the conventional method of manufacturing a CMOS thin film transistor, the channel portions of the P-type and N-type thin film transistors must be doped, respectively, so that a lot of masks are required and the overall process is complicated.
본 발명이 이루고자 하는 기술적 과제는 상술한 종래 기술의 문제점을 해결하기 위한 것으로, 불순물의 도핑시 반도체층 채널부의 포토레지스트 패턴을 하프 톤(half tone) 이나 오픈(open)으로 하여 도핑함으로써 마스크수를 줄이고 또한 공정을 단순화시키는데 그 목적이 있다. The technical problem to be solved by the present invention is to solve the above-described problems of the prior art, and when the doping of the impurity doping the photoresist pattern of the semiconductor layer channel portion halftone or open, the number of masks The purpose is to reduce and also simplify the process.
상기 기술적 과제들을 이루기 위하여 본 발명은 CMOS 박막트랜지스터 제조 방법을 제공한다. 상기 방법은 절연 기판 상에 비정질 실리콘층을 형성하는 단계, 상기 비정질 실리콘층에 제 1 불순물로 채널 도핑을 실시하는 단계, 상기 채널 도핑된 비정질 실리콘층을 결정화하고 패터닝하여 제 1 및 제 2 반도체층 패턴을 형성하는 단계, 상기 제 1 및 제 2 반도체층 패턴 상에 제 1 포토레지스트를 증착하고 패터닝한 후 상기 제 2 반도체층 패턴 상에 제 2 불순물로 도핑을 실시하여 소오스/드레인 영역을 정의하는 단계 및 상기 제 1 포토레지스트를 제거하고 제 2 포토레지스트를 상기 제 1 및 제 2 반도체층 패턴 상에 증착하고 패터닝한 후 제 1 반도체층 상에 제 3 불순물로 도핑을 실시하여 소오스/드레인 영역을 정의하는 단계를 포함한다.In order to achieve the above technical problem, the present invention provides a method of manufacturing a CMOS thin film transistor. The method includes forming an amorphous silicon layer on an insulating substrate, performing channel doping of the amorphous silicon layer with a first impurity, crystallizing and patterning the channel doped amorphous silicon layer to form a first and second semiconductor layer. Forming a pattern, depositing and patterning a first photoresist on the first and second semiconductor layer patterns, and then doping with a second impurity on the second semiconductor layer pattern to define a source / drain region. And removing the first photoresist, depositing and patterning a second photoresist on the first and second semiconductor layer patterns, and then doping with a third impurity on the first semiconductor layer to form a source / drain region. Defining steps.
또한, 상기 방법은 절연 기판 상에 비정질 실리콘층을 형성하는 단계, 상기 비정질 실리콘층을 결정화하고 패터닝하여 제 1 및 제 2 반도체층 패턴을 형성하는 단계, 상기 제 1 및 제 2 반도체층 패턴에 제 1 불순물로 채널 도핑을 실시하는 단계, 상기 제 1 및 제 2 반도체층 패턴 상에 제 1 포토레지스트를 증착하고 패터닝한 후 상기 제 2 반도체층 패턴 상에 제 2 불순물로 도핑을 실시하여 소오스/드레인 영역을 정의하는 단계 및 상기 제 1 포토레지스트를 제거하고 제 2 포토레지스트를 상기 제 1 및 제 2 반도체층 패턴 상에 증착하고 패터닝한 후 제 1 반도체층 상에 제 3 불순물로 도핑을 실시하여 소오스/드레인 영역을 정의하는 단계를 포함한다.In addition, the method includes forming an amorphous silicon layer on an insulating substrate, crystallizing and patterning the amorphous silicon layer to form first and second semiconductor layer patterns, and forming a first and second semiconductor layer patterns on the first and second semiconductor layer patterns. Performing channel doping with one impurity, depositing and patterning a first photoresist on the first and second semiconductor layer patterns, and then doping with a second impurity on the second semiconductor layer pattern to perform source / drain Defining a region, removing the first photoresist, depositing and patterning a second photoresist on the first and second semiconductor layer patterns, and then doping with a third impurity on the first semiconductor layer. / Defining the drain area.
상기 제 1 포토레지스트의 패터닝은 제 1 반도체층 패턴은 채널부를 하프 톤(half tone) 마스크 또는 오픈(open) 마스크를 사용하고, 제 2 반도체층 패턴은 채널부를 제외한 부분을 오픈 마스크를 사용하여 수행할 수 있다.The patterning of the first photoresist is performed by using a half tone mask or an open mask on the channel portion of the first semiconductor layer pattern, and using an open mask on the portion except the channel portion of the second semiconductor layer pattern. can do.
상기 제 1 및 제 3 불순물은 P형 불순물이고, 제 2 불순물은 N형 불순물일 수 있다. The first and third impurities may be P-type impurities, and the second impurities may be N-type impurities.
또한, 상기 제 1 및 제 3 불순물은 N형 불순물이고, 제 2 불순물은 P형 불순물일 수 있다. In addition, the first and third impurities may be N-type impurities, and the second impurities may be P-type impurities.
상기 P형의 불순물은 B, Al, Ga 및 In으로 이루어진 군에서 선택될 수 있고, 상기 N형의 불순물은 P, As, Sb 및 Bi로 이루어진 군에서 선택될 수 있다.The P-type impurities may be selected from the group consisting of B, Al, Ga, and In, and the N-type impurities may be selected from the group consisting of P, As, Sb, and Bi.
상기 채널 도핑의 도즈는 1×1011 내지 6×1011ions/㎠인 것이 바람직하다.The dose of the channel doping is preferably 1 × 10 11 to 6 × 10 11 ions / cm 2.
상기 채널 도핑의 가속 전압은 10 내지 50keV인 것이 바람직하다. The acceleration voltage of the channel doping is preferably 10 to 50 keV.
상기 결정화는 SPC법, MIC법, MILC법, ELA법 및 SLS법으로 이루어진 군에서 선택하여 사용할 수 있다. The crystallization can be selected from the group consisting of SPC method, MIC method, MILC method, ELA method and SLS method.
상기 방법에 의하여 제조되는 CMOS 박막트랜지스터는 액정 표시 소자 또는 유기 전계 발광 소자에 사용될 수 있다.The CMOS thin film transistor manufactured by the above method may be used in a liquid crystal display device or an organic electroluminescent device.
이하, 본 발명을 보다 구체적으로 설명하기 위하여 본 발명에 따른 바람직한 실시예를 첨부한 도면을 참조하여 보다 상세하게 설명한다. 명세서 전체에 걸쳐 동일한 참조 번호는 동일한 구성 요소를 나타낸다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention in order to explain the present invention in more detail. Like numbers refer to like elements throughout the specification.
도 2a 내지 도 2e는 본 발명의 제 1 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들이다.2A through 2E are process diagrams for describing a method of manufacturing a CMOS thin film transistor according to a first embodiment of the present invention.
도 2a를 참조하면, P형 박막트랜지스터가 형성될 영역(20a)과 N형 박막트랜지스터가 형성될 영역(20b)을 구비한 절연 기판(20) 상에 비정질 실리콘층(21)을 형성한다. 상기 비정질 실리콘층(21)을 P형 저농도 불순물로 채널 도핑한다. 상기 채널 도핑의 도즈는 1×1011 내지 6×1011ions/㎠, 상기 채널 도핑의 가속 전압은 10 내지 50keV인 것이 바람직하다. 상기한 도핑의 도즈로 채널 도핑이 되었을때 이동도가 향상되며, 상기한 도핑의 가속 전압에서 채널 도핑이 되었을때 문턱 전압 등과 같은 소자 특성이 향상된다.Referring to FIG. 2A, an amorphous silicon layer 21 is formed on an insulating substrate 20 having a region 20a in which a P-type thin film transistor is to be formed and a region 20b in which an N-type thin film transistor is to be formed. The amorphous silicon layer 21 is channel-doped with a P-type low concentration impurity. The dose of the channel doping is 1 × 10 11 to 6 × 10 11 ions / cm 2, and the acceleration voltage of the channel doping is 10 to 50 keV. The mobility is improved when the channel is doped with the doping of the doping, and the device characteristics such as the threshold voltage are improved when the channel is doped at the acceleration voltage of the doping.
도 2b를 참조하면, 상기 채널 도핑된 비정질 실리콘층(21)을 결정화하고 제 1 마스크(도면에 미기재)를 사용하여 패터닝함으로써 각각 제 1 반도체층 패턴(21a) 및 제 2 반도체층 패턴(21b)을 형성한다. 2B, the first semiconductor layer pattern 21a and the second semiconductor layer pattern 21b are respectively crystallized by patterning the channel doped amorphous silicon layer 21 and patterned using a first mask (not shown). To form.
도 2c를 참조하면, 상기 제 1 및 제 2 반도체층 패턴(21a, 21b) 상에 포토레지스트 패턴(22)를 증착한다. 이때, 포토레지스트를 패터닝함에 있어서, 제 1 반도체층 패턴(21a)의 채널부(23a)에는 하프 톤 마스크로하거나 오픈 마스크를 사용하여 상기 포토레지스트를 패터닝한다. 또한, 제 2 반도체층 패턴(21b)에는 채널부(23b)를 제외한 소오스/드레인 영역(25a, 25b)을 오픈 마스크를 사용하여 패터닝한다. Referring to FIG. 2C, photoresist patterns 22 are deposited on the first and second semiconductor layer patterns 21a and 21b. At this time, in patterning the photoresist, the photoresist is patterned in the channel portion 23a of the first semiconductor layer pattern 21a using a halftone mask or an open mask. In addition, the source / drain regions 25a and 25b except for the channel portion 23b are patterned in the second semiconductor layer pattern 21b using an open mask.
이어서, P형 및 N형 박막트랜지스터 영역 전면에 걸쳐서 N형 고농도 불순물로 도핑한다. 이때, 제 1 반도체층 패턴(21a)의 채널부(23a)를 오픈 마스크를 사용 한 경우에는 N형의 농도가 저농도로 되고, 하프 톤 마스크를 사용한 경우에는 오픈마스크를 사용하여 도핑한 경우보다는 농도가 높게 된다. 이와 동시에, 제 2 반도체층 패턴(21b)의 소오스/드레인 영역(25a, 25b)은 N형의 고농도 불순물이 형성되고 채널부(23b)에는 P형의 저농도 불순물이 형성된다. Then, the dopant is doped with an N-type high concentration impurity over the entire P-type and N-type thin film transistor regions. In this case, when the channel portion 23a of the first semiconductor layer pattern 21a uses the open mask, the N-type concentration becomes low, and when the halftone mask is used, the density is lower than that of the doping using the open mask. Becomes high. At the same time, N-type high concentration impurities are formed in the source / drain regions 25a and 25b of the second semiconductor layer pattern 21b, and P-type low concentration impurities are formed in the channel portion 23b.
도 2d를 참조하면, 상기 포토레지스트 패턴(22)을 제거하고 제 1 반도체층 패턴(21a)의 소오스/드레인 영역(24a, 24b)을 고농도 불순물로 도핑하기위하여 제 1 반도체층 패턴의 채널부(23b) 및 N형 박막트랜지스터 영역(20b)을 제 2 마스크(26)로 증착한다. 이어서, P형 고농도 불순물로 도핑을 실시한다. 그 결과, 제 1 반도체층 패턴의 소오스/드레인 영역(24a, 24b)은 P형의 고농도 불순물이 형성되고, 채널부(23a)는 N형 저농도 불순물이 형성된다. Referring to FIG. 2D, the channel portion of the first semiconductor layer pattern may be removed to remove the photoresist pattern 22 and to dope the source / drain regions 24a and 24b of the first semiconductor layer pattern 21a with high concentration impurities. 23b) and the N-type thin film transistor region 20b are deposited with the second mask 26. Next, doping is performed with a P-type high concentration impurity. As a result, P-type high concentration impurities are formed in the source / drain regions 24a and 24b of the first semiconductor layer pattern, and N-type low concentration impurities are formed in the channel portion 23a.
도 2e를 참조하면, 상기 포토레지스트(26)를 제거하고 제 1 반도체층 패턴(21a) 및 제 2 반도체층 패턴(21b) 상에 절연 기판 전면에 걸쳐 게이트 절연막(27)을 형성한다. 이어서, 게이트 전극 물질을 형성하고 제 3 마스크(도시하지 않음)를 사용하여 게이트 전극(28a, 28b)을 형성한다. 이후, 소오스/드레인 전극을 형성함으로써 CMOS 박막트랜지스터를 완성한다. Referring to FIG. 2E, the photoresist 26 is removed and a gate insulating layer 27 is formed over the entire surface of the insulating substrate on the first semiconductor layer pattern 21a and the second semiconductor layer pattern 21b. Subsequently, a gate electrode material is formed and gate electrodes 28a and 28b are formed using a third mask (not shown). Thereafter, the CMOS thin film transistor is completed by forming source / drain electrodes.
상기한 바와 같이, 비정질 실리콘층에 채널 도핑을 수행한 후, 포토레지스트 패턴을 하프 톤 마스크 또는 오픈 마스크를 사용하여 패터닝함으로써 종래보다 마스크수가 줄어들고 공정이 단순화되었다. 종래에는 6개의 마스크가 필요한 반면에, 본 발명에서는 PR을 포함하여 4개의 마스크가 필요하여 2개의 마스크가 줄어들었으며 공정 또한 단순화되었음을 알수 있다. As described above, after channel doping the amorphous silicon layer, the photoresist pattern is patterned using a halftone mask or an open mask, thereby reducing the number of masks and simplifying the process. Conventionally, six masks are required, whereas in the present invention, four masks are required including the PR, so that two masks are reduced and the process is simplified.
도 3a 내지 도 3e는 본 발명의 제 2 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들이다. 3A to 3E are flowcharts illustrating a method of manufacturing a CMOS thin film transistor according to a second exemplary embodiment of the present invention.
도 3a를 참조하면, N형 박막트랜지스터가 형성될 영역(30a)과 P형 박막트랜지스터가 형성될 영역(30b)을 구비한 절연 기판(30) 상에 비정질 실리콘층(31)을 형성한다. 상기 비정질 실리콘층(31)을 N형의 저농도 불순물로 채널 도핑한다. Referring to FIG. 3A, an amorphous silicon layer 31 is formed on an insulating substrate 30 having a region 30a in which an N-type thin film transistor is to be formed and a region 30b in which a P-type thin film transistor is to be formed. The amorphous silicon layer 31 is channel-doped with an N-type low concentration impurity.
도 3b를 참조하면, 상기 비정질 실리콘층(31)을 결정화하고 패터닝하여 제 1 및 제 2 반도체층 패턴(31a, 31b)을 형성한다. Referring to FIG. 3B, the amorphous silicon layer 31 is crystallized and patterned to form first and second semiconductor layer patterns 31a and 31b.
도 3c를 참조하면, 상기 제 1 및 제 2 반도체층 패턴(31a, 31b) 상에 포토레지스트 패턴(32)을 형성하여 N형 및 P형 박막트랜지스터 영역 전면에 걸쳐서 P형 고농도 불순물로 도핑한다.Referring to FIG. 3C, photoresist patterns 32 are formed on the first and second semiconductor layer patterns 31a and 31b to be doped with P-type high concentration impurities over the entire N-type and P-type thin film transistor regions.
도 3d를 참조하면, 상기 포토레지스트 패턴(32)을 제거하고 제 1 반도체층 패턴(31a)의 소오스/드레인 영역(34a, 34b)을 고농도 불순물로 도핑하기위하여 제 1 반도체층 패턴의 채널부(33b) 및 N형 박막트랜지스터 영역(30b)을 포토레지스트 마스크(36)로 증착한다. 이어서, N형 고농도 불순물로 도핑을 실시한다. 그 결과, 제 1 반도체층 패턴의 소오스/드레인 영역(34a, 34b)은 N형의 고농도 불순물이 형성되고, 채널부(33a)는 N형 저농도 불순물이 형성된다. Referring to FIG. 3D, the channel portion of the first semiconductor layer pattern may be removed to remove the photoresist pattern 32 and to dope the source / drain regions 34a and 34b of the first semiconductor layer pattern 31a with high concentration impurities. 33b) and the N-type thin film transistor region 30b are deposited by the photoresist mask 36. Next, doping is performed with an N-type high concentration impurity. As a result, N-type high concentration impurities are formed in the source / drain regions 34a and 34b of the first semiconductor layer pattern, and N-type low concentration impurities are formed in the channel portion 33a.
도 3e를 참조하면, 상기 포토레지스트 마스크(36)을 제거하고 제 1 반도체층 패턴(31a) 및 제 2 반도체층 패턴(31b) 상에 절연 기판 전면에 걸쳐 게이트 절연막(37)을 형성한다. 이어서, 게이트 전극 물질을 형성하고 마스크(도면에 미기재)를 사용하여 게이트 전극(38a, 38b)을 형성한다. 이후, 소오스/드레인 전극을 형성함으로써 CMOS 박막트랜지스터를 완성한다. Referring to FIG. 3E, the photoresist mask 36 is removed to form a gate insulating layer 37 over the entire surface of the insulating substrate on the first semiconductor layer pattern 31a and the second semiconductor layer pattern 31b. Subsequently, a gate electrode material is formed and gate electrodes 38a and 38b are formed using a mask (not shown in the figure). Thereafter, the CMOS thin film transistor is completed by forming source / drain electrodes.
상기한 것을 제외하고는 본 발명의 제 1 실시예에 따른 CMOS 박막트랜지스터의 제조 방법과 동일하다. Except for the above, it is the same as the manufacturing method of the CMOS thin film transistor according to the first embodiment of the present invention.
도 4a 및 도 4b는 본 발명의 제 3 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들이다. 4A and 4B are flowcharts illustrating a method of manufacturing a CMOS thin film transistor according to a third exemplary embodiment of the present invention.
도 4a를 참조하면, P형 박막트랜지스터가 형성될 영역(40a)과 N형 박막트랜지스터가 형성될 영역(40b)을 구비한 절연 기판(40) 상에 비정질 실리콘층을 형성한다. 상기 비정질 실리콘층을 결정화하고 패터닝하여 제 1 및 제 2 반도체층 패턴(41a, 41b)을 형성한다. Referring to FIG. 4A, an amorphous silicon layer is formed on an insulating substrate 40 having a region 40a in which a P-type thin film transistor is to be formed and a region 40b in which an N-type thin film transistor is to be formed. The amorphous silicon layer is crystallized and patterned to form first and second semiconductor layer patterns 41a and 41b.
도 4b를 참조하면, 상기 제 1 및 제 2 반도체층 패턴(41a, 41b)에 P형 저농도 불순물로 채널 도핑을 실시한다. 본 발명의 제 1 실시예에서는 비정질 실리콘층에 채널 도핑을 하였으나, 제 3 실시예에서는 반도체층 패턴을 형성한 후에 채널 도핑을 실시한다. Referring to FIG. 4B, channel doping of the first and second semiconductor layer patterns 41a and 41b is performed using P-type low concentration impurities. In the first embodiment of the present invention, channel doping is performed on the amorphous silicon layer. In the third embodiment, channel doping is performed after the semiconductor layer pattern is formed.
상기한 것을 제외하고는 본 발명의 제 1 실시예에 따른 CMOS 박막트랜지스터의 제조 방법과 동일하다. Except for the above, it is the same as the manufacturing method of the CMOS thin film transistor according to the first embodiment of the present invention.
도 5a 및 도 5b는 본 발명의 제 4 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들이다. 5A and 5B are process diagrams for describing a method of manufacturing a CMOS thin film transistor according to a fourth exemplary embodiment of the present invention.
도 5a를 참조하면, N형 박막트랜지스터가 형성될 영역(50a)과 P형 박막트랜지스터가 형성될 영역(50b)을 구비한 절연 기판(50) 상에 비정질 실리콘층을 형성한다. 상기 비정질 실리콘층을 결정화하고 패터닝하여 제 1 및 제 2 반도체층 패턴(51a, 51b)을 형성한다. Referring to FIG. 5A, an amorphous silicon layer is formed on an insulating substrate 50 having a region 50a in which an N-type thin film transistor is to be formed and a region 50b in which a P-type thin film transistor is to be formed. The amorphous silicon layer is crystallized and patterned to form first and second semiconductor layer patterns 51a and 51b.
도 5b를 참조하면, 상기 제 1 및 제 2 반도체층 패턴(51a, 51b)에 N형 저농도 불순물로 채널 도핑을 실시한다. 본 발명의 제 2 실시예에서는 비정질 실리콘층에 채널 도핑을 하였으나, 제 4 실시예에서는 반도체층 패턴을 형성한 후에 채널 도핑을 실시한다. Referring to FIG. 5B, channel doping of the first and second semiconductor layer patterns 51a and 51b with N-type low concentration impurities is performed. In the second embodiment of the present invention, channel doping is performed on the amorphous silicon layer. In the fourth embodiment, channel doping is performed after the semiconductor layer pattern is formed.
상기한 것을 제외하고는 본 발명의 제 2 실시예에 따른 CMOS 박막트랜지스터의 제조 방법과 동일하다. Except for the above, it is the same as the manufacturing method of the CMOS thin film transistor according to the second embodiment of the present invention.
상술한 바와 같이 본 발명에 따르면, 불순물의 도핑시 반도체층 채널부의 포토레지스트 패턴을 하프 톤(half tone) 이나 오픈(open)을 사용하여 패턴한 후 도핑함으로써 마스크수를 줄이고 또한 공정을 단순화시키는 CMOS 박막트랜지스터의 제조 방법을 제공하는 이점이 있다. As described above, according to the present invention, a CMOS that reduces the number of masks and simplifies the process by doping after patterning the photoresist pattern of the semiconductor layer channel portion using half tone or open during doping of impurities. There is an advantage to provide a method of manufacturing a thin film transistor.
상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있을 것이다.While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. Could be.
도 1a 내지 도 1f는 종래의 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들,1A to 1F are process diagrams for explaining a method of manufacturing a conventional CMOS thin film transistor,
도 2a 내지 도 2e는 본 발명의 제 1 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들,2A through 2E are process diagrams for describing a method of manufacturing a CMOS thin film transistor according to a first embodiment of the present invention;
도 3a 내지 도 3e는 본 발명의 제 2 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들,3A to 3E are flowcharts illustrating a method of manufacturing a CMOS thin film transistor according to a second embodiment of the present invention;
도 4a 및 도 4b는 본 발명의 제 3 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들, 4A and 4B are flowcharts illustrating a method of manufacturing a CMOS thin film transistor according to a third embodiment of the present invention;
도 5a 및 도 5b는 본 발명의 제 4 실시예에 따른 CMOS 박막트랜지스터의 제조 방법을 설명하기 위한 공정도들이다. 5A and 5B are process diagrams for describing a method of manufacturing a CMOS thin film transistor according to a fourth exemplary embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 20, 30, 40 : 절연 기판 10, 20, 30, 40: insulated substrate
10a, 20a, 30b, 40a, 50b : P형 박막트랜지스터가 형성될 영역10a, 20a, 30b, 40a, 50b: area where P-type thin film transistor is to be formed
10b, 20b, 30a, 40b, 50a : N형 박막트랜지스터가 형성될 영역10b, 20b, 30a, 40b, 50a: region where the N-type thin film transistor is to be formed
21, 31 : 비정질 실리콘층21, 31: amorphous silicon layer
11a, 21a, 31a, 41a, 51a : 제 1 반도체층 패턴11a, 21a, 31a, 41a, 51a: first semiconductor layer pattern
11b, 21b, 31b, 41b, 51b : 제 2 반도체층 패턴11b, 21b, 31b, 41b, 51b: second semiconductor layer pattern
22, 32 : 포토레지스트 패턴22, 32: photoresist pattern
14, 27, 37 : 게이트 절연막14, 27, 37: gate insulating film
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| KR100795803B1 (en) * | 2006-08-10 | 2008-01-21 | 삼성에스디아이 주식회사 | Cmos thin film transistor and method for fabricating the same |
| KR100796609B1 (en) * | 2006-08-17 | 2008-01-22 | 삼성에스디아이 주식회사 | Fabricating method for cmos thin film transistor and cmos thin film transistor using the same |
| KR100796606B1 (en) * | 2006-08-08 | 2008-01-22 | 삼성에스디아이 주식회사 | Method for fabricating of thin film transistor |
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| KR20190111723A (en) * | 2018-03-23 | 2019-10-02 | 잉 홍 | Low temperature poly-Si Semiconductor Device and method thereof |
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