KR20050121441A - Solid state image sensing device having source follower jfet of vertical channel configuration and driving method thereof - Google Patents

Abstract

Disclosed are a solid-state imaging device having a source follower JFET having a vertical channel structure, and a driving method thereof. In the solid-state imaging device, a JFET that forms a vertical channel is used as the source follower transistor. The JFET is subjected to voltage control of the FD node with only one gate electrode, and a depletion layer is formed toward the STI by such a gate electrode, so that a substantial channel is formed vertically between the edge of the depletion layer and the STI.

Description

Solid state image sensing device having source follower JFET of vertical channel configuration and driving method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state image sensing device, and more particularly, to a pixel circuit of a CMOS image sensor (CIS) type solid state imaging device and a driving method of the solid state imaging device.

The CIS-type solid-state imaging device is mounted on a mobile phone camera, a digital still camera, or the like, and captures an image developed in a field of view, converts the image into an electrical signal, and transmits it to a digital signal processor. The digital signal processing unit processes color image data R, G, and B output from the solid state image pickup device to drive a display device such as a liquid crystal display (LCD).

1 is a block diagram showing a general CIS type solid-state imaging device 100. Referring to FIG. 1, a general CIS type solid-state imaging device 100 includes an active pixel sensor (APS) array 110, a row driver 120, and an analog-digital converter (ADC). 130 is provided. The row driver 120 receives a control signal from a row decoder (not shown), and the analog-to-digital converter 130 receives a control signal from a column decoder (not shown). In addition, the solid-state imaging device 100 includes a control unit (not shown) for generating general timing control signals and addressing signals for selecting each pixel and outputting a sensed image signal. In general, in the case of the color solid-state imaging device 100, as shown in FIG. 2, a color filter is installed to receive only light of a specific color on each pixel forming the APS array 110. In order to arrange at least three kinds of color filters. The most common color filter array is Bayer, where the patterns of two colors R (red) and G (green) are arranged in one row, and the patterns of two colors G (green) and B (blue) are arranged in another row. ) Has a pattern. At this time, G (green), which is closely related to the luminance signal, is disposed in every row, and R (red) color and B (blue) color are alternately arranged in each row to increase the luminance resolution. Digital still cameras, etc. are applied to a CIS array of many million pixels or more in order to increase the resolution.

In the CIS type solid-state imaging device 100 having such a pixel structure, the APS array 110 detects light using a photodiode and converts the light into an electrical signal to generate an image signal. The video signal output from the APS array 110 is an analog signal of three colors of red (R), green (G), and blue (B). The analog-digital converter 130 receives an analog image signal output from the pixel array 110 and converts the analog image signal into a digital signal.

In the general CIS type solid-state imaging device 100 as shown in FIG. 1, when converting an image signal detected by an optical device into a digital signal by the analog-digital converter 130, a correlated double sampling (CDS) method is used. Such a driving method is well described in the US patent, "USP5,982,318", or "USP6,067,113". 3 is a circuit diagram of a unit pixel of an APS array in a CDS scheme. Referring to FIG. 1, one pixel is a current source CS1 which is modeled by four metal-oxide-semiconductor field effect transistors (M1 to M4), one optical device PD, and a bias circuit. It is composed. In the analog-to-digital conversion of the CDS method, after receiving the reset signal VRES from the pixel, the video signal VSIG received from the optical device PD is converted into a digital signal. In FIG. 3, in the state in which the row select signal SEL is activated in a logic high state, in response to the reset control signal RX, the voltage of the FD node transferred from the power supply VDD is the source follower M3. It is output through the source terminal of. The voltage of the FD node output to the source terminal of M3 is output to the analog-to-digital converter 130 as a reset signal VRES through the source terminal of M1. On the other hand, in a state in which the row select signal SEL is activated in a logic high state, in response to the transfer control signal TX, the image signal VSIG photoelectrically converted from the optical device PD is analogized through the source terminal of M1. It is output to the digital converter 230. Such an operation is performed on the pixels of each row whenever the row select signals SEL1, SEL2, SEL3, ... are sequentially activated. The digital signal converted as described above is output to the digital signal processor and subjected to a predetermined interpolation process. In addition, the subsequent digital signal processor generates drive signals suitable for the corresponding resolution of the display device such as an LCD, and drives the display device.

In a CIS type solid-state imaging device, a MOSFET is usually used as a source follower transistor (M3 in FIG. 3) as described above. Since the MOSFET is a surface channel element, it can generate a large noise. The smaller the pixel size, the smaller the size of the source follower transistor, and therefore, the noise in particular in the source follower transistor becomes a greater problem. In order to reduce noise in the source follower transistor, NIKON has proposed a method called Lateral buried channel accumulator and sensing array (LBCAST). Such a structure using a LBCAST type junction field effect transistor (JFET) as a source follower transistor is well shown in Japanese Laid Open Patent Application, "JP1996-293591". 4 is a cross-sectional view illustrating a conventional JFET structure of the source follower transistor of FIG. 3. Since the source follower JFET shown in FIG. 4 operates by the bulk current of the lateral channel, it may not generate a large noise. However, in the source follower JFET having such a conventional structure, it is necessary to arrange the gate diffusion layer N + S / D in the entire direction around the source diffusion layer P + S / D, and the source diffusion layer P + S. / D) Space with other electrodes is needed from side to side. Thus, the JFET of this lateral channel structure occupies more than twice the area of the MOSFET in the same processing technology. Even if a normal vertical panel JFET is used instead of the horizontal channel JFET, it also occupies a larger footprint than the MOSFET. Therefore, the conventional JFET structure may be applicable when the pixel size is large, but when the pixel size is small, there is a problem that it is not applicable because the "fill factor" is small.

Accordingly, a technical object of the present invention is to provide a solid-state imaging device using a source follower JFET applicable to a small pixel, and a method of driving the solid-state imaging device.

A solid-state imaging device according to the present invention for achieving the above technical problem is characterized by comprising an APS array, a row driver, a column driving circuit, and an analog-to-digital converter. In the APS array, pixels are arranged in a two-dimensional matrix, and in each pixel of the selected row, an output reset signal is generated and transmitted in response to a pixel reset signal, and a photoelectrically converted image signal is transmitted in response to a transfer control signal. do. The row driver generates row selection signals that are sequentially activated to select each row of the APS array, and generates the transfer control signal. The column driving circuit generates the pixel reset signal in response to a first reset control signal, receives the output reset signal and the image signal transmitted from the APS array in response to a read signal, and outputs constant voltages corresponding thereto. . The analog-digital converter converts an analog signal corresponding to the difference of the video signal with respect to the output reset signal into a digital signal and outputs the digital signal. The column driving circuit generates an optical device reset signal in response to a second reset control signal, and the optical device included in the selected pixel of each column is reset in response to the optical device reset signal.

Each of the pixels included in the APS array includes an optical device, a first MOSFET, a second MOSFET, and a JFET. The optical device receives external light to generate the photoelectrically converted image signal. In the first MOSFET, a gate electrode receives the transfer control signal, one side of the source / drain electrodes is connected to the optical device output side, and the other side is connected to the FD node. In the second MOSFET, a gate electrode receives the row select signal, one of the source / drain electrodes is connected to the FD node, and the other is connected to the output node. In the JFET, a gate electrode is connected to the FD node, one side of the source / drain electrodes is connected to the output node, and the other side is grounded. The output reset signal and the video signal are transmitted through the output node. The first MOSFET and the second MOSFET are characterized in that the N-channel type. The JFET is characterized in that the P channel type. The JFET is characterized in that it operates by the bulk current in the vertically formed channel. The JFET is characterized in that the drain electrode is a P-WELL formed between the substrate and the P-EPI layer.

According to another aspect of the present invention, there is provided a method of driving a solid-state imaging device, the method comprising: generating a row selection signal that is sequentially activated to select each row of the APS array; Generating a pixel reset signal in response to the first reset control signal; Generating and delivering an output reset signal in response to said pixel reset signal at each pixel of a selected row of an APS array; Generating a transfer control signal; Delivering, at each pixel of a selected row of an APS array, a photoelectrically converted image signal in response to the transfer control signal; Receiving the output reset signal and the image signal transmitted from the APS array in response to a read signal and outputting predetermined voltages corresponding thereto; And converting an analog signal corresponding to the difference of the video signal with respect to the output reset signal into a digital signal and outputting the digital signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

In the CIS-type solid-state imaging device according to an embodiment of the present invention, as shown in FIG. 2, each column of the APS array 110 in which pixels are arranged in a two-dimensional matrix form is configured with the column circuit 500 of FIG. 5. . Referring to FIG. 5, the column circuit 500 includes pixel circuits 510, 520,... For each pixel. In addition, the column circuit 500 drives and controls the pixel circuits 510, 520,... Around the top or bottom of the pixel circuits 510, 520,... A column driving circuit 530 for outputting predetermined voltages corresponding to the output reset signal VRES and the image signal VSIG transmitted from 510, 520, ... to the analog-digital converter (130 of FIG. 1). Equipped. In the CIS type solid-state image pickup device according to an embodiment of the present invention, when the image signal sensed by the pixel photodiode is converted into a digital signal by the analog-digital converter (130 of FIG. 1), it is described in FIG. A correlated double sampling (CDS) scheme is used. In particular, the present invention proposes a source follower JFET that can be applied to a small pixel in order to reduce noise in the source follower transistor (M3 in FIG. 3), and to drive the changed pixel circuit 510 and the pixel circuit at this time. A column drive circuit 530 is proposed. The timing diagram of FIG. 6 is referred to for describing the circuit operation of FIG. 5.

In FIG. 5, the first pixel circuit 510 includes an optical device PD1, a first MOSFET M11 as a transfer gate, a second MOSFET M12 as a reset and row select gate, and a JFET J1. The second pixel circuit 520 has the same configuration as the first pixel circuit 510, and other pixel circuits not shown in the drawing have the same configuration as the first pixel circuit 510, and all of them have similar operations. Do it. In the same row of pixels, the same transfer control signals TG1, TG2, ..., and row selection signals RESEL1, RESEL2, ... are controlled. The optical device PD1 receives an external light to generate a photoelectrically converted image signal. In the first MOSFET M11, a gate electrode receives a transfer control signal TG1, one side of the source / drain electrodes is connected to the optical device PD1 output side, and the other side is connected to the FD node FD1. do. In the second MOSFET M12, a gate electrode receives a corresponding row select signal RESEL1, one side of the source / drain electrodes is connected to the FD node FD1, and the other side is connected to the output node Vout. do. The first MOSFET M11 and the second MOSFET M12 are of N channel type. In the JFET J1, a gate electrode is connected to the FD node FD1, one side of the source / drain electrodes is connected to the output node Vout, and the other side is grounded. The output reset signal VRES and the image signal VSIG generated at each pixel are transmitted to the column driving circuit 530 through the output node Vout. The JFET is a P channel.

In order to drive the column circuit 500 as shown in FIG. 5, the row driver (see FIG. 1) generates row select signals RESEL1, RESEL2,..., To sequentially select and transfer each row of the APS array. Generate control signals TG1, TG2, ... The selection signals RESEL1, RESEL2, ... of each row are activated once per frame. As each row of the APS array is selected as described above, at each pixel of the selected row, in response to the pixel reset signal generated by the column driving circuit 530, an output reset signal VRES is generated to generate an output node Vout. And the photoelectrically converted image signal VSIG to the output node Vout in response to the transfer control signals TG1, TG2,... For example, in FIG. 6, C1 is a point in time when the output reset signal VRES is generated in the first pixel circuit 510, and C2 is generated in the second pixel circuit 520, which is the next row, and generates an output reset signal VRES. It is time to. In addition, in FIG. 6, each of E1 and E2 is a time point at which each of the first pixel circuit 510 and the second pixel circuit 520 transfers the image signal VSIG to the output node Vout.

In FIG. 5, the column driving circuit 530 generates the pixel reset signal in response to the first reset control signals RST1 and RST1B and outputs the pixel reset signal to the output node Vout. The RST1B signal is an inverted signal of the RST1 signal. The first switch PG1 including a PMOSFET and an NMOSFET may output a VRST voltage to the output node Vout as the pixel reset signal when the first reset control signals RST1 and RST1B are activated. The VRST voltage has a voltage level small enough to turn on the P-channel type JFETs J1, J2, ....

At this time, the VRST voltage is not transmitted to the FD nodes FD1, FD2, ... of all pixels in each column, but only in the pixels of the row selected by the row selection signals RESEL1, RESEL2, .... VRST voltage can be delivered. That is, at the time B1 of FIG. 6, the row selection signals RESEL2,... Except for the first row selection signal RESEL1 transition to a logic low state, and at the time C1, the first row selection signal ( RESEL1) transitions to a logic low state. Accordingly, the MOSFET M12 turned on at the time C1 by the first row select signal RESEL1 transfers the VRST voltage to the FD1 node, and at this time, the corresponding JFET J1 is turned on. Accordingly, the first pixel circuit 510 may generate the output reset signal VRES in response to the VRST voltage transmitted to the FD1 node. Similarly, at time point B2 of FIG. 6, the row selection signals except for the second row selection signal RESEL2 transition to a logic low state, and at time C2, the second row selection signal RESEL2 transitions to a logic low state. Accordingly, the MOSFET M22 turned on at the time C2 by the second row select signal RESEL2 transfers the VRST voltage to the FD2 node, and at this time, the corresponding JFET J2 is turned on. Accordingly, the second pixel circuit 520 may generate the output reset signal VRES in response to the VRST voltage transmitted to the FD2 node.

In addition, the column driving circuit 530 generates an optical device reset signal in response to the second reset control signals RST2 and RST2B and outputs it to the output node Vout. The RST2B signal is an inverted signal of the RST2 signal. The second switch PG2 including the PMOSFET and the NMOSFET may output a VH voltage to the output node Vout as the optical device reset signal when the second reset control signals RST2 and RST2B are activated. In the pixel selected by the row select signal, the optical device is reset in response to the optical device reset signal. The VH voltage has a voltage level large enough to turn off the P-channel type JFETs J1, J2, .... The VH voltage is greater than the VRST voltage level. For example, in A1 and A2 of FIG. 6, the transfer control signals TG1, TG2,... Are activated while the optical device reset signals are transmitted to the FD nodes FD1, FD2,. At this time, the pixel circuits 510 and 520 are reset.

As shown in FIG. 6, it can be seen that the output reset signal VRES is generated at C1 or C2 after the optical devices PD1, PD2,... Are reset at A1 or A2. That is, after the optical devices PD1, PD2, ... are reset, the second reset control signals RST2 and RST2B are deactivated at the time B1 or B2, so that the second switch PG2 is turned off. Then, it can be seen that the output reset signal VRES is generated only in the corresponding pixel of the row selected in each column by the first reset control signals RST1 and RST1B that are active at C1 or C2.

Meanwhile, in FIG. 6, the column driving circuit 530 receives a third switch PG3 composed of a PMOSFET and an NMOSFET and a predetermined bias voltage VBIAS to allow a constant current to flow between the VDD power supply and the ground. It is further provided. The column driving circuit 530 receives the output reset signal VRES and the image signal VSIG transmitted from the pixels of the APS array in response to read signals READ and READB. M531) outputs the corresponding voltages set at the output node Vout to the analog-to-digital converter 130 (FIG. 1). The READB signal is an inverted signal of the READ signal. When the read signals READ and READB are activated and the third switch PG3 is turned on, both the first switch PG1 and the second switch PG2 are in an OFF state. In FIG. 6, after the output reset signal VRES is generated at the pixel at C1 or C2, when the third switch PG3 is turned on at D1 or D2, the output reset signal VRES is applied to the MOSFET M531. The corresponding voltage set on the output node Vout is output to the analog-to-digital converter 130 of FIG. In E1 or E2, when the third switch PG3 is turned on, the corresponding voltage at which the video signal VSIG is set at the output node Vout by interaction with the MOSFET M531 is the analog- It is output to the digital converter (130 in FIG. 1). The analog-to-digital converter 130 of FIG. 1 converts an analog signal corresponding to the difference of the image signal VSIG to the output reset signal VRES into a digital signal and outputs the digital signal.

Here, the sequential operation of the first pixel circuit 510 and the second pixel circuit 520 is described, but the output reset signal VRES and the image signal VSIG are sequentially performed in the same manner with other pixel circuits of the same column. Outputs

7 is a cross-sectional view of the source follower JFET J1 and the reset and row select gate M12 included in the first pixel circuit 510. FIG. 8 is a diagram for describing a vertical channel of the source follower JFET J1 of FIG. 7. 9 is a plan view of FIG. 7. 7 and 8 are cross-sectional views taken along line AA ′ of FIG. 9. Referring to FIG. 7, the gate electrode 11 of JFET J1 is connected to one source / drain electrode 23 of M12, which corresponds to the FD node. In addition, the source electrode 13 of JFET J1 and the other source / drain electrode 22 of M12 are connected, which corresponds to the output node Vout. The JFET J1 has a "DEEP P-WELL" layer formed between a substrate (P-SUB) and a P-EPI layer, which is an epitaxial layer, as a drain electrode. In JFET J1, current flows through the vertical channel as shown in FIG. The channel of JFET J1 is formed at the edge between the shallow trench isolation (STI) and the depletion layer, as shown in FIG. The J-FET J1 source electrode 13 is three-dimensionally surrounded by STI, and the width of the depletion layer is determined by the potential of the gate electrode 11 of the J-FET J1. In the structure shown in FIG. 7, since the depletion layer grows in one direction (left direction), vertical channels can be formed. In addition, in FIG. 7, when the doping concentration level of the P-EPI is too low, an appropriate impurity doping may be applied to the bottom of the J-FET J1 source electrode 13. In such a J-FET J1 structure, the current path is on the side of the STI and the source follower current flows through the bulk, thereby reducing noise. Therefore, with the source follower JFET J1 structure using only one gate electrode and having a vertical channel structure, as shown in FIG. 9, the source follower JFET J1 of the present invention has almost the same area as a conventional MOSFET. Can be designed.

As described above, in the solid state image pickup device according to the embodiment of the present invention, a JFET that forms a vertical channel is used as the source follower transistor. The JFET is subjected to voltage control of the FD node with only one gate electrode, and a depletion layer is formed toward the STI by such a gate electrode, so that a substantial channel is formed vertically between the edge of the depletion layer and the STI.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the source follower JFET used in the solid-state imaging device according to the present invention uses only one gate electrode and forms a vertical channel structure, so that it can occupy almost the same area as a conventional MOSFET. In the solid-state imaging device according to the present invention, the wiring connecting the gate electrode of the source follower JFET and the FD node and the VDD wiring can be omitted by the pixel circuit structure different from the existing structure. Therefore, a large "fill factor" can be maintained even in small pixels, and the noise generated can be significantly improved.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram showing a general CIS type solid-state imaging device.

FIG. 2 is an example illustrating a Bayer pattern of the APS array of FIG. 1.

3 is a circuit diagram of a unit pixel of the APS array of FIG. 1.

4 is a cross-sectional view illustrating a conventional JFET structure of the source follower transistor of FIG. 3.

FIG. 5 is a view schematically illustrating a column circuit of an APS array implemented in a CIS type solid-state imaging device according to an embodiment of the present invention.

6 is a timing diagram for describing the circuit operation of FIG. 5.

FIG. 7 is a cross-sectional view of a source follower JFET and a reset and row select gate provided for each pixel of FIG. 5.

FIG. 8 is a diagram for describing a vertical channel of the source follower JFET of FIG. 7.

9 is a plan view of FIG. 7.

Claims (13)

An APS array in which pixels are arranged in a two-dimensional matrix, and in each pixel of a selected row, generating and transmitting an output reset signal in response to a pixel reset signal, and transmitting a photoelectrically converted image signal in response to a transfer control signal; A row driver generating a row selection signal that is sequentially activated to select each row of the APS array and to generate the transfer control signal; A column driving circuit configured to generate the pixel reset signal in response to a first reset control signal, and receive the output reset signal and the image signal transmitted from the APS array in response to a read signal and output constant voltages corresponding thereto; And And an analog-digital converter configured to convert an analog signal corresponding to the difference of the video signal with respect to the output reset signal into a digital signal and output the digital signal. The method of claim 1, wherein the column drive circuit, And generating an optical device reset signal in response to the second reset control signal, wherein the optical device provided in the selected pixel of each column is reset in response to the optical device reset signal. The method of claim 1, wherein each of the pixels provided in the APS array, An optical element configured to receive external light and generate the photoelectrically converted image signal; A first MOSFET receiving the transfer control signal, one side of source / drain electrodes connected to the optical device output side, and the other side connected to an FD node; A second MOSFET having a gate electrode receiving the row selection signal, one of the source / drain electrodes connected to the FD node, and the other of the gate / drain electrodes connected to the output node; And A gate electrode is connected to the FD node, one of the source / drain electrodes is connected to the output node, and the other side has a grounded JFET, And transmitting the output reset signal and the video signal through the output node. The method of claim 3, wherein the first MOSFET and the second MOSFET, The solid-state imaging device characterized by the N-channel type. The method of claim 3, wherein the JFET, The solid-state imaging device characterized by the P-channel type. The method of claim 5, wherein the JFET, And a bulk current in a vertically formed channel. The method of claim 5, wherein the JFET, A solid-state imaging device comprising a P-WELL formed between a substrate and a P-EPI layer as a drain electrode. Generating a row selection signal that is sequentially activated to select each row of the APS array; Generating a pixel reset signal in response to the first reset control signal; Generating and delivering an output reset signal in response to said pixel reset signal at each pixel of a selected row of an APS array; Generating a transfer control signal; Delivering, at each pixel of a selected row of an APS array, a photoelectrically converted image signal in response to the transfer control signal; Receiving the output reset signal and the image signal transmitted from the APS array in response to a read signal and outputting predetermined voltages corresponding thereto; And And converting an analog signal corresponding to the difference of the video signal with respect to the output reset signal into a digital signal and outputting the digital signal. The method of claim 8, wherein the solid-state image sensor driving method, Generating an optical device reset signal in response to the second reset control signal, And an optical device provided in a selected pixel of each column of the APS array is reset in response to the optical device reset signal. The method of claim 8, wherein each of the pixels provided in the APS array, A JFET is used as a source follower transistor. The method of claim 10, wherein the JFET, A solid-state image sensor driving method, characterized in that the P-channel type. The method of claim 10, wherein the JFET, And operating by bulk current in a vertically formed channel. The method of claim 10, wherein the JFET, A P-WELL formed between a substrate and a P-EPI layer is a drain electrode.