KR20050114938A - Semiconductor device being able to controll refresh cycle according to temperature - Google Patents

Abstract

There is provided a semiconductor device in which a refresh cycle is adjusted according to temperature. The semiconductor device receives a temperature sensor unit that operates in response to an operation start signal and a clock coding signal that receives an output of the temperature sensor unit and feeds back to the refresh clock control signal and the temperature sensor unit in response to the operation start signal to change the sensed temperature of the temperature sensor unit. It includes a clock control unit for outputting.

Description

Semiconductor device being able to controll refresh cycle according to temperature}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that reduces power consumption and improves consumer reliability by adjusting an appropriate refresh cycle according to temperature.

Normally, cell capacitors store data in the form of electric charges, but because the capacitors are not perfect, the stored charges are dissipated to the outside by leakage currents. Therefore, before the data is completely destroyed, an iterative process of extracting, reading, and rewriting data is required. This is called a refresh operation. In principle, the computer cannot use the DRAM during the refresh operation. The time required for one refresh operation is the same as a normal write operation cycle, after which the external computer can use the DRAM. Therefore, the rate at which the DRAM cannot be used due to the refresh operation is called a busy rate. The shorter the value, the better.

When the computer system is in sleep mode, most of the internal devices are turned off, but the DRAM must be refreshed to keep the data, which causes the self-refresh current to flow through the DRAM. Therefore, it is very important to reduce the self refresh current, especially in battery operated computer systems.

One recent trend in technology development is an attempt to reduce the current by varying the refresh cycle with temperature. The data retention time of the DRAM becomes longer as the temperature decreases, so it is possible to reduce the current consumption by dividing the temperature into several regions and lowering the frequency of the refresh clock relatively at low temperatures.

In the implementation structure of this type, as shown in FIGS. 1A and 1B, the temperature sensor unit 10 has different branches 12 and 14 capable of sensing various temperatures. In some cases, a plurality of temperature sensor result signals Tout1, Tout2, and Tout3 are provided to FIG. 1B). In general, the enable signal has a pulse shape as much as T1 according to a constant period T2 as shown in FIG. 1B. For example, it is a method of determining whether the temperature inside a semiconductor is 45 degreeC, 45 degreeC-70 degreeC, 70 degreeC-90 degreeC by operating a temperature sensor part once every 1 ms.

The clock provider 20 receives a result of a temperature sensor having a plurality of signals Tout1, Tout2, and Tout3 and provides an appropriate refresh clock RFRCK.

This structure has a plurality of temperature sensors that can sense different temperatures to know the more accurate temperature inside the semiconductor, but has the disadvantage of increasing the area of the temperature sensor portion and outputting a plurality of bits.

In addition, as another structure, as shown in FIGS. 2A and 2B, the temperature sensor unit 10 ′ has a variable detecting branch 12 ′ that can variably detect various temperatures. In some cases, a plurality of temperature sensor result signals may be provided to the enable signal EN ′ (see FIG. 2B). In general, the enable signal is in the form of providing a pulse for the time T1 for the number of sensing temperatures according to a constant period T2 as shown in FIG. 2B. For example, it has a temperature detection range similar to that of the conventional refresh clock controller through three temperature sensing operations while changing the sensing temperature into three types of 45 ° C, 70 ° C, and 95 ° C every 1ms.

The clock provider 20 receives a temperature sensor result having a plurality of signals Tout1 ', Tout2', and Tout3 'and provides an appropriate refresh clock RFRCK.

Since the structure of the structure is variable and detects several times, the burden of increasing the area of the temperature sensor unit can be reduced, but the disadvantage of outputting a plurality of bits remains. There is also a burden of providing multiple enable signals.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device that adjusts an appropriate refresh cycle according to temperature.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

The semiconductor device according to the present invention for achieving the above technical problem, receives a temperature sensor unit operating in response to the operation start signal, the output of the temperature sensor unit and is fed back to the refresh clock control signal and the temperature sensor unit in response to the operation start signal And a clock control unit for outputting a clock coding signal for changing the sensed temperature of the temperature sensor unit.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

3A is a block diagram illustrating a refresh clock controller of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, the refresh clock controller 300 constituting the semiconductor device according to an exemplary embodiment of the present invention includes a temperature sensor unit 400, a clock controller 500, and a clock provider 900.

The temperature sensor unit 400 is activated in response to the operation start signal, and is preferably activated by receiving the complementary enable ENB. The final output Tout of the temperature sensor unit 400 is one temperature sensor result signal Tout indicating whether the actual temperature inside the semiconductor is higher than the sensing temperature. For example, in the case of 1 bit, when the sensing temperature is 75 ° C, 0 is output when the actual temperature in the semiconductor is 50 ° C.

The complementary enable signal ENB received by the temperature sensor unit 400 is complementary to the enable signal EN received by the clock controller 500, and the complementary enable signal ENB is changed from high to low. It is preferable to activate the temperature sensor unit. However, it is a matter of course that the temperature sensor unit 400 may be changed so that the clock control unit 500 is activated by the complementary enable signal ENB by the enable signal EN.

The clock coded signal Tx may be configured of a plurality of bits to represent a plurality of sensing temperatures, and adjust a resistance value inside the temperature sensor unit. Preferably, the higher the temperature is detected, the faster the refresh clock is needed, so the less resistance is required. Therefore, the temperature sensor unit 400 has one sensing temperature different from the sensing temperature at the time of inputting the previous operation start signal by the clock coding signal Tx every time the operation start signal is input.

The clock controller 500 is activated in response to the operation start signal. Preferably, it is activated by the enable signal EN as shown in FIG. 3B, receives the temperature sensor result signal Tout, feeds back the clock coding signal Tx to the temperature sensor unit 400, and refreshes the refresh clock control signal ( CK_CONTROL) to the clock provider 900.

The clock provider 900 receives a refresh clock control signal CK_CONTROL and provides a refresh clock RFRCK whose period is adjusted according to an operating temperature of the semiconductor device.

Hereinafter, an operation of the semiconductor device according to the embodiment of the present invention will be described in detail with reference to FIG. 3A.

Referring to Table 1, the temperature sensor unit 400 outputs 0 or 1 as the temperature sensor result signal Tout. The clock controller 500 outputs the refresh clock control signals CK_CONTROL A, B, C, D, E, and F, and the clock coding signals Tx include 30 ° C, 45 ° C, 60 ° C, 75 ° C, and 90 ° C. Generates information about multiple temperatures up to. For example, an area smaller than 30 ° C becomes A, and an area larger than 30 ° C and smaller than 45 ° C is B. The information may be a plurality of bits of information depending on the user. For example, three bits may be represented by A for 000, B for 001, or the like. In addition, when the clock coded signal is also displayed in 3 bits, T30 representing 30 ° C may be represented as 000, and T45 representing 45 ° C may be represented as 001.

After power is supplied to the semiconductor, the clock controller is initialized to E at 75 ° C. for the first time. Initialization values of the temperature sensor unit and the clock control unit are not limited to the above examples. Assume that the temperature inside the semiconductor is 50 ° C.

The temperature sensor unit 400 may detect temperatures of 30 ° C., 45 ° C., 60 ° C., 75 ° C., and 90 ° C. by a method such as resistance control, and if the temperature inside the semiconductor is higher than the detection temperature, the result signal Tout ) Prints '1' and prints '0' if low. Therefore, since the temperature inside the semiconductor is lower than the initial temperature sensor 75 ° C, the temperature sensor result signal Tout outputs '0'.

The clock controller 500 receives '0', outputs 'D' as the refresh clock control signal CK_CONTROL, and outputs a T60 signal, which is a clock coding signal representing 60 ° C, which is lower than 75 ° C, which is the initial set temperature. . The refresh clock control signal and the clock coding signal may include a plurality of bits. When the 3-bit signal is used, the refresh clock control signal CK_CONTROL becomes '011', and the clock coding signal Tx, T60, becomes '010'. This can be

Next, the temperature sensor unit 400 receives the clock coding signal Tx, and is changed to change the resistance value inside the temperature sensor unit so as to sense 60 ° C., and again in response to the operation start signal. 50 ℃ is compared and '0' is output as temperature sensor result signal (Tout). Accordingly, the clock controller outputs 'C' 010 as the refresh clock control signal CK_CONTROL and outputs 'T45' (001) indicating 45 ° C. as the clock coding signal Tx.

Thirdly, when the temperature sensor unit 400 is operated, the temperature sensor result signal Tout is outputted as '1', and the clock controller outputs the 'C' 010 as the second refresh clock control signal CK_CONTROL. The clock coded signal Tx outputs 'T60' (010) indicating 60 ° C. If the temperature inside the semiconductor stays at 50 ° C., the sensing temperature of the temperature sensor part passes between 45 ° C. and 60 ° C., and the clock control part continuously outputs 'C'. Accordingly, since the clock provider 900 provides the refresh clock RFRCK according to the refresh clock control signal CK_CONTROL, a constant refresh clock is maintained.

In conclusion, the temperature sensor unit 400 detects an external temperature, continuously changes the detected temperature according to the received clock coding signal Tx, and compares the detected external temperature with the external temperature. In addition, the clock controller 500 may output a clock coding signal Tx different from the clock coding signal at the time of input of the previous enable signal EN according to the temperature sensor result signal Tout provided by the temperature sensor unit 400. Feedback to the temperature sensor unit (400). The refresh clock control signal CK_CONTROL is also provided to the clock providing unit 900.

When the temperature inside the semiconductor changes, the temperature sensor unit 400 and the clock controller 500 change while tracking the temperature inside the semiconductor as described above. Therefore, the refresh clock RFRCK also changes with temperature.

Therefore, despite the fact that the temperature inside the semiconductor can be subdivided into several pieces, the temperature sensor part has only one sensing temperature in one operation, and the clock sensor signal is received every time the clock sensor signal is received. Each point has a different sensing temperature than the previous operation, and is distinguished from the conventional refresh clock control method.

4 is a block diagram illustrating an interior of a temperature sensor unit of FIG. 3A.

Referring to FIG. 4, the temperature sensor unit 400 of the semiconductor device according to an embodiment of the present invention is activated with a complementary enable signal ENB and receives a clock coding signal Tx to provide a sensor output signal OS. It includes a temperature sensor 410.

The sensor output signal controller 440 receives the sensor output signal OS and outputs a temperature sensor result signal Tout. The sensor output signal OS mainly refers to a voltage value obtained by changing the reference voltage value and the clock coding signal Tx, and compares the magnitudes of the two voltage values by a comparator so that the temperature sensor result signal Tout. '0' and '1' are printed.

FIG. 5 is a block diagram illustrating the clock controller of FIG. 3A.

Referring to FIG. 5, a clock controller 500 of a semiconductor device according to an embodiment of the present invention may be activated by an enable signal EN and provide a pulse providing unit 700 and a temperature sensor. The intermediate processing unit 600 and the intermediate processing signal MC and the enable pulse which receive the temperature sensor result signal Tout and the clock coding signal Tx provided by the unit 400 and provide the intermediate processing signal MC. And a clock control signal providing unit 800 for receiving the clock coding signal Tx and the refresh clock control signal CK_CONTROL.

Enable pulses preferably provide pulses when enable signal EN falls from high to low. Further, the intermediate processing signal MC processes and provides one bit of the temperature sensor result signal Tout and a plurality of bits of the clock coding signal Tx by the plurality of NAND calculation units.

The refresh clock control signal providing unit 800 includes a plurality of units, each of which is activated by an enable pulse and receives an intermediate processing signal and processes the NAND operation unit to control the clock coding signal Tx and the refresh clock. Provide the signal CK_CONTROL. In the present invention, a plurality of units are classified into two types, and the two types of units have only the difference in whether the value initialized by the power supply voltage is high or low, and the operation principle is the same.

Hereinafter, exemplary circuit diagrams of respective parts of the refresh clock controller of the semiconductor device of the present invention will be described with reference to FIGS. 6 to 9B. Of course, the present invention is not limited by the following experimental examples.

6 is a circuit diagram illustrating the temperature sensor of FIG. 4.

Referring to FIG. 6, the temperature sensor 410 receives a complementary enable signal ENB, receives a first PMOS transistor 411 that transfers a power supply voltage Vcc, and a second that receives a sensing temperature voltage OTa. The PMOS transistor 412 and the third and fourth PMOS transistors 413 and 414 that receive the reference voltage Oref are included. In addition, the first PMOS transistor 414 and the third NMOS transistor 417 includes a first 1,2,3 NMOS transistors 415, 416, 417 which are driven at the same time receives the voltage. And a fourth, fifth, sixth and seventh NMOS transistors 420, 421, 422, and 423 and a resistor unit 425. The second and third NMOS transistors 416 and 417 are configured to receive the clock coded signal Tx. ) Include diodes 418 and 419 respectively.

The first PMOS transistor 411 receives the complementary enable signal ENB and transfers a power supply voltage Vcc. Since the second PMOS transistor 412 is controlled by the sensing temperature voltage OTa, the second PMOS transistor 412 transfers the power supply voltage only in one direction. When the sensing temperature voltage OTa goes from low to high, the second PMOS transistor 412 is controlled. Is turned off. The operation manners of the third and fourth PMOS transistors 413 and 414 are the same. In addition, when the voltage between the fourth PMOS transistor 414 and the third NMOS transistor 417 goes from low to high, the first, second and third NMOS transistors 415, 416, 417 are turned on to supply power ( Vcc).

The voltage between the first NMOS transistor 415 and the resistor 425 is defined as Va, and the current flowing between the first NMOS transistor 415 and the resistor 425 is defined as Ia. Since the resistor unit 425 may be sized by the clock coding signal Tx, Va changes by the clock coding signal Tx. For example, when the clock coding signal T45 of about 45? Is input, only the fourth NMOS transistor 420 is turned on and the remaining NMOS transistors are turned off, so that Ia increases. Therefore, the sensing temperature voltage OTa changes according to the clock coding signal.

On the other hand, since the ratio of the current driving capability of the first diode 418 and the second diode 419 is M: 1, the current Ir flowing between the second NMOS transistor 416 and the first diode 418 is represented by the following equation. Equation 1 It can be seen that the current Ir is proportional to the current driving capability ratio M and the absolute temperature T, and inversely proportional to the resistance values R and 424 and the charge amount q. Therefore, the reference voltage Oref can be calculated according to the value of Ir. In the temperature sensor 410, the sensing temperature OTa and the reference voltage Oref are provided as the sensor output signal OS.

7 is an exemplary circuit diagram of the sensor output signal controller of FIG. 4.

Referring to FIG. 7, the sensor output signal controller 440 compares a voltage OTa corresponding to a sensing temperature, which is a sensor output signal OS received from the temperature sensor 410, with a voltage Oref corresponding to a reference voltage. A comparator 441, a PMOS transistor for receiving the enable signal EN and a NMOS transistor for receiving the complementary enable signal ENB, and transmitting a value provided by the comparator. A first transmission gate 442, an inverter 443a for reversing the value transmitted from the first transmission gate 442, and an inverter 443a that is operated by receiving an input signal opposite to the first transmission gate 442. A second transmission gate (445) for delivering a value provided by < RTI ID = 0.0 >), < / RTI > and a second inverter (446a) for reversing the value transferred at the second transmission gate (442).

By further connecting a third inverter 443b to the inverter 443a by a latch, charge is distributed at a point where the first transmission gate 442 and the second transmission gate 445 are connected to each other so that the sensor It is possible to prevent the output signal OS from being floated (a state in which it is impossible to determine whether it is high or low);

Since the third inverter 443b latches the value provided by the sensor output signal OS through the comparator, the widths of the PMOS transistors and the NMOS transistors constituting the third inverter 443b are determined by the inverter. It is preferable to design smaller than the widths of the PMOS transistors and the NMOS transistors constituting the 443a to facilitate the transition of the values provided by the sensor output signal OS through the comparator. The fourth inverter 446b is also designed in the same manner as the third inverter 443b.

The sensor output signal controller 440 opens only the first transmission gate while the temperature sensor 410 is operated by the complementary enable signal ENB, so that the sensor output signal OS receives the value provided by the comparator. It is stored in the latch portions 443a and 443b. After that, when the complementary enable signal ENB becomes high, the first transmission gate 442 is closed, and the second transmission gate 445 is opened, and the value stored in the first latch parts 443a and 443b is stored in the second latch part ( 446a and 446b are provided as a temperature sensor result signal Tout.

8 is an exemplary circuit diagram illustrating the clock controller of FIG. 3A.

Referring to FIG. 8, the clock controller 500 includes an intermediate processor 600, a pulse provider 700, and a clock controller 800.

The intermediate processor 600 calculates an inverter 610 for inverting the temperature sensor result signal Tout, a temperature sensor result signal Tout, an inverted temperature sensor result signal, and a clock coding signal Tx having a plurality of bits. It includes a plurality of NAND operation unit (620 to 696).

The pulse providing unit 700 outputs an enable signal EN and output signals of three series inverters (inverter chains 710, 720, and 730) to which the enable signal EN is input through the NO operation unit 740. Provide the calculated value.

When the enable signal EN is activated, the output signals of the inverter chains 710, 720, and 730 are activated after a predetermined delay time, so that a pulse is provided during the delay time.

The pulse provider 700 adjusts the number of inverters of the inverter chains 710, 720, and 730 because the delay time of the enable signal EN increases in proportion to the number of inverters of the inverter chains 710, 720, and 730. To control the time the pulse is provided.

The number of inverters in the inverter chains 710, 720, 730 must be odd and can be deactivated after a predetermined delay time.

The refresh clock control signal providing unit 800 is activated by an enable pulse provided by the pulse providing unit 700, and calculates and outputs an intermediate processing signal MC provided by the intermediate processing unit 600. A plurality of clock control units 810 to 896 is included. The units 810 to 896 are composed of two types, and the two types of units have the same operation principle except that the value initialized by the power supply voltage is high or low. Two input values are calculated and output through the NAND calculator. The detailed structure is mentioned later.

When the clock coding signal Tx input to the temperature sensor is 'T45' and the refresh clock control signal CK_CONTROL is 'C', when the temperature sensor result signal Tout is '0', the clock controller 500 may clock. It should output 'T30' as the coding signal Tx and 'B' as the refresh clock control signal CK_CONTROL. This process will be described in detail with reference to FIG. 8.

Since the temperature sensor result signal Tout is low, it is high by the inverter 610. The clock coded signal Tx is high only at T45 and the rest is low. Therefore, a high and a low are input to the NAND calculator 620 and a high is output. Since the two high are input to the NAND calculator 630, a low is output. Therefore, high and low are input to the clock control unit 820, and thus high is output by the NAND operation. That is, T30 is output as the clock coding signal Tx.

In addition, since two rows are input to the NAND calculator 640, a high is output. Therefore, a high and a low are input to the unit 830, and thus a high is output by the NAND operation. That is, 'B' is output as the refresh clock control signal CK_CONTROL.

On the other hand, it can be seen that all the remaining output values are low by the same method. Accordingly, it can be seen that the refresh clock RFRCK is provided while changing the clock coding signal Tx and the refresh clock control signal CK_CONTROL according to the temperature inside the semiconductor.

9A is a circuit diagram of a clock control unit UNIT A that sets the initial value of FIG. 8 to low.

A first inverter transferring an output value through an inverter 811 for reversing an enable pulse (Enable), an NAND calculator 812 for receiving and calculating Input 1 and Input 2, which are intermediate processing signals MC, and an NAND operator 812. A transmission gate 813, a first inverter 814a that reverses the value transmitted through the first transmission gate, a second transmission gate 815 that transmits the value reversed by the inverter 814a, and a second And a second inverter 816a that reverses the value passed through the transmission gate. Also, a signal controlled by an initial set and grounded NMOS transistor 817, an inverter 818 for inverting an initial set, and an inverter 818 for inverting an initial set are determined to determine an initial value. And a PMOS transistor 819 that receives an input and delivers a power supply voltage Vcc.

The charge is distributed at the point where the first transmission gate 813 and the second transmission gate 815 are connected by further connecting a third inverter 814b to the first inverter 814a by a latch. In this case, the intermediate processing signals MC, Input1 and Input2, can be prevented from being floated (floating).

Since the third inverter 814b latches a value calculated by the intermediate processing signal MC through the NAND operator, the widths of the PMOS transistors and the NMOS transistors constituting the third inverter 814b are The width of the PMOS transistors and the NMOS transistors constituting the inverter 814a may be smaller than the widths of the PMOS transistors and the NMOS transistors, thereby facilitating the transition of the values calculated by the NAND calculation unit.

Upon receiving an initial set, the NMOS transistor 817 initializes the point A between the first transmission gate 813 and the inverter 814a to low, and receives an inverted initial set to receive the initial set. The MOS transistor 819 transfers a power supply voltage Vcc to initialize the B point between the second transmission gate 815 and the inverter 816a to high. Therefore, the output value is initialized to low. Thereafter, when the NAND operation unit 812 calculates the intermediate processing signal MC and outputs high by being activated by the enable pulse Enable, the point A becomes high and the value inverted by the inverter 814a is transferred. The point B goes low. Therefore, high is output as a result value (Output).

FIG. 9B is a circuit diagram of a clock control unit UNIT B that sets the initial value of FIG. 8 to high, and the same or corresponding parts as in FIG. 9A are denoted by the same reference numerals, and description thereof will be omitted.

Upon receiving an initial set, the NMOS transistor 887 initializes the point B 'between the second transmission gate 815 and the inverter 816a to low, and receives an inverted initial set. The PMOS transistor 889 transfers the power supply voltage Vcc to initialize the A 'point between the first transmission gate 813 and the inverter 814a to high. Therefore, the output value is initialized high. After that, when the NAND operation unit 882 calculates Input 1 and Input 2, which are the intermediate processing signals MC, and outputs a low by the enable pulse Enable, the A 'point becomes low and is driven by the inverter 884a. Because the inverted value is passed, the B 'point goes high. Therefore, a row is output as a result value (Output).

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the semiconductor device and the method in which the refresh period as described above is adjusted, there are one or more of the following effects.

Even with temperature changes, the refresh cycle can be properly adjusted to reduce power consumption, reduce DRAM busyness, and increase consumer confidence.

1A is a block diagram illustrating a refresh clock controller of a conventional semiconductor device.

1B is a signal diagram illustrating an enable signal for controlling a refresh clock cycle of a conventional semiconductor device.

2A is a block diagram illustrating a refresh clock control unit of another conventional semiconductor device.

2B is a signal diagram illustrating an enable signal for controlling a refresh clock cycle of another conventional semiconductor device.

3A is a block diagram illustrating a refresh clock controller of a semiconductor device according to an embodiment of the present invention.

3B is a signal diagram illustrating an enable signal for controlling a refresh clock cycle of a semiconductor device according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating a temperature sensor unit of FIG. 3A.

FIG. 5 is a block diagram illustrating a clock controller of FIG. 3A.

6 is an exemplary circuit diagram of a temperature sensor configuring the temperature sensor unit of FIG. 4.

7 is an exemplary circuit diagram of the sensor output signal controller of FIG. 4.

8 is an exemplary circuit diagram of the clock controller of FIG. 3A.

9A is a circuit diagram of a clock control unit UNIT A that sets the initial value of FIG. 8 to a low signal.

9B is a circuit diagram of a clock control unit UNIT B that sets the initial value of FIG. 8 to a high signal.

 (Explanation of symbols for the main parts of the drawing)

300: refresh clock control unit 400: temperature sensor unit

410: temperature sensor 440: sensor output signal control unit

500: clock control unit 600: intermediate processing unit

700: pulse providing unit 800: refresh clock control signal providing unit

900: clock provider

Claims (6)

A temperature sensor unit operable in response to an operation start signal; And a clock controller configured to receive an output of the temperature sensor unit and output a refresh clock control signal and a clock coding signal fed back to the temperature sensor unit to change a sensed temperature of the temperature sensor unit in response to the operation start signal. The semiconductor device of claim 1, further comprising a clock providing unit configured to receive the refresh clock control signal and provide a refresh clock. The semiconductor device according to claim 1, wherein the output of the temperature sensor unit is one signal. The semiconductor device of claim 1, wherein the temperature sensor unit has one sensing temperature that is different from a sensing temperature when a previous operation start signal is input by the clock coding signal. The clock controller of claim 4, wherein the clock controller receives a previous clock coding signal generated when a previous operation start signal is input, and receives an output of the temperature sensor unit to generate a clock coding signal different from the previous clock coding signal. Semiconductor device. Sensing an external temperature; And And a refresh clock controller interlocked with a temperature for performing a step of raising or lowering the sensing temperature according to the sensing result of the external temperature.