KR20050109344A - Apparatus for identifying a chip - Google Patents

Abstract

The present invention relates to a device for identifying a chip, by storing a chip number in a chip using a lot number, a wafer number in a lot, and an XY coordinate on the chip, and enabling the chip to be identified in a test mode. During testing, it can identify which part of a wafer is located and which process has been processed, which can be linked to process steps to facilitate cause analysis.

Description

Apparatus for identifying a chip

The present invention relates to an apparatus for identifying a chip, and more particularly, to an apparatus for identifying a chip capable of identifying a chip using a lot number, a wafer number in a lot, and an XY coordinate in a wafer. .

Typically, testing is done at wafer level or packaged after the semiconductor fabrication process is complete. At this time, when a defect occurs, the cause is analyzed in various ways. Since a special ID is not assigned to the chip, there is a problem that it is difficult to analyze the cause in connection with the process step.

In contrast, the apparatus for identifying a chip according to the present invention stores a chip number on a wafer using a lot number, a wafer number in a lot, and an XY coordinate on the chip, and makes it possible to confirm the result in a test mode. In addition, it is possible to identify which part of a wafer is located in a chip test and to determine which process has been performed, which can be connected to the process step to facilitate cause analysis.

An apparatus for identifying a chip according to an embodiment of the present invention includes a plurality of fuses for storing the chip identification information in a cutting state, and outputs the information according to the address signal.

The apparatus for identifying a chip according to another embodiment of the present invention controls the entry into the test mode according to the test mode control signal, and outputs the chip identification information when the chip identification mode is selected among the test modes according to the test mode selection signal. A test mode control means for outputting an enable signal, a plurality of fuses for storing chip identification information in a cutting state, a fuse box for outputting these information according to an address signal, and a chip in accordance with an output enable signal And output control means for outputting identification information to the input / output pins.

In the above description, the fuse box may include a first fuse block for displaying a lot number, a first fuse block for displaying a wafer number to distinguish a plurality of wafers included in the lot, and an area where a chip is located on the wafer. And a third fuse block for displaying.

In this case, four first fuse blocks may be provided to display the lot number in hexa form, and two third fuse blocks may be provided to display the lot number.

Meanwhile, any one of the first to third fuse blocks may be connected between the first node and the power supply voltage terminal, and transmit the power supply voltage to the first node according to a control signal before reading the cutting state of the fuses. Precharge means for precharging the plurality of fuses, the plurality of fuses connected in parallel to the first node and having the chip identification information stored therein for cutting, and the coded signals of the address signals respectively connected between the fuses and the ground terminal. The potential of the first node, which is dependent on the cutting state of the fuses connected to the switched-on switching elements when the coded signals are input in sequence and some of the switching elements are turned on, including a plurality of switching elements whose on / off is determined accordingly. Indicates chip identification information.

The apparatus may further include an address input detector configured to detect input of coded signals to generate an output enable signal, and a buffer to output the potential of the first node according to the output enable signal.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 is a block diagram illustrating an apparatus for identifying a chip according to an embodiment of the present invention.

Referring to FIG. 1, an apparatus for identifying a chip according to an embodiment of the present invention may include a fuse box 110, a test mode control means 120, and an output control means 130, and may identify a chip. The identification signal is output to the outside through the input and output pins 140. The detailed description of each component is as follows.

First, when the test mode enable signal mrsp6 is initially input, the test mode control means 120 generates a test mode enable signal so that peripheral circuits can operate in the test mode. In this case, the test type is determined according to the test mode selection signal At <0:10> input when the test mode enable signal mrsp6 is applied. Which test is determined according to the test mode selection signal At <0:10> may be changed according to a combination of signals, which is already known and a detailed description thereof will be omitted.

On the other hand, when entering the identification mode for identifying the chip according to the test mode selection signal At <0:10>, the test mode control means 120 outputs the enable signal Tm_wafcode of the chip identification mode.

The fuse box 110 is composed of a plurality of fuse blocks, a lot number in the cutting state of the fuse, a wafer number to distinguish the number of wafers among the plurality of wafers included in the lot, and a plurality of chips in the wafer The data for representing the XY coordinates are stored in order to determine which part is located in the chip.

A specific embodiment will be described below.

The fuse block may be composed of 10 fuses, and the chip may be identified by reading cutting states of the fuses using signals encoded by five address signals (for example, Add <2: 6>) applied after entering the test mode. can do.

First, four fuse blocks 111 to 114 are used to express lot numbers 0000 to 9999 in hexa form, and one fuse block 115 to represent wafer numbers 0 to 25. Is used, two fuse blocks 116 and 117 may be used to represent the XY coordinates of the chip on the wafer. In this case, a total of seven fuse blocks 111 to 117 are required. Each fuse block has the same configuration, and only the cutting state of the fuse is different.

FIG. 2 is a circuit diagram for describing a configuration and an operation of the fuse block illustrated in FIG. 1.

Referring to FIG. 2, the fuse block includes a plurality of fuses (shown as 10 in the drawing; F101 to F110) connected in parallel to the first node A, the respective fuses F101 and F110 and a ground terminal. The first node A is connected to a plurality of switching elements T101 to T110 connected between the plurality of switching elements T101 to T110 and determined on / off according to coded address signals Add <2: 6>. It is connected between, and includes a precharge means (T111) for precharging the first node (A) by transmitting a power supply voltage in accordance with the control signal (xredstpb) before reading the cutting state of the fuses (F101 and F110) It is done by

The potential of the first node A varies according to the cutting state of the fuses F101 and F110 and the on / off states of the switching elements T101 to T110, and the potential of the first node A is the buffer N102. And INV105). According to the output signal, it is possible to distinguish which chip is located on which part of which wafer and which part of the lot. Through this, it is possible to easily identify the problem by associating the chip under what process conditions.

In the above configuration, precharge holding means INV101 and T112 for maintaining the precharge state of the first node A may be further included. The apparatus may further include an address input detector 111a that detects input of coded address signals Add <2: 6> and generates an output enable signal.

First, the operation of the fuse block having the above configuration will be described.

First, the fuse cutting at the wafer level records which chips were placed on which part of the wafer. For example, the chip case where the X-Y coordinate of the second wafer of the first lot is located at 2-3 will be described as an example. In this case, the first, third, and seventh fuses F101, F103, and F107 are used in the fuse block (eg, 114) displaying the lowest number among the fuse blocks (111 to 114 in FIG. 1) indicating the lot number. Is cut. In the fuse block 115 indicating the wafer number, the second, third and seventh fuses F102, F103 and F107 are cut. In the fuse block 116 representing the X coordinate of the wafer, the second, third and seventh fuses F102, F103 and F107 are cut. In the fuse block 117 representing the Y coordinate of the wafer, the first, fourth and seventh fuses F101, F104, and F107 are cut.

In this state, the address signals Add <2: 6> are coded as shown in Table 1 below and input in order.

A6 A5 A4 A3 A2 j i h g f e d c b a order 00000 0 0 0 One 0 0 0 One 0 One One 00001 0 0 0 One 0 0 0 One One 0 2 00010 0 0 0 One 0 0 One 0 0 One 3 00011 0 0 0 One 0 0 One 0 One 0 4 00100 0 0 0 One 0 One 0 0 0 One 5 00101 0 0 0 One 0 One 0 0 One 0 6 00110 0 0 0 One One 0 0 0 0 One 7 00111 0 0 0 One One 0 0 0 One 0 8 01000 0 0 One 0 0 0 0 One 0 One 9 01001 0 0 One 0 0 0 0 One One 0 10 01010 0 0 One 0 0 0 One 0 0 One 11 01011 0 0 One 0 0 0 One 0 One 0 12 01100 0 0 One 0 0 One 0 0 0 One 13 01101 0 0 One 0 0 One 0 0 One 0 14 01110 0 0 One 0 One 0 0 0 0 One 15 01111 0 0 One 0 One 0 0 0 One 0 16 10000 0 One 0 0 0 0 0 One 0 One 17 10001 0 One 0 0 0 0 0 One One 0 18 10010 0 One 0 0 0 0 One 0 0 One 19 10011 0 One 0 0 0 0 One 0 One 0 20 10100 0 One 0 0 0 One 0 0 0 One 21 10101 0 One 0 0 0 One 0 0 One 0 22 10110 0 One 0 0 One 0 0 0 0 One 23 10111 0 One 0 0 One 0 0 0 One 0 24 11000 One 0 0 0 0 0 0 One 0 One 25 11001 One 0 0 0 0 0 0 One One 0 26 11010 One 0 0 0 0 0 One 0 0 One 27 11011 One 0 0 0 0 0 One 0 One 0 28 11100 One 0 0 0 0 One 0 0 0 One 29 11101 One 0 0 0 0 One 0 0 One 0 30 11110 One 0 0 0 One 0 0 0 0 One 31 11111 One 0 0 0 One 0 0 0 One 0 32

In the above, when the address '00000' is first input after the control signal xredstpb is applied as a low pulse and the first node A is precharged, the first address is used as the coded signals a to j. The first, third, and seventh switching elements T101, T103, and T107 are turned on and the remaining switching elements are turned off, respectively, by being applied to the tenth to tenth switching elements T101 to T110. In this case, since the first, third, and seventh fuses F101, F103, and F107 are cut in the fourth fuse block 114 (FIG. 1), a current path from the first node A to the ground terminal is not formed. Therefore, the precharge state of the first node A is maintained as it is. Accordingly, in the fourth fuse block 114, the potential of the first node A may be output at a high level through the buffers N102 and INV105 to identify the chip included in the first lot. On the other hand, since at least one of the first, third and seventh fuses F101, F103 and F107 is kept uncut in the other fuse block, a current path is formed and all low signals are output.

Subsequently, when the control signal xredstpb is applied again with a low pulse so that the first node A is precharged and the address '00001' is input for the second time, the first address is input as the coded signals a to j. The second, third, and seventh switching elements T102, T103, and T107 are turned on and the remaining switching elements are turned off, respectively, by being applied to the tenth to tenth switching elements T101 to T110. In this case, the second, third and seventh fuses F102, F103, and F107 are cut in the fifth and sixth fuse blocks 115 and 116 of FIG. 1, and thus, the first node A to the ground terminal. Since no current path is formed, the precharge state of the first node A is maintained as it is. Therefore, in the fifth and sixth fuse blocks 115 and 116, the potential of the first node A is output at a high level through the buffers N102 and INV105 to the first of the wafers included in the first lot. It can be identified that the included chip, and at the same time it can be seen that the X coordinate of the chip is located on the wafer 2. On the other hand, at least one of the second, third and seventh fuses F1022, F103 and F107 is kept uncut in the other fuse block, so that a current path is formed and all low signals are output.

Subsequently, when the control signal xredstpb is applied again with a low pulse so that the third address '00010' is input after the first node A is precharged, the address is reset to the coded signals a to j. The first, fourth, and seventh switching elements T101, T104, and T107 are turned on and the remaining switching elements are turned off, respectively, by being applied to the first to tenth switching elements T101 to T110. In this case, since the first, fourth, and seventh fuses F101, F104, and F107 are cut in the seventh fuse block 117 of FIG. 1, a current path from the first node A to the ground terminal is not formed. Therefore, the precharge state of the first node A is maintained as it is. Therefore, in the seventh fuse block 117, the potential of the first node A is output at a high level through the buffers N102 and INV105, so that the Y coordinate at which the chip is positioned on the wafer is 2. On the other hand, at least one of the first, fourth and seventh fuses F101, F104, and F107 is kept uncut in the other fuse block, so that a current path is formed and all low signals are output.

Thereafter, the same operation proceeds. However, as described above, in the case of the chip located in the portion where the X-Y coordinate of the second wafer of the first lot is 2-3, all information can be obtained at the time of input of the third address.

Meanwhile, the configuration and operation of the address input detector 111a shown in FIG. 2 will be described below.

The address input sensing unit 111a is connected between the second node B and the ground terminal in parallel, and includes a plurality of switching elements T113 to T116 to which a coded address signal Add34 <0: 3> is applied. A switching element T117 connected between the power supply voltage terminal VDD and the second node B to initialize the second node B according to the control signal xredstpb, and latches a potential of the second node B. The latch LAT1 and the buffers N101 and INV104 which transmit the output signals of the latch LAT1 to the buffers N102 and INV105 are included. In the above, although the address signals Add34 <0: 3> coded to the switching elements T113 to T116 are input, other coded address signals Add2 <0: 1> or Add56 <0: 3> are applied. It's okay.

The address input detection unit 111a having the above-described configuration outputs a low level signal by precharging the second node B by the control signal xredstpb before inputting the address, and this signal is output to the buffers N102 and INV105. To prevent the fuse block from operating. In this state, when a coded address signal is applied, at least one of the switching elements T113 to T116 is turned on to form a current path. Accordingly, the address input detector 111a outputs a high level signal, and the signal is applied to the buffers N102 and INV105 so that the fuse block operates normally.

As such, the address input detector 111a detects that the coded address signal is applied and outputs data from the fuse block only when the coded address signal is applied.

As described above, the present invention stores the chip number on the wafer using the lot number, the wafer number in the lot, and the XY coordinates on the chip, and makes it possible to confirm this in the test mode, thereby determining the It can identify where it was located and determine what process has been carried out, which can be linked to the process steps to facilitate cause analysis.

1 is a block diagram illustrating an apparatus for identifying a chip according to an embodiment of the present invention.

FIG. 2 is a circuit diagram for describing a configuration and an operation of the fuse block illustrated in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

110: fuse box 111 to 117: fuse block

120: test mode control means 130: output control means

140: input / output pins

Claims (8)

And a fuse including a plurality of fuses for storing the chip identification information in a cutting state, the fuse box outputting the information according to an address signal. Test mode control means for controlling entry to a test mode according to a test mode control signal, and outputting an output enable signal of chip identification information when a chip identification mode is selected among the test modes according to a test mode selection signal; A fuse box including a plurality of fuses for storing the chip identification information in a cutting state and outputting the information according to an address signal; And And output control means for outputting the chip identification information to an input / output pin in accordance with the output enable signal. The method according to claim 1 or 2, The fuse box may include a first fuse block for displaying lot numbers; A first fuse block for displaying a wafer number to distinguish a plurality of wafers included in the lot; And And a third fuse block for displaying an area in the wafer where the chip is located in coordinates. The method of claim 3, wherein And identifying the chip having four first fuse blocks for displaying the lot number in hexa form. The method of claim 3, wherein And a chip having two third fuse blocks to display the coordinates. The method of claim 3, wherein any one of the first to third fuse block, Precharge means connected between a first node and a power supply voltage terminal, for precharging the first node by transferring a power supply voltage to the first node according to a control signal before reading the cutting state of the fuses; A plurality of fuses connected in parallel to the first node and having the chip identification information stored therein; Including a plurality of switching elements each connected between the fuses and the ground terminal and on / off determined according to coded signals of the address signals, When the coded signals are input in order and a part of the switching elements is turned on, the chip representing the chip identification information may be identified as a potential of the first node that is dependent on the cutting state of the fuses connected to the turned on switching elements. Device. The method of claim 6, Each of the fuses and the switching elements may include ten, one of the first and second fuses, one of the third to sixth fuses, and one of the seventh to tenth fuses may be disconnected. And a coded signal is applied to the switching elements in order as shown in Table 2 below. order Switching element 10 Switching element 9 Switching element 8 Switching element 7 Switching element 6 Switching element 5 Switching element 4 Switching element 3 Switching element 2 Switching element 1 One 0 0 0 One 0 0 0 One 0 One 2 0 0 0 One 0 0 0 One One 0 3 0 0 0 One 0 0 One 0 0 One 4 0 0 0 One 0 0 One 0 One 0 5 0 0 0 One 0 One 0 0 0 One 6 0 0 0 One 0 One 0 0 One 0 7 0 0 0 One One 0 0 0 0 One 8 0 0 0 One One 0 0 0 One 0 9 0 0 One 0 0 0 0 One 0 One 10 0 0 One 0 0 0 0 One One 0 11 0 0 One 0 0 0 One 0 0 One 12 0 0 One 0 0 0 One 0 One 0 13 0 0 One 0 0 One 0 0 0 One 14 0 0 One 0 0 One 0 0 One 0 15 0 0 One 0 One 0 0 0 0 One 16 0 0 One 0 One 0 0 0 One 0 17 0 One 0 0 0 0 0 One 0 One 18 0 One 0 0 0 0 0 One One 0 19 0 One 0 0 0 0 One 0 0 One 20 0 One 0 0 0 0 One 0 One 0 21 0 One 0 0 0 One 0 0 0 One 22 0 One 0 0 0 One 0 0 One 0 23 0 One 0 0 One 0 0 0 0 One 24 0 One 0 0 One 0 0 0 One 0 25 One 0 0 0 0 0 0 One 0 One 26 One 0 0 0 0 0 0 One One 0 27 One 0 0 0 0 0 One 0 0 One 28 One 0 0 0 0 0 One 0 One 0 29 One 0 0 0 0 One 0 0 0 One 30 One 0 0 0 0 One 0 0 One 0 31 One 0 0 0 One 0 0 0 0 One 32 One 0 0 0 One 0 0 0 One 0 The method of claim 6, An address input detector for detecting an input of the coded signals and generating an output enable signal; And And a buffer for outputting a potential of the first node in accordance with the output enable signal.