KR20050108980A - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device. In the present invention, a data selection block is disposed at the top and the bottom, respectively, and the main data line and the redundancy I / O bus signal of the redundancy I / O decoding block through the data selection block. Outputs any one of the data transmitted through the redundancy data line. Therefore, the present invention can improve the performance of the semiconductor chip by minimizing the transmission delay of the repair I / O bus signal. In addition, the lines of the signal BRBUS of the redundancy control block transmitted from the bottom to the top can be reduced as much as possible. Through this, the entire signal arrangement of the semiconductor chip can be optimized more, thereby optimizing the semiconductor chip area and improving the performance of the semiconductor chip.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for minimizing a delay of a transmission time of redundancy control block signals in a semiconductor memory device employing a repair scheme of a memory cell. It is about.

The input / output (I / O) repair method of a semiconductor memory device includes a 1: 1 (ont to one) method in which a specific redundancy cell can repair only a specific I / O, and a specific redundancy cell is an arbitrary I. There is a random method that only repairs / O.

First, the redundancy control method is relatively simple because the redundancy cell block is physically allocated to a specific I / O. In addition, repair is possible for a fail cell having the same address of different I / Os. However, since there are few redundant cell blocks allocated to each I / O, when the address of a fail cell increases for one I / O, a problem cannot be repaired. Therefore, there is a disadvantage in that more redundancy cell blocks need to be allocated to improve the repair capability.

The random scheme can repair any I / O of each redundant cell block, and this scheme can increase the repair capability because a redundant cell block can be allocated to each I / O as much as possible. However, this scheme is relatively complicated because each redundant cell block must replace an arbitrary I / O, and the same column / row address failure of different I / Os may occur. In this case, repair is not possible depending on how the redundancy control scheme is configured.

In general, a NAND flash memory device uses a global column repair method and a random I / O repair method. As an example, a random I / O repair method of a NAND flash memory device will be described below with reference to FIG. 5.

As shown in FIG. 5, 'REP <N: 0>', which is a signal output from each address fuse block (not shown) of the redundancy control blocks 14a and 14b, is physically coded to the redundancy decoders 13a and 13b. (coding) Accordingly, when a specific column address is input, a specific signal REP is generated by the address fuse block, and the data of the specific redundancy cell in the redundancy cell array 11 causes the redundancy data line rDL to be generated by the signal REP. Is sent through. Meanwhile, the signals 'TRBUS <3: 0> and BRBUS <3: 0>', which are output from the I / O fuse blocks (not shown) of the redundancy control blocks 14a and 14b, are tops based on the cell array. Is muxed by the redundancy bus select block 15 disposed at. The redundancy bus select block 15 generates a single repair I / O bus signal 'RBUS <3: 0>'. The signal RBUS <3: 0> is decoded into 'RIO <15: 0>' by the redundancy I / O decoding block 16. Any one of these signals RIO <15: 0> is enabled and the corresponding I / O is repaired.

In addition, in the case of a NAND flash memory device, the main cells of the main cell array 10 and the redundancy cells of the redundancy cell array 11 are alternately arranged in a top and bottom. Therefore, the redundancy control blocks 14a and 14b are also arranged in top and bottom. However, the signals TRBUS <3: 0> and BRBUS <3: 0> of each of the redundancy control blocks 14a and 14b disposed at the top and the bottom are muxed and output by one redundancy bus select block 15. . The top and bottom redundancy data lines rDL are connected to one data selection block 17, and the data transmitted through these rDLs are selected through the data selection block 17. Therefore, the columns of the main memory cell array 11 arranged on the top may also be repaired using the redundancy cells arranged in the bottom. On the contrary, the columns of the main memory cell array 11 arranged in the bottom may be repaired by using the redundancy cells arranged on the top.

Basically, the redundancy control blocks 14a and 14b start to operate when the address is changed and require approximately 5 ns of time until the signal 'REP' for controlling the data of the redundancy cell is generated. In addition, the time taken to generate the 'RBUS <3: 0>' signal containing the I / O information to be repaired and decoded in the redundancy I / O decoding block 16 to finally replace the I / O to be repaired You need about 5ns. In this case, when the DQ pad is disposed on the top, 'BRBUS <3: 0>' generated in the bottom is transmitted to the top, which delays approximately 5ns. This is due to the RC loading of the signal transmission line. In fact, the operation of the redundancy cell on the 512M product is delayed by about 10ns to 15ns compared to the operation of the main memory cell, which affects various AC characteristics and margins, leading to degradation of the chip performance.

Accordingly, the present invention has been made to solve the above problems, and provides a semiconductor memory device which can improve the performance of a semiconductor chip by minimizing a delay time required to transfer a bottome repair I / O bus signal BRBUS. Its purpose is to.

According to an aspect of the present invention for realizing the above object, in the main memory cell array, first and second page buffers and column decoders are disposed at the top and the bottom, respectively, to input and output main data to the main cell, and a redundancy array. The first and second redundancy decoders are respectively disposed at the top and the bottom to input and output repair data, and the first and the second redundancy control blocks are respectively placed at the top and the bottom to control the operation of the first and second redundancy decoders. In this arranged semiconductor memory device, a first and a second redundancy control block is disposed in the top and bottom, respectively, and decodes the first signal of the first and second redundancy control block and outputs the first and second redundancy I / O bus signals, respectively. And a second redundancy I / O decoding block and top and bottom, respectively, arranged through the first and second main data lines, respectively, for the first and second page buffers and column decodes. Further connected to the first and second redundancy decoders through first and second redundancy data lines, respectively, and the first and second main data according to the first and second redundancy I / O bus signals. A semiconductor memory device including first and second data selection blocks for transmitting any one data of each of the main data transmitted through the line and each of the repair data transmitted through the first and second redundancy data lines to the data line. Is provided.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 is a block diagram illustrating a semiconductor memory device according to a preferred embodiment of the present invention, and FIG. 2 is a block diagram of the redundancy control block shown in FIG. 1. Here, the semiconductor memory device refers to any memory device to which the repair scheme of the memory cell is applied, and the NAND flash memory device is illustrated as an example for convenience of description.

1 and 2, a NAND flash memory device according to a preferred embodiment of the present invention includes a main memory cell array 110 and a redundancy memory cell array 111. The main memory cell array 110 and the redundancy memory cell array 111 are composed of a plurality of strings, and one string is formed by connecting a plurality of cells (16 or 32) in series.

Page buffers and column decoders 112a and 112b are disposed at the top and bottom of the main memory cell array 110, respectively. In general, a column gate (not shown) is disposed at the top of the page buffer, which is controlled by a column decoder that decodes an external address. However, for the sake of simplicity, only the column decoder is shown here. Likewise, a page buffer and a column gate are disposed in the top and bottom of the redundancy memory cell array 111, respectively. However, for the sake of convenience of explanation, only the redundancy decoders 113a and 113b will be described herein. That is, the illustrated redundancy decoders 113a and 113b include page buffers and column gates. Normally, page buffer and column decoders 112a and 112b are selected by redundancy address fuse blocks 1141 (0) to 1141 (N) (see Fig. 2) operating in accordance with external addresses. If one of the page buffers and column decoders 112a and 112b arranged in the top and bottom is selected, the other is configured not to be selected.

The redundancy memory cell array 111 may be formed of, for example, 2N redundancy strings. In this case, 2N redundancy page buffers (not shown) are disposed at the top and the bottom of the redundancy memory cell array 111, and 2N redundancy column gates (not shown) are respectively disposed at the top and the bottom to correspond to the redundancy page buffer. do. That is, the redundancy decoders 113a and 113b are arranged. Each of the redundancy decoders 113a and 113b is controlled by the signals 'REP <N: 0>' output from the redundancy address fuse blocks 1141 (0) to 1141 (N).

In the NAND flash memory device according to the preferred embodiment of the present invention, the redundancy control blocks 114a and 114b are disposed at the top and the bottom, respectively, and as shown in FIG. 2, the redundancy control blocks 114a and 114b are multiplied. Redundancy address fuse blocks 1141 <0> through 1141 <N> and redundant I / O fuse blocks 1142 (0) through 1142 (N) are required for the I / O repair by the number of redundancy columns to be repaired. Meanwhile, the output signals IOBUS <3: 0> of the redundancy I / O fuse blocks 1142 <0> to 1142 <N> correspond to 'TRBUS <3: 0>' and 'BRBUS <3: 0>'. do.

The redundancy address fuse blocks 1141 <0> to 1141 <N> output 'REP <0> to' REP <N> 'according to an external address to be repaired during the repair operation. The signal REP <N: 0> is transmitted to the redundancy I / O fuse blocks 1142 <0> to 1142 <N> and the redundancy decoders 113a and 113b to control them. The redundancy I / O fuse blocks 1142 (0) to 1142 (N) correspond to information on which column of the main memory cell array 110 is to be repaired when the signal REP <N: 0> is input. Outputs the signal IOBUS <3: 0>.

The NAND flash memory device according to an exemplary embodiment of the present invention has a redundancy I / O decoding block 115a for decoding signals 'TRBUS <3: 0>' and 'BRBUS <3: 0>' at the top and the bottom, respectively. , 115b). The redundancy I / O decoding blocks 115a and 115b decode 'TRBUS <3: 0>' and 'BRBUS <3: 0>', respectively, to display 'TRIO <15: 0>' and 'BRIO <15: 0>'. Output '

In the NAND flash memory device according to the preferred embodiment of the present invention, data selection blocks 116a and 116b are disposed at the top and the bottom. The data selection blocks 116a and 116b are connected to the page buffers and the column decoders 112a and 112b through the main data lines TDL <15: 0> and BDL <15: 0>, respectively, and the redundancy data lines TrDL, BrDL) is connected to the redundancy decoders 113a and 113b, respectively. For example, the data selection block 116a may select one of the main data line TDL <15: 0> and the redundancy data line TrDL according to the 'TRIO <15: 0>' data line DL <15: 0>. ). The configuration of such data selection blocks 116a and 116b is shown in FIG. As shown in FIG. 3, the data selection blocks 116a and 116b are composed of a plurality of data selection units 1161 (0) to 1161 (N). Here, 'N' is 15, i.e., there are 16 data selectors. Each of the data selectors 1161 <0> to 1161 <N> includes an inverter INV and transfer gates TG1 and TG2 as shown in FIG. 4.

An operation characteristic of the data selectors 1161 <0> to 1161 <N> will be described with reference to FIG. 4. First, in a non-repair operation, 'RIO' is input at a low level ('0'). As a result, the transfer gate TG1 is turned on and the main data line 'nDL' is connected to the data line DL. On the other hand, in the repair operation, when 'RIO' is input at a high level '1', the transfer gate TG2 is turned on so that the redundancy data line rDL is connected to the data line DL. As a result, data of the main memory cell is output during the non-repair operation, and data of the redundancy memory cell is output during the repair operation.

Meanwhile, the data transmission block 117 shown in FIG. 1 transmits the transmitted data to the DQ pad via the data lines DL <15: 0>.

Hereinafter, operation characteristics of a NAND flash memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 4. However, the main cell arranged in the tower uses the top redundancy control block 114a to be replaced with the redundancy cells arranged in the tower, and the main cell arranged in the batum is replaced with the redundancy cell arranged in the batum. 114b) may be used. That is, since the repair operation is performed in the same way as the top and the bottom, only the repair operation of the main cell disposed on the top will be described here.

When the address is input, the top redundancy control block 114a is enabled to generate 'TREP <N: 0>' and 'TRBUS <3: 0>', thereby generating the top redundancy I / O decoding block 115a. 'TRIO <15: 0>' is created. At this time, the data of the redundancy cell is loaded on the top redundancy data line TrDL by 'TREP <15: 0>', and the data of the main cell is loaded on the top main data line TDL <15: 0>. Data carried on each data line TrDL and TDL <15: 0> is transferred to the top data selection block 116a. The top data selection block 116a selects and outputs any one of the data through the data lines TrDL and TDL <15: 0> according to 'TRIO <15: 0>'. That is, during the repair operation, data transmitted through the top main data line TDL <15: 0> is cut off, and only data transmitted through the top redundancy data line TrDL is output. In contrast, during the non-repair operation, data transmitted through the top main data line TDL <15: 0> is output, and only data transmitted through the top redundancy data line TrDL is blocked.

Hereinafter, a chip operating speed of a NAND flash memory device according to an exemplary embodiment of the present invention and a NAND flash memory device according to the related art shown in FIG. 5 will be compared.

First, when main data is input to the main memory cell array 10 in the NAND flash memory device according to the related art as shown in FIG. 5, the main data is directly passed through the data selection block 17 and the bottom page buffer and column. It is input to the decoder 12a. However, when the repair data input to the redundancy memory cell array 11 is input, it must wait until any one of 'RIO <15: 0>' is enabled. However, in order for 'RIO <15: 0>' to be enabled, the redundancy control block 14a is enabled to generate 'BRBUS <3: 0>' and this 'BRBUS <3: 0>' is placed on top. It must be delivered to the redundancy bus select block 15, resulting in a delay of approximately 5 ns. Of course, about 5 ns is delayed even when the main data is transmitted to the bottom page buffer and the column decoder 12b. As a result, the repair data is input to the redundancy memory cell array 11 about 15 ns slower than the main data is input to the main memory cell array 10.

However, in the case of a NAND flash memory device according to an exemplary embodiment of the present invention, first, main data is input to the data transfer block 117 and the bottom redundancy control block (BUM) is used for the time input to the bottom page buffer and the column decoder 112b. Since 114b) is enabled, a time delay of about 5 ns in which main data is transmitted from the data transfer block 117 to the bottom page buffer and the column decoder 112b can be saved. In addition, since the redundancy I / O decoding blocks 115a and 115b are disposed not only in the top but also in the bottom, respectively, the time of about 5 ns, which is the delay time that 'BRBUS <3: 0>' was transmitted to the top in the prior art, is also provided. I can eliminate it. As a result, data input speeds of 10ns or more overall can be saved. On the other hand, when outputting data in the prior art 'BRBUS <3: 0>' can be eliminated the time delay of about 5ns that was sent to the tower, it is possible to improve the speed more than 5ns.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a data selection block is disposed at the top and the bottom, respectively, and the main data line and the redundancy data according to the redundancy I / O bus signal of the redundancy I / O decoding block through the data selection block. By outputting any one of the data transmitted through the line, it is possible to minimize the transmission delay of the repair I / O bus signal generated in the prior art to improve the performance of the semiconductor chip. In addition, the lines of the signal BRBUS of the redundancy control block transmitted from the bottom to the top can be reduced as much as possible. Through this, the entire signal arrangement of the semiconductor chip can be further optimized, thereby optimizing the semiconductor chip area and improving the performance of the semiconductor chip.

1 is a block diagram of a NAND flash memory device illustrated to explain a semiconductor memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of the redundancy control block shown in FIG. 1.

3 is a block diagram of a data selection block shown in FIG. 1.

4 is a configuration diagram illustrating a data selector shown in FIG. 3.

5 is a configuration diagram illustrating a NAND flash memory device illustrated in order to describe a semiconductor memory device according to the related art.

<Explanation of symbols for main parts of drawing>

10, 110: main memory cell array

11, 111: redundancy memory cell array

12a, 12b, 112a, 112b: page buffer and column decoder

13a, 13b, 113a, 113b: redundancy decoder

14a, 14b, 114a, 114b: redundancy control block

15: Redundancy bus select block

16, 115a, 115b: redundancy I / O decoding block

17, 116a, 116b: data selection block portion

117: data transmission block

Claims (3)

In the main memory cell array, first and second page buffers and column decoders are respectively disposed at the top and the bottom to input and output the main data to the main cell, and the first and the second buffers are respectively placed at the top and the bottom to input and output the repair data to the redundancy array. A semiconductor memory device having a second redundancy decoder and a first and a second redundancy control block disposed at a top and a bottom, respectively, for controlling an operation of the first and second redundancy decoder. First and second redundancy I / O decoding blocks disposed at the top and the bottom, respectively, and decoding first signals of the first and second redundancy control blocks to output first and second redundancy I / O bus signals, respectively. ; And Disposed on the top and bottom, respectively, and connected to the first and second page buffers and column decoders through first and second main data lines, respectively; and the first and second through first and second redundancy data lines, respectively. A main data transmitted through the first and second main data lines and the first and second redundancy data lines according to the first and second redundancy I / O bus signals. And first and second data selection blocks for transmitting one of the repair data to a data line. The method of claim 1, The first and second data selection blocks connect the first and second redundancy data lines and the data lines by the first and second redundant I / O bus signals, respectively, during a repair operation. And the first and second main data lines and the data lines, respectively, by the first and second redundancy I / O bus signals. The method of claim 1, The first and second data selection blocks are enabled according to the first and second redundancy I / O bus signals to select one of the main data and the repair data and transmit the selected data to the data line. A semiconductor memory device.