KR20050097066A - Driving circuit for bit line sense amplifer - Google Patents

Abstract

The present invention relates to a bit line sense amplifier driving circuit. In particular, an external voltage is applied to a pull-up terminal according to a low level control signal after a column enable signal is enabled, and is applied to a high level control signal after a delay time of a delay unit. As a result of the high integration and low voltage by applying the core voltage to the pull-up terminal, the loading of the local I / O line of the DRAM increases and the core voltage gradually decreases, thereby causing the bit line and the bit by the loading of the local I / O line when the column enable signal is enabled. A bit line sense amplifier drive circuit is proposed that can prevent the error of data caused by the line bar level being changed at the core voltage level.

Description

Driving circuit for bit line sense amplifer

The present invention relates to a bit line sense amplifier driving circuit, and more particularly, by supplying a core voltage after a column enable signal is enabled in a read operation of a DRAM and after supplying an external voltage to a pull-up terminal of a bit line sense amplifier for a predetermined period. The present invention relates to a bit line sense amplifier driving circuit capable of securing ρV of a local input / output line by correcting the levels of bit lines and bit line bars.

FIG. 1 is a diagram illustrating a bit line sense amplifier and a data path around the bit line in a typical DRAM. FIG. 2 is a waveform diagram of a bit line BL and a bit line bar BLb during a read operation. As shown in FIG. 1, in a typical DRAM, the bit line sense amplifier 11 is formed in a cross-coupled form between a pull-up voltage terminal rto and a pull-down voltage terminal sb to form a bit line BL and a bit line bar BLb. Amplify by sensing data. For the read operation using the bit line sense amplifier 11, the word line is enabled to the pumping voltage VPP level by the row address strobe signal RAS, and charge sharing between the cell capacitor and the bit line load is performed. ) Is generated to generate a voltage difference ΔV between the bit line BL and the bit line bar BLb. The bit line sense amplifier 11 is operated by using the voltage difference ΔV to amplify the bit line BL and the bit line bar BLb to the core voltage Vcore level. The amplified data is transferred to local input / output lines lio and liob through data input / output lines sio and siob according to the column enable signal yi. The column enable signal yi is generated by the column address strobe signal CAS. The cell data of the data input / output lines (sio and siob) are amplified by the input / output sense amplifier through the local input / output lines (lio and liob) by the column enable signal yi, and the amplified data are global input / output lines (gio and giob). ) Is output to DQ.

The bit line BL and the bit line bar BLb have high levels when the data is in a high state, and the bit line BL is in a high state, and the bit line bar BLb is in a low state. On the contrary, when the data is in the low state, the bit line BL is in the low state and the bit line bar BLb is in the high state. However, in the trend of high integration and low voltage DRAM, the column enable signal yi is enabled to transfer the data of the data input / output lines si and siob to the local input / output lines lio and liob. And loading of the liob may affect the data of the bit line BL and the bit line bar BLb to cause data errors.

In order to prevent such a problem, there is a method of reducing the loading of local input / output lines (lio and liob). To this end, the DRAM core is divided into quarter banks, and the size of the banks is reduced to reduce the length of the local I / O lines lio and liob, thereby reducing the loading of the local I / O lines lio and liob. However, this method has a disadvantage in that the area increases because the configuration for controlling each bank must be increased.

An object of the present invention is to provide a bit line sense amplifier driving circuit which can prevent a problem that a data error occurs due to the bit line and bit line bars are affected by the loading of the local input and output lines.

According to another object of the present invention, when the column enable signal is enabled, the bit line and bit line bar levels are changed to the core voltage level after the pull-up terminal of the bit line sense amplifier is raised to an external voltage level in a predetermined period. It is to provide a bit line sense amplifier driving circuit that can prevent the change according to the loading of the line to prevent the wrong data is transmitted through the data input and output lines or the margin of the voltage difference between the bit line and the bit line bar is reduced.

The bit line sense amplifier driving circuit according to the present invention includes a control unit for inputting a column enable signal to generate a control signal whose state changes according to a delay time, and according to the control signal, the pull-up enable signal, and the pull-down enable signal. A first driver for applying a core voltage and a ground voltage to a pull-up terminal and a pull-down terminal of a bit line sense amplifier, and the pull-up of the bit line sense amplifier according to the control signal, the pull-up enable signal, and the pull-down enable signal And a second driver for applying an external voltage and the ground voltage to the terminal and the pull-down terminal, respectively.

The control unit includes a delay unit for delaying the column enable signal, an inverter for inverting the output signal of the delay unit, a NAND gate for inputting the column enable signal and the output signal of the inverter to output a control signal. It includes.

The controller outputs the control signal at a low level for a time corresponding to a delay time of the delay unit after the column enable signal is enabled.

The first driver further includes a bit line precharge unit configured to apply a bit line precharge voltage to the pull-up terminal and the pull-down terminal of the bit line sense amplifier according to a bit line equalization signal.

The first driver may include a first voltage supply unit for applying the core voltage to the pull-up terminal of the bit line sense amplifier according to the control signal and the pull-up enable signal, and according to the control signal and the pull-down enable signal. And a second voltage supply unit for applying the ground voltage to the pull-down terminal of the bit line sense amplifier.

The first voltage supply unit is connected in series between the core voltage terminal and the pull-up terminal with a first PMOS transistor driven according to the inverted signal of the control signal and a second PMOS transistor driven according to the pull-up enable signal.

The second voltage supply unit is connected in series between the pull-down terminal and the ground terminal with a first NMOS transistor driven in accordance with the pull-down enable signal and a second NMOS transistor driven in accordance with the control signal.

The second driver may include a first voltage supply unit for applying the external voltage to the pull-up terminal according to the control signal and the pull-up enable signal, and the bit line sense amplifier according to the control signal and the pull-down enable signal. And a second voltage supply unit for applying the ground voltage to the pull-down terminal.

The first voltage supply unit is connected in series between a first PMOS transistor driven according to the control signal and a second PMOS transistor driven according to the pull-up enable signal.

The first voltage supply unit further includes a plurality of diodes selectively driven according to a switch between the second PMOS transistor and the pull-up terminal.

The second voltage supply part is connected in series between the pull-down terminal and the ground terminal with a first PMOS transistor driven in accordance with the control signal and a second PMOS transistor driven in response to the inverted signal of the pull-down enable signal.

The second voltage supply unit further includes a plurality of diodes selectively driven according to a switch between the pull-down terminal and the first PMOS transistor.

In the bit line sense amplifier driving circuit according to the present invention, after the column enable signal is enabled, the second driver is driven in accordance with the low level control signal to apply the external voltage to the pull-up terminal, and After the delay time, the first driver is driven according to the high level control signal to apply the core voltage to the pull-up terminal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 is a control circuit diagram for controlling a bit line sense amplifier driving circuit according to the present invention.

The delay unit 21 delays the column enable signal yi, and the column enable signal yi delayed by the delay unit 21 is inverted by the inverter I21. The NAND gate 22 inputs the column enable signal yi and the output signal of the inverter I21 and then logically combines them to output a control signal (enablez). The external voltage Vext supply time of the bit line sense amplifier driving circuit is determined according to the delay time of the delay unit 21.

As shown in the waveform diagram of FIG. 4, the control circuit of the bit line sense amplifier driving circuit according to the present invention configured as described above is performed in a first section t1 in which the column enable signal yi is disabled and applied in a low state. The first inverter I21 outputs a signal in a high state so that the control signal enable is output in a high state. On the other hand, the first inverter I21 outputs a high state signal until a second section t2 where the column enable signal yi is enabled and applied in a high state, and the control signal is enabled in a low state. . However, the column enable signal yi is kept high and the first inverter I21 outputs a low signal in the third section t3 so that the control signal is enabled. In addition, after the fourth period t4 in which the column enable signal yi is disabled again and applied in a low state, the first inverter I21 outputs a high state signal so that the control signal is enabled. Is output.

FIG. 5 is a circuit diagram illustrating a bit line sense amplifier driving circuit according to an embodiment of the present invention, in which a first driver 300 for supplying a core voltage Vcore to a pull-up terminal rto of a bit line sense amplifier and a pull-up terminal rto of a bit line sense amplifier are shown. The second driver 400 supplies an external voltage Vext having a voltage higher than the core voltage Vcore.

The first driver 300 pulls up the core voltage Vcore and the ground voltage Vss according to the control signal, the pull-up enable signal rto_en, and the pull-down enable signal sb_en, and the pull-up terminal rto and the pull-down terminal. each to (sb). In addition, the second driver 400 pulls up the external voltage Vext and the ground voltage Vss according to the control signal, the pull-up enable signal rto_en, and the pull-down enable signal sb_en. It is applied to pull-down terminal sb, respectively. However, the first driver 300 is driven when the control signal (enablez) is applied in a high state, and the second driver 400 is driven when the control signal (enablez) is applied in a low state. At this time, the column enable signal yi is enabled, the pull-up enable signal rto_en is applied in a low state, and the pull-down enable signal sb_en is applied in a high state.

The configuration of the first driver 300 is as follows. First and second PMOS transistors P31 and P32 are connected in series between the core power supply terminal Vcore and the pull-up terminal rto, and the first PMOS transistor P31 is inverted through the first inverter I31. The second PMOS transistor P32 is driven according to the signal enable, and the second PMOS transistor P32 is driven according to the pull-up enable signal rto_enz. The first NMOS transistor N31 is connected between the bit line precharge power supply terminal Vblp and the pull-up terminal rto, and the second NMOS transistor (between the bit line precharge power supply terminal Vblp and the pull-down terminal sb). N32 is connected, and a third NMOS transistor N33 is connected between the pull-up terminal rto and the pull-down terminal sb, and the first to third NMOS transistors N31 to N33 are bit line equalization signals bleq, respectively. Driven by). These first to third NMOS transistors N31 to N33 are configured to initially precharge the pull-up terminal rto and the pull-down terminal sb according to the bit line equalization signal bleq. The fourth and fifth NMOS transistors N34 and N35 are connected in series between the pull-down terminal sb and the ground terminal Vss, and the fourth NMOS transistor N34 is driven according to the pull-down enable signal sb_en. The fifth NMOS transistor N35 is driven according to the control signal enable.

The configuration of the second driver 400 is as follows. The third and fourth PMOS transistors P33 and P34 are connected in series between the external power supply terminal Vext and the first node Q31, and the third PMOS transistor P33 is driven according to the control signal enablez, The fourth PMOS transistor P34 is driven according to the pull-up enable signal rto_en. Diode-connected sixth and seventh NMOS transistors N36 and N37 are connected between the first node Q31 and the pull-up terminal rto, respectively, which are implemented according to the first and second switches SW31 and SW32. As an optional part, it controls the external power supply Vext supplied to the pull-up terminal rto. Diode-connected eighth and ninth NMOS transistors N38 and N39 are connected between the pull-down terminal sb and the second node Q32, respectively, which are implemented according to the third and fourth switches SW33 and SW34. It is an optional part. The fifth and sixth PMOS transistors P35 and P36 are connected in series between the second node Q32 and the ground terminal Vss, and the fifth PMOS transistor P35 is driven according to the control signal enablez, The 6 PMOS transistor P36 is driven according to the pull-down enable signal sb_en inverted by the second inverter I32.

The driving method of the bit line sense amplifier driving circuit according to the present invention configured as described above will be described with reference to the waveform diagram of FIG. 4.

When the column enable signal yi is disabled and applied in the low state, the control circuit outputs a high state control signal enablez in the first period t1. The control signal in the high state is inverted to the low state through the first inverter I31 to turn on the first PMOS transistor P31 and to turn on the fifth NMOS transistor N35. The third and fifth PMOS transistors P33 and P35 are turned off by the control signal in the high state. However, before the column enable signal yi is enabled, the pull-up enable signal rto_en is applied in a high state, and the pull-down enable signal sb_en is applied in a low state. Accordingly, the second and fourth PMOS transistors P32 and P34 are turned off by the pull-up enable signal rto_en in the high state, and the fourth NMOS transistor N34 is turned off by the pull-down enable signal sb_en in the low state. Is turned off, and the sixth PMOS transistor P36 is turned off by a signal in which the pull-down enable signal sb_en of the low state is inverted to the high state by the second inverter I32. Thus, the input / output sense amplifier drive circuit is disabled.

When the column enable signal yi is enabled and applied in a high state, the control circuit outputs a control signal enablez in a low state until the second period t2. At this time, since the column enable signal yi is enabled, the pull-up enable signal rto_en is applied in a low state, and the pull-down enable signal sb_en is applied in a high state. However, the first PMOS transistor P31 is turned off by the control signal enablez inverted to the high state by the first inverter I31 and the fifth NMOS transistor N35 by the control signal enablez in the low state. ) Is turned off, so the first driver 300 is not driven. On the other hand, the third and fifth PMOS transistors P33 and P35 are turned on by the low state control signal (enablez), and the fourth PMOS transistor P34 is turned on by the pull-up enable signal rto_en in the low state. Since the sixth PMOS transistor P36 is turned on by the pull-down enable signal sb_en inverted to the low state by the second inverter I32, the second driver 400 is driven. Accordingly, the external power source Vext is applied to the pull-up terminal rto by the second driver 400, and the pull-down terminal sb maintains the potential of the ground voltage Vss.

The column enable signal yi is enabled and applied in the high state, and in the third period t3, the control circuit outputs the control signal enablez in the high state. At this time, the pull-up enable signal rto_en is applied in a low state, and the pull-down enable signal sb_en is applied in a high state. However, the first PMOS transistor P31 is turned on by the control signal enableable inverted to the low state by the first inverter I31, and the fifth NMOS transistor N35 is driven by the control signal enableable in the high state. Since is turned on, the first driver 300 is driven. On the other hand, since the third and fifth PMOS transistors P33 and P35 are turned off by the control signal enable in the high state, the fourth PMOS transistor P34 is turned on by the pull-up enable signal rto_en in the low state. And the sixth PMOS transistor P36 is turned on by the pull-down enable signal sb_en inverted to the low state by the second inverter I32, the second driver 400 is not driven. Accordingly, the core voltage Vcore is applied to the pull-up terminal rto by the first driver 300, and the pull-down terminal sb maintains the potential of the ground voltage Vss.

On the other hand, since the pull-up enable signal rto_en is applied to the high state and the pull-down enable signal sb_en is applied to the low state after the fourth period t4 in which the column enable signal yi is disabled again. The input / output sense amplifier drive circuit is disabled.

As described above, the bit line sense amplifier driving circuit according to the present invention has a delay time of the delay unit 21 of the control circuit (Fig. 3) after the column enable signal yi is enabled and the control signal is enabled. The pull-up terminal rto of the bit line sense amplifier is raised to the external voltage Vext level until the second period t2 determined according to the step, and after the delay time of the delay unit, that is, the bit line sense amplifier in the third period t3. The pull-up terminal rto of is changed to the core voltage Vcore level. 6 is an output waveform diagram of a bit line using the bit line sense amplifier driving circuit according to the present invention. Therefore, the margin of the voltage difference ΔV between the bit line and the bit line bar due to the loading of the local input / output line is reduced, thereby preventing an error of data generated.

As described above, according to the present invention, as the integrated voltage and the low voltage are supplied by supplying the core voltage after supplying the external voltage to the pull-up terminal of the bit line sense amplifier for a predetermined period, the loading of the local input / output line of the DRAM increases and the core voltage gradually decreases. Therefore, when the column enable signal is enabled, it is possible to prevent data errors caused by the bit line and bit line bar levels being changed at the core voltage level by loading of the local input / output lines.

1 illustrates a data path including a bitline sense amplifier in a typical DRAM.

2 is an output waveform diagram of a bit line in a typical DRAM.

3 is a control circuit diagram for controlling a bit line sense amplifier driving circuit according to the present invention;

4 is an input / output waveform diagram of a control circuit for controlling a bit line sense amplifier driving circuit according to the present invention;

5 is a bit line sense amplifier driving circuit diagram in accordance with the present invention.

6 is an output waveform diagram of a bit line using the bit line sense amplifier drive circuit according to the present invention.

Claims (13)

A controller for inputting a column enable signal to generate a control signal whose state changes according to a delay time; A first driver configured to apply a core voltage and a ground voltage to a pull-up terminal and a pull-down terminal of a bit line sense amplifier according to the control signal, the pull-up enable signal, and the pull-down enable signal, respectively; And And a second driver configured to apply an external voltage and the ground voltage to the pull-up terminal and the pull-down terminal of the bit line sense amplifier according to the control signal, the pull up enable signal and the pull down enable signal. Driving circuit. The apparatus of claim 1, wherein the controller comprises: a delay unit for delaying the column enable signal; An inverter for inverting the output signal of the delay unit; And And a NAND gate for inputting the column enable signal and the output signal of the inverter to output a control signal. The bit line sense amplifier driving circuit of claim 1 or 2, wherein the controller outputs the control signal at a low level for a time corresponding to a delay time of the delay unit after the column enable signal is enabled. The bit line sense device of claim 1, wherein the first driver further comprises a bit line precharge unit configured to apply a bit line precharge voltage to the pull-up terminal and the pull-down terminal of the bit line sense amplifier according to a bit line equalization signal. Amplifier driving circuit. The display device of claim 1, wherein the first driver comprises: a first voltage supply unit configured to apply the core voltage to the pull-up terminal of the bit line sense amplifier according to the control signal and the pull-up enable signal; And And a second voltage supply unit configured to apply the ground voltage to the pull-down terminal of the bit line sense amplifier according to the control signal and the pull down enable signal. The semiconductor device of claim 5, wherein the first voltage supply unit comprises a first PMOS transistor driven according to an inversion signal of the control signal and a second PMOS transistor driven according to the pull-up enable signal between the core voltage terminal and the pull-up terminal. A bit line sense amplifier drive circuit connected in series with the circuit. 6. The second voltage supply unit of claim 5, wherein the second voltage supply unit has a first NMOS transistor driven according to the pulldown enable signal and a second NMOS transistor driven according to the control signal connected in series between the pulldown terminal and the ground terminal. Bitline sense amplifier drive circuit. The display device of claim 1, wherein the second driver comprises: a first voltage supply unit configured to apply the external voltage to the pull-up terminal according to the control signal and the pull-up enable signal; And And a second voltage supply unit configured to apply the ground voltage to the pull-down terminal of the bit line sense amplifier according to the control signal and the pull down enable signal. 9. The apparatus of claim 8, wherein the first voltage supply unit is connected in series between the external voltage terminal and the pull-up terminal by connecting the first PMOS transistor driven in accordance with the control signal and the second PMOS transistor driven in response to the pull-up enable signal. Bit line sense amplifier drive circuit. 10. The bit line sense amplifier driving circuit of claim 9, wherein the first voltage supply unit further comprises a plurality of diodes selectively driven according to a switch between the second PMOS transistor and the pull-up terminal. 10. The display device of claim 8, wherein the second voltage supply unit is configured between a first PMOS transistor driven according to the control signal and a second PMOS transistor driven according to an inverted signal of the pulldown enable signal between the pulldown terminal and the ground terminal. Bitline sense amplifier drive circuit connected in series. 12. The bit line sense amplifier driving circuit of claim 11, wherein the second voltage supply unit further comprises a plurality of diodes selectively driven according to a switch between the pull-down terminal and the first PMOS transistor. The method of claim 1, wherein after the column enable signal is enabled, the second driver is driven in accordance with a low level control signal to apply the external voltage to the pull-up terminal, and the high level after a delay time of the delay unit. And a first line driving unit for applying the core voltage to the pull-up terminal according to the control signal.