KR20050089117A - Method to transmit data in pci 2.2 using prefetch request - Google Patents

Abstract

The present invention is to improve the data transfer efficiency by using the prefetch request in PCI 2.2, the address of the next memory read command and the amount of data to be read in advance to the target device by using the memory write command of the bus master This allows you to prepare the exact amount of data to send from the target device.

The bus master using a memory write command to store an address of a memory read command to be requested next and a size of data to be read in a prefetch control register; Prefetching corresponding data from a target device using information stored in the prefetch control register and storing the data in a buffer; The target device relates to a data transmission method using a prefetch request in PCI 2.2, comprising: receiving a read command applied from a bus master and transmitting prefetched data to the bus master.

Description

Method to transmit data in PCI 2.2 using prefetch request}

The present invention relates to a data transfer method using a prefetch request in PCI 2.2. More specifically, the address of a memory read command to be requested next and the amount of data to be read are notified to the target device in advance by using a memory write command of a bus master. The present invention relates to a data transmission method using a prefetch request in PCI 2.2, which enables more efficient data transmission using a prefetch request.

Generally, Peripheral Component Interconnect (PCI) bus is a data transmission bus that improves the slow data transmission speed of the previous Besa-local bus method as a bus for data transmission, and the CPU is a host-PCI bridge. This type of PCI bus system consists of a PCI bridge, an Arbiter connected to the PCI bus, and a PCI device connected to the PCI bus. In such a PCI bus system, an expansion bus bridge is often connected to the PCI bus. The expansion device is connected to this expansion bus bridge via an expansion bus.

The PCI bus is designed to operate independently of the CPU and generally operates at 33 MHz with 32-bit bus width. In recent years, the performance of the CPU and memory has been improved, and peripheral devices including network cards and disk controllers have been improved. As a result, the PCI bus that connects them becomes a bottleneck for the entire system, and a PCI-X interface has been developed for more efficient bus utilization and is used for servers and workstations that require high-speed data transfer.

However, most computers still support the PCI 2.2 bus, and the PCI 2.2 bus is also applied in various fields such as set-top boxes, communication systems, real-time systems, and factory automation systems. PCI-X supports the PCI 2.2 protocol. As an optional additional protocol, all PCI-X devices support the PCI 2.2 protocol, so the performance of the PCI 2.2 bus will greatly affect the performance of the entire system.

When the PCI 2.2 bus master wants to read data from the target device, the target device prepares the data for internal transmission. When the bus master requests a memory read command from the target device, the target device internally transmits the data. Data is prepared. Especially for PCI device with local bus, it needs time to read data from local device. So, it should occupy PCI bus without any data transfer. If local bus is slow Ramen occupies the PCI bus for a long time to transmit data, which reduces bus utilization and data transmission efficiency.

As a result, the PCI 2.2 specification uses a delayed transaction mechanism as shown in FIG. 1A. When the bus master A requests a memory read command from the target device B as shown in FIG. Device B terminates the protocol with a retry process to indicate that data cannot be transmitted. Target device B starts to prepare data by itself using the address that it remembers. This is called prefetch. When the data master is ready to transfer data, the bus master A transmits the prepared data as shown in FIG. 1B when the bus master A requests the same memory read command again.

The delay transaction mechanism used in PCI 2.2 is used when bus master A transfers data with another target device while target device B prepares data requested by bus master A, or bus master B It can be used to improve the efficiency of the PCI bus.

However, when the delayed transaction mechanism is used in PCI 2.2, there are the following problems.

First, if there is less data prefetched by the target device than the data that the bus master wants to read, the target device will no longer be able to transmit data, so the protocol will be terminated by disconnection. The bus is again licensed by the arbiter and requests data as a read command for the rest of the data transfer.As a result, when the bus master is again licensed by the bus and the target device terminates the protocol by retrying, the protocol is free again. Since the data must be fetched, the overall data transfer efficiency is lowered, which causes a problem that the bus utilization and data transfer efficiency are further reduced when the bus master attempts to read a large amount of data at one time.

Second, if the bus master reads less data than the data prefetched by the target device and terminates the protocol, then if the target device is still prefetching data from the lower bus, it immediately terminates and the target device Any remaining data already prefetched is discarded, since there is no guarantee that the bus master will reread the remaining data from the target device. There is no problem even if the target device discards the remaining data.

If the bus master attempts to read a large amount of data but inevitably terminates the protocol due to an internal problem or a timeout termination of the bus master, the bus master will definitely request a memory read command again for the remaining data transfer. Since the target device discards all remaining data, there is no data to transmit, resulting in a decrease in bus usage and data transmission efficiency.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem, and the bus master provides accurate information on the amount of data transmission to the target device so that it can be prefetched in advance so that the protocol is large or various. Even when this is done, it is possible to prefetch the correct amount of data, thereby improving the data transfer efficiency and the bus usage efficiency.

A method for transferring data in PCI 2.2 to achieve the above object, the method comprising: a bus master using a memory write command to store the address of a memory read command to be requested next and the size of data to be read in a prefetch control register; Prefetching corresponding data from a target device using information stored in the prefetch control register and storing the data in a buffer; The target device relates to a data transmission method using a prefetch request in PCI 2.2, comprising: receiving a read command applied from a bus master and transmitting prefetched data to the bus master.

Hereinafter, a data transmission method using a prefetch request in PCI 2.2 applied to the present invention will be described in detail with reference to the accompanying drawings.

Figure 2ab is a block diagram showing a data transmission process using a prefetch request in PCI 2.2 applied to the present invention, Figure 3ab is a behavior model that operates in clock units using the C language implemented by an embodiment of the present invention 4 is a graph illustrating the number of clocks according to the size of prefetch data implemented by an embodiment of the present invention, and FIG. 5 is a local bus implemented by an embodiment of the present invention. 6 is a graph illustrating a data transmission rate according to a delay, and FIG. 6 is a graph illustrating a data transmission rate according to divided transmission of data implemented by an embodiment of the present invention.

As shown, the bus master 10 stores the address and data size of a memory read command to be requested using a memory write command in the prefetch control register 30, and the target device 20 uses the data to prefetch data. After storing the buffer 40 in the buffer 40, the prefetched data can be transmitted to the bus master 10 when a memory read command is requested from the bus master 10.

The bus master 10 is a program in the input / output controller that directly manages the data flow on the computer bus or the input / output circuit to control the address and control signal flow on the bus circuit.

The target device 20 efficiently uses the prefetch request that informs the target device 20 of the amount of data to be read by the bus master 10 to perform a memory read command in advance using the memory write command. The prefetch control register 30 and the buffer 40 can be configured for transmission.

The prefetch control register 30 is an internal control register for supporting a prefetch request of the bus master 10. The prefetch control register 30 may be requested next by using a memory write command of the bus master 10 to perform a memory read command. The address of the memory read command and the size of data can be stored, which is commonly referred to as a prefetch request.

When the address for prefetch and size information of the data are stored in the prefetch control register 30, the buffer 40 stores the corresponding data from the local device by the target device 20 using the information. To be possible.

As described above, a data transmission method using a prefetch request in PCI 2.2 configured according to an embodiment of the present invention will be described in detail.

As shown in FIG. 2A, the bus master 10 first stores a memory read command address and a size of data to be read in the prefetch control register 30 using a memory write command. This is commonly referred to as a prefetch request. When the address and data size information for prefetch are stored in the prefetch control register 30, the target device 20 uses the same to prefetch the corresponding data from the local device. To be stored in the buffer 40.

When the data is prefetched into the buffer 40 as described above, the bus master 10 requests a memory read command to the target device 20 as shown in FIG. 2B, and at this time, the target device 20 If it fails to prefetch the data to be transmitted, the protocol is terminated by retry termination. If the data to be transmitted is prefetched, the corresponding data is transmitted to the bus master 10.

The data transmission method using prefetch in PCI 2.2 according to the present invention can solve the problem that may occur in the delay transaction mechanism because the target device 10 can know exactly how many data to prefetch. That is, when the target device 20 has less or more data prefetched compared to the data that the bus master 10 intends to read in the delay transaction, if the target device 20 prefetches a large amount of data, the data is transmitted. Although the efficiency may be improved, in this case, a problem arises in that the buffer and local bus efficiency are deteriorated due to the need to always prefetch a large amount of data regardless of how much data the bus master 10 requires.

In addition, when the bus master 10 attempts to read a large amount of data but inevitably terminates the protocol due to a timeout end or a lack of space in the internal buffer of the bus master 10, the method according to the present invention uses the target device 20. ) Waits for the bus master 10 to read back without discarding the remaining data, and if the target device 20 fails to prefetch all the data requested by the bus master 10, the data continues to be prefetched. In this case, since the bus master 10 accurately tells in advance how much data to read, it will always require a memory read command again for the remaining data transfer.

Hereinafter, various embodiments of a data transmission method using a prefetch request in PCI 2.2 configured according to an embodiment of the present invention will be described in detail.

In order to experiment with a data transmission method using a prefetch request in PCI 2.2 according to the present invention, as shown in FIG. 3A, the arbiter, the PCI 2.2 bus master, the PCI 2.2 target device, and the local device are clocked using the C language. Each model is connected to each other using Verilog Simulator PLI (Programming Language Interface).

The entire simulation environment is a test vector written by the user or automatically generated by a random generator, as shown in Figure 3b, which lists instructions for the PCI bus master to perform. For example, to read 84 bytes of data from local memory 300 and send it to 100 PCI target devices, coat mWrite 0x100, 0x300, 84, and read this command from the test vector file. After acquiring, the memory write command is executed. When all memory write commands are executed, the PCI bus master reads the next command from the vector.

Example 1 (Number of Clocks According to Size of Prefetch Data)

4 shows the number of clocks required when the bus master 10 requests data transmission using a memory read multiple command while increasing the size of the transmitted data. When the delay transaction is applied, the target device 20 is measured. Simulates increasing the size of the data to be prefetched from the local device from 16 bytes to 512 bytes, increasing the size of the data to be transmitted from 512 bytes to 4K bytes, and avoiding delays in the local bus and the PCI bus. Make sure no out occurs.

4, the horizontal axis represents the size of data to be transmitted, and the vertical axis represents the number of clocks required until the transfer is completed, and (i) to (iii) are 16 bytes, 32 bytes, 64 bytes, respectively, when a delay transaction is applied. In the case of prefetching data by 128 bytes and 512 bytes, (iii) is a case in which the method according to the present invention is applied, the larger the amount of data, the longer the transmission time, and in the delay transaction, the larger the prefetch size, the shorter the transmission time. It can be seen that, if the prefetch size is 512 bytes or more, the data transfer efficiency is similar to that of the method of the present invention.

Example 2 (Data Transfer Rate According to Local Bus Delay)

Figure 5 shows the data transfer rate according to the local bus delay, the instruction uses a memory read multiple, the size of the data to be transmitted is 4K bytes, prefetch to maximize the data transfer rate when a delay transaction is applied The size of the data to be set is 4K bytes, there is no delay of the PCI bus, and the condition is set so that a timeout does not occur at the bus master.

5 is the local bus delay clock, the vertical axis is the number of clocks required to complete the transmission, (i) is the case where a delay transaction is applied, and (ii) is the case where the method according to the present invention is applied.

In both the method using the delay transaction and the method according to the present invention, it can be seen that the data transmission time increases as the delay of the local bus increases, and the delay transaction and the method according to the present invention are performed until the local bus delay is 0 to 7 clocks. The performance of the method is similar, but if the local bus delay is 8, the transfer time is significantly longer for delayed transactions. This is because the local bus delay causes the target device to send data to the PCI bus master within 8 cycles. Because the transmission fails, the target device must terminate the PCI protocol by disconnection, which causes the current prefetch by the target device to be aborted and all prefetched data must be discarded.

Example 3 (Data Transfer Rate According to Split Transfer of Data)

When the bus master 10 needs to terminate the protocol due to an internal problem or cannot use the bus for a long time and needs to terminate the protocol by the timeout termination, the bus master 10 uses a read multiple instruction to read as many as 4K bytes. Data transmission is required, and when a delay transaction is applied to the target device 20, the size of data to be prefetched is 4K bytes, and a condition is set so that there is no PCI bus delay.

As shown in FIG. 6, the bus master 10 receives up to 32 divided transmissions of data up to 4K bytes at a time without protocol termination in the middle, and the horizontal axis represents the number of times of division transmission by the bus master 10. , The vertical axis represents the number of clocks for which transmission has been completed, (i) represents a case where a delay transaction is applied, and (ii) represents a case where the method according to the present invention is applied.

When all the data is transmitted at once, the two cases have almost the same performance, but the more the number of interruptions in the middle of the transmission method of the present invention, the better the transmission efficiency, the target device to which the delay transaction is applied ( Although 20) prefetches 4K bytes of data, if the bus master terminates the protocol in the middle, the target device 20 must discard all prefetched data. This is because the target device 20 waits for the bus master to request again without discarding the data even if the protocol is terminated in the middle.

In addition, 100 data are randomly selected from 4 bytes to 4K bytes to be transmitted, but local bus delays are randomly selected from 0 to 8, conditions are set such that there is no PCI bus delay, and the bus master 10 targets A memory read command is used to read 4 bytes of data from the device 20, a memory read line command is used to read 16 bytes or less, and a memory read multiple command is used to read more data. When the bus master 10 reads the data, it reads all the data at once without terminating the protocol or randomly selects whether to receive the data up to 32 times. As a result, the method according to the present invention averages more than the delayed transaction. It can be seen that the 10% improvement.

As described above, according to the present invention, the data transfer is efficiently performed by first requesting the target device 20 for a prefetch request that informs the target device 20 of the amount of data to be read using a memory write command. The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawing.

According to the present invention, when the bus master requests a data transfer to a target device with a memory read command in PCI 2.2, the target device has an amount of data to be read using a memory write command to shorten a preparation time of data to be transmitted internally by the target device. By prefetching requests in advance, the target device has time to fully prepare the correct amount of data to transmit, thereby improving the data transfer efficiency and the efficiency of using the PCI bus and the local bus.

Figure 1ab is a block diagram showing a delayed transaction mechanism used in the conventional PCI 2.2

Figure 2ab is a block diagram showing a data transmission process using a prefetch request in PCI 2.2 applied to the present invention

Figure 3ab is a block diagram showing a behavior model operating in clock units using the C language implemented by an embodiment of the present invention

4 is a graph showing the number of clocks according to the size of prefetch data implemented according to an embodiment of the present invention.

Figure 5 is a graph showing the data rate according to the local bus delay implemented by one embodiment of the present invention

6 is a graph illustrating a data transmission rate according to divided transmission of data implemented by an embodiment of the present invention.

* Description of Signs of Main Parts of Drawings *

10. Bus master 20. Target device

30. Prefetch control register 40. Buffer

Claims (1)

In PCI 2.2, how to transfer data, The bus master using a memory write command to store an address of a memory read command to be requested next and a size of data to be read in a prefetch control register; Prefetching corresponding data from a target device using information stored in the prefetch control register and storing the data in a buffer; And receiving, by the target device, a memory read command from a bus master and transmitting the corresponding prefetched data to the bus master. 2.