KR20050088292A - Selectively changeable line width memory - Google Patents

Abstract

The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory (14). The selected line width is used in communicating with one or more processors (12, 26). This provides increased flexibility and efficiency for communicating with the memory. In particular, a register (42) can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block (38) in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache (30, 130), multiple ways (40) of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task (13, 28), a processor, and/or a performance evaluation.

Description

Selectable variable line width memory {SELECTIVELY CHANGEABLE LINE WIDTH MEMORY}

The present invention relates to memory line widths.

Cache is a type of memory used to speed up data transfer between main memory and processing units. In general, a cache contains a smaller amount of data than main memory. Typically, data that has been accessed or intended to be accessed by a processing unit (eg, recently accessed data, neighbor data, data determined by a look ahead algorithm, etc.) is loaded from main memory into one or more data blocks in the cache. If a main memory address is provided to the cache by the processing unit, all or part of the address of that main memory is used to determine whether the requested data is in the cache.

1 shows an example cache 2 structured in a lattice structure of data blocks (cells) 6. Columns are referred to as passages 8, with rows each marked with an index. In the example cache 2, four passages 8, i.e. passages ₁ through _3, and eight columns indexed 0-7 are provided. Therefore, 32 data blocks are shown. Each data block 6 contains one or more word data. "Word" refers to the smallest amount of data that is independently addressable in a processing system. A word is generally one or more bytes (eg, 2 bytes, 4 bytes, etc.). To reduce the burden of overhead in memory, typically a plurality of words are stored in each data block 6. Memory for a single operation is reserved for a plurality of pieces of data stored in each data block 6.

Given the address of the main memory, the cache 2 uses the index to locate the corresponding data block 6 within each passage 8. The cache 2 then determines whether any located data blocks 6 contain data for the provided main memory address. When data exists in one of the located data blocks 6, a predetermined operation (e.g., read, write, delete, etc.) is performed on the data. If no data exists, the requested data is retrieved from the main memory, loaded into one of the located data blocks 6, and then a predetermined operation can be performed.

2 shows a conventional address lookup operation for the cache 2. The cache 2 is shown to contain _N passages 8, that is, passages ₀ through _N-1 . Each passageway 8 comprises 2 ^I data blocks 6 indexed from 0 to 2 ^I −1. Typically, the processor provides the cache 2 with a main memory address 4 for data. To locate the requested data, the cache 2 regards the main memory address 4 as including a tag portion 4A, an index portion 4B, and / or a block offset portion 4C. The relative size of the cache 2 relative to the main memory and the amount of data 6D in each data block 6 determines the size of each address portion 4A-C. For example, a particular main memory may contain 4 mega words (2 ²² words) requiring an address that is 22 bits long. However, each passage 8 in the cache 2 may contain only 1 kilo word (2 ¹⁰ words), which are stored in 256 data blocks of 4 words each. In this case, the block offset portion 4C will contain two bits (to find the position of one of the 4 (2 ² ) words), and the index portion 4B will have eight bits (one of the 256 (2 ⁸ ) data blocks. To find the position of the < RTI ID = 0.0 > and < / RTI > tag portion 4A will contain the remaining 12 bits. The index portion 4B may be located starting from the bits adjacent to the block offset portion 4C in the main memory address 4. The tag portion 4A includes the remaining bits T which are not used in the block offset portion 4C or the index portion 4B in the main memory address 4. Typically, the tag portion 4A includes a bit ("highest order bit") assigned to the value of the highest position in the main memory address 4.

In order to retrieve the data, the cache 2 uses the index portion 4B to locate the rows of the data block 6, i.e., the index portion 4B may use the index lookup ( 5) is used. The cache 2 then compares the tag portion 4A with the tags 6A stored in each data block 6, thereby providing a main memory address 4 provided with one of the data blocks 6 in the located row. It is determined whether to include the data (6D) for. If the correct data exists, the predetermined operation is performed. The block offset portion 4C includes a significant amount of bits B of the main memory address 4, which is required to determine the location of the data within the data 6D. Typically, the block offset portion 4C includes a bit assigned to the value of the lowest position in the main memory address 4 ("lowest bit"). Other information, such as dirty bit 6B, indicating whether data 6D in data block 6 matches data in main memory, and indicating whether data block 6 has valid data. A valid bit 6C may be included in each data block 6.

In order to load the data located at the main memory address 4 into the cache 2, an index portion 4B is used as the index lookup 5 for the row of the data block 6. The data block (s) 6 in one of the passages 8 is selected and the data is loaded into the data block (s) 6. When data is loaded into the data block 6, the tag portion 4A is written to the tag 6A of each data block 6. Then, if a main memory address 4 is provided for retrieval, the index portion 4B is again used as an index lookup 5 to locate the row of data block 6 that may contain that data. . To determine whether the data block 6 contains the requested data, the tag portion 4A is compared with the tag 6A in each located data block 6.

"Line width" is the amount of bits passed to / from memory in a single operation. Typically, the line width for transferring data to / from the cache 2 corresponds to the amount of data 6D in the data block 6 and is fixed. For example, in the above example, each data block 6 comprises four words. Therefore, the line width is 4 words. As a result, each passage 8 is accessed individually while the memory operation is performed.

For a given memory size, the larger the line width, it is advantageous as the less memory operation required to perform the data operation. For example, 16 read operations are required to read 16 words using a line width of 1 word. Using the same operation with a 4-word line width requires only four read operations. However, if a cache is used and the line width corresponds to the size of the data block, the larger the block, the greater the likelihood that data cannot be stored in the cache (ie, a cache miss). Increasing the rate of cache misses degrades performance, causing more frequent transfers between main memory and the cache. In general, when a large line width is used to reduce the number of operations in the cache, there is a single operation that keeps the locality of the code small while performing many data operations. On the other hand, if the locality of the code is more distributed and / or many tasks share one cache, smaller line widths are desirable because additional blocks of data may be stored from unrelated physical addresses. Unfortunately, current technology offers different line widths for a single memory (cache). This problem exists for tasks that benefit from separate line widths, and tasks that benefit from using separate line widths when performing separate functions. In addition, the inability to provide varying line widths for a single cache is problematic when certain processor architectures or legacy program code may need / expect certain line widths to function properly. Can be. This problem is amplified when the processor and / or task share one memory, while requesting / desiring different line widths.

In view of the foregoing, there is a need for a method of selectively changing the line width of a memory.

1 is a prior art cache diagram;

2 is a prior art address lookup operation diagram for a cache;

3 is an exemplary system diagram in accordance with one embodiment of the present invention;

4 is an address lookup operation diagram according to an embodiment of the present invention;

5 is an exemplary partial view of a cache after various operations have been performed;

6 is an address lookup operation diagram for a cache according to another embodiment of the present invention;

The present invention provides for a selective change in line width for memory. The line width is used to communicate with one or more processors. This enhances flexibility and efficiency in communicating with the memory. In particular, the register may store a value indicating the selected line width, where the selected line width is used when managing data in memory. The processor must not be in the register to select the line width. The line width used when communicating with the memory is adjusted according to the register value. In order to allow multiple line widths to be used simultaneously, the selected line widths may be associated with each data block in memory. When implemented in a cache, data blocks in multiple passages of the cache may be treated as a group that provides data using a wider line width while a single memory operation is performed. The line width can vary widely based on processing system, task, processor, and / or performance assessment.

Exemplary aspects of the present invention are designed to solve the problems described herein, and other problems that are not discussed but can be found by those skilled in the art.

  These and other features of the present invention will be more readily understood from the following detailed description of various aspects of the invention taken in conjunction with the accompanying drawings.

It should be noted that the figures of the present invention are not to scale. The drawings are intended only to illustrate typical aspects of the invention and therefore should not be considered as limiting the scope of the invention. In the drawings, like numerals indicate like elements between the figures.

Best Mode for Carrying Out the Invention

The present invention provides for a selective change of the line width for the memory, i.e. selecting one of a plurality of line widths for communicating with the memory. The line width may be selected based on a plurality of parameters including, for example, a processing system in which the memory is installed, a processor accessing the memory, a task using the memory, and / or a performance assessment of the effect of the memory being used. As for the processing system, the line width can be selected when the memory of the present invention is installed in the processing system. This allows the same memory to be manufactured and installed in one of various processing systems using different line widths. As for the task or processor, the line width may be selected based on the loading / unloading of the task, or the start / end of one of several processors accessing the shared memory. When implementing an optional variable line width memory that allows jobs to use different line widths, the selected line width must be associated with each job. The line width is selected when a job is loaded, as is known in the art, and can be stored when the job is unloaded according to other job information (ie, program counters, register information, etc.). The default line width for the processing system may be used if the processor / job did not select a particular line width. The line width can also be changed for the active task. For example, one or more compiler directives may be incorporated to allow software developers to vary line widths for certain portions of a program. For example, the SetCacheWidth # X command can specify the desired line width (X), while the EndCacheWidth command can return the selected line width to its previous or default size. This allows a software developer to specify a large line width, for example, when a portion of a task that is to deliver a significant amount of data is entered, thus benefiting from the large line width. With regard to performance assessment, an operating system running one or more tasks on the processor may detect inefficient memory performance and change the line width of active and / or other tasks. For example, the operating system may monitor the cache hit / miss ratio and determine that the ratio is too high. In response, the operating system may instruct to select a different line width for all or some of the tasks using the cache.

Returning to the drawings, FIG. 3 shows an exemplary processing system 10 implementing various aspects of the present invention. Processing system 10 includes a processor 12 and a memory 14. In general, the processor 12 performs memory operations such as reading, writing, and deleting of data stored in the memory 14. To perform the desired operation, processor 12 uses address line (s) 16 to provide an address to memory 14. Data is transferred using data line 18 between processor 12 and memory 14. The processor 12 may deliver the desired operation using all or part of the data line 18 or by one or more operation lines not shown.

If implemented as a cache, the memory 14 stores some of the data stored in the main memory 20. In operation, main memory 20 includes one or more memory blocks 13 reserved for one or more tasks to be performed by processor 12. The processor 12 provides an address for the data stored in the main memory 20. The memory 14 first determines whether to include a copy of the data based on the main memory 20 address. If the requested data exists, the desired operation is performed on the data in memory 14. If the requested data does not exist in the memory 14, the memory 14 obtains data from the main memory 20 before performing the operation. The memory 14 writes the modified data back to the main memory 20 before erasing and / or swapping out with other data.

The memory 14 may communicate with the processor 12 using a line width that may be selectively changed with respect to the data line 18. In order to implement a variable variable line width, memory 14 is shown to include a width unit 22 and an address unit 24. The width unit 22 stores, for example, the line width to be selected by the processor 12 for the data line 18. The address unit 24 generates a lookup based on the provided main memory and the selected line, as described below. Although the width unit 22 and the address unit 24 are included in the memory 14, the functions of the units 22 and 24 may be software (eg, executed in the processor 12), hardware, or software and hardware. It is understood that the combination of can be implemented within and / or separately from the memory 14. Further, one or more additional processors, i.e., the processor 26, perform one or more tasks, and one or more memory blocks to communicate with, and perform operations on, the memory 14 and / or main memory 20. (28) can be reserved.

4 illustrates an address lookup operation for cache 30 in accordance with one embodiment of the present invention that enables the line width to be selectively changed. When the selected line width is a plurality of pieces of data 38D in the data block 38, the data blocks 38 located in the plurality of passages 40 are managed as a group. Further, the size and / or position of the block offset portion 36C, the index portion 36B, and / or the tag portion 36A is variable depending on the selected line width.

In order to implement the selection of the line width, the cache 30 is shown as including a width unit 32. The width unit 32 includes a width register 42 set by the processor / task to select the desired line width. The cache 30 uses the width unit 32 to determine the line width. Based on the selected line width, cache 30 manages data blocks 38 in one or more passages 40 as a single data block of variable size. For example, if the width register 42 indicates the line width of 2 ^{B + 1} words (two data blocks), then the data blocks located at index _{0 in} passage ₀ and passage ₁ are twice as large as single data. It is managed as a block.

   One point to note is that if the line width changes, all of the data in the cache 30 may be because one or more data blocks do not contain the correct data and / or because the data may be located in other data blocks. Or some become inaccessible and / or invalid. For example, when the line width is changed from 1 to 2 data blocks, the data previously written as a single data block cannot be retrieved as two data blocks because the data blocks of the second passage have not been written. Similarly, when the line width is changed from 2 data blocks to 1 data block, the second data block with data is located at another index. As a result, when a new line width is selected, all or part of the data in the cache 30 may need to be invalidated.

In order to prevent all data from being invalidated, the selected line width is associated with each data block 38 so that it can later be determined at which line width the data block 38 was written. This allows multiple processors / tasks to simultaneously use the cache 30 without having to invalidate the data in the cache 30 whenever there is a line width change. In one embodiment, the selected line width (eg, the value of the width register 42) is associated with the data block 38 by storing that value as the size 38E in the data block 38. Alternatively, the value of the width register 42 may be mapped to a different value corresponding to each of the possible line widths stored in the size 38E, in order to associate the selected line width with the data block 38. Based on the value of size 38E, whether the data block 38 has been written with the current line width, and if the tag portion 36A matches the tag 38A stored in the data block 38, the current It can be determined whether line width can be used. If a plurality of data blocks 38 are managed as a group, the overhead for each data block (ie, tag 38A, dirty bit 38B, valid bit 38C) is only the first data block 38. ), Since the overhead for additional data block 38 will only be a copy of the first data block 38. However, the size 38E is written for all data blocks 38 in the group so that subsequent accesses using separate line width sizes can recognize that data block as old and / or invalid. Alternatively, all or part of the information may continue to be written to each data block 38. For example, when data 38D in fewer data blocks than all of data blocks 38 is changed, dirty bits 38B are updated separately for each data block 38 and copied into main memory. It is possible to limit the amount of data 38D.

The cache 30 also includes an address unit 34 that generates a lookup 37 based on the index portion 36B to locate the data block 38. The address unit 34 changes the index portion 36B based on the selected line width such that when the line width changes for the task / processor, the data of all or part of the data block 38 remains valid. To select the line width, an appropriate mask is written to the width register 42. The width register 42 includes the number E of bits corresponding to the maximum number of masked (set to zero) index portion 36B bits when the maximum line width (ie, the maximum number of data blocks) is selected. do. In other words, for a cache with N paths, the width register 42 will contain up to log ₂ (N) bits (E). The address unit 34 includes a logical AND gate 44. AND gate 44 is used to combine the least significant E bits of index portion 36B with the contents of width register 42. The result is then combined with the rest of the index portion 36B to produce a lookup 37. The lookup 37 is then used to locate the data block 38 in the passage 40 which may contain data for the main memory address 36.

The example table below provides the value of the width register 42 when up to eight data blocks can be selected. As can be seen in row 1, when the line width is selected with one data block, all I bits of the index portion 36B are used so that each data block can be accessed individually. Each time the line width is doubled, starting with the lowest index bit, the index bits are further masked. Consequently, in row 2, lookup 37 accesses the indexed data block every two times, and in row 3, the indexed data block is accessed every four times. If the line width is selected with the eight data blocks (last row), the least significant three bits of the index portion 36B are masked, resulting in every eighth block being accessed. Masked index bit (s) (rows 2 through 4) are needed to determine which data block 38 in the group contains the desired data in the data 38D. As a result, the masked bits of the index portion 36B may be considered as part of the block offset portion 36C (ie, the size of the block offset portion 36C increases by the number of masked bits).

Considering FIG. 5 in conjunction with FIG. 4, an exemplary portion of cache 30 is shown after each of the four operations A through D has been performed. The example portion includes three passages 40 (paths ₀ through ₃ ), each passage having eight data blocks 38 (shown in cells in FIG. 5) indexed 0-7. The cache 30 is shown first, after the operation A has been performed. Since task A uses one data block 38 as the line width (ie each passage is managed independently), the width registers 42 are all set to 1, so that all of the index portion 36B Allows the I bits to be used to generate a lookup 37 for locating the data block 38. As a result, task A may write data to any data block 38 located within any passage 40.

Task B uses four data blocks (four passages) as the line width. Thus, each time task B reads data from cache 30, data 38D of all data blocks at a given index is passed (i.e., passages ₀ through ₃ ). Further, since task B communicates with cache 30 using four data blocks 38 in line width, the least significant two bits of width register 42 are set to zero as described above. As a result, when generating the lookup 37 for the task B so that the line widths can be varied without invalidating all data in the cache 30 for the task B, the address unit 34 Sets the least significant two bits of the index portion 38B to zero. Therefore, task B is limited to writing data to data block 38 at indexes 0 and 4 of the cache 30 portion as shown.

Task C uses two data blocks 38 (two passages) as the line width. As a result, when the least significant bit of the width register 42 is set to zero to generate a lookup 37 for task C, the address unit 34 can set the least significant bit of the index portion 38B to zero. do. After task C is executed, a portion of one of the entries of task B is replaced (i.e., data block 0 of passage ₀ and passage ₁ ). As a result, the rest of job B becomes invalid and can no longer be accessed by job B.

After job C is executed, the data block 38 for jobs A, B, and C still remains valid because the data block was not replaced for another job, and is unique to each job by each job. It can be accessed using the line width of. Similarly, after operation D, which makes one data block 38 line width, is executed, a significant amount of data blocks 38 used by operations A and C still survive. However, only one data block 38 used by task B remains valid because the data at index 0 for task B has been replaced. In addition, in the data block 38 of the index 3, the data of the work A, once the work D overwrites the data for the work A in the passage ₀ of the index 3, It is invalidated for all passages. Cache 30 illustrates the tradeoffs obtained between small line widths (more hits) versus large line widths (less actions). Furthermore, as shown, the cache 30 has the ability to simultaneously store data for multiple jobs including different line widths, thereby enhancing the efficiency of using the cache 30.

If the line width for the active task can vary, then the data block 38 containing the data for the active task can be invalidated as described above. To ensure efficient transition between line widths, cache 30 can be run in a "store through" mode. In the save through mode, the cache 30 writes any modified data to the main memory without waiting for work replacement or data to be replaced. This allows the data block 38 to be marked as invalid before this occurs, potentially without requiring a significant amount of writes to the main memory. Further, when the index portion 36B is masked based on the line width, when the line width of the task varies in various ways, the data portion of the passage 40 still remains valid. The parts of the job's data are stored in the same location for different line widths. For example, in FIG. 5, after the operation B is executed, if the line width of the operation B is changed to two data blocks (two passages), the data at the indices 0 and 4 of the passage ₀ and the passage ₁ is changed. The task B data of block 38 is valid and will remain available. As a result, this data will need to be loaded from main memory and not need to be marked invalid.

4, instead of masking the bits of the index portion 36B, the address unit 34 may provide the index portion 36B as a lookup 37 to locate the data block 38. . This may be desirable if the width register 42 varies variously based on processors using different sized addressable words. For example, a processor with a one byte word may use a line width of one data block 38 and a processor and cache 30 using a line width of a two data block 38 while having a two byte word. Can share In this configuration, a one byte addressable processor has N data hit possibilities (one probability per path 40), while a two byte addressable processor has N / 2 data hit possibilities (a pair of paths). Per 40, will have 1 possibility).

It is understood that the tag 38A may include a copy of the tag portion 36A, or any data having the ability to match a designated main memory address 36 with data stored in one or more data blocks 38. . Furthermore, it is understood that the main memory address 36 may include all or a portion of the portions 36A-C shown. For example, if each data block 38 is one word in size, the block offset portion 36C is zero bits (ie not included). In addition, the position of index portion 36B, and block offset 36C within main memory address 36 may be reordered in accordance with how data is stored / accessed in cache 30.

6 illustrates an alternative cache 130 in accordance with another embodiment of the present invention. The cache 130 grants access to all data blocks 38, regardless of the size of the selected line width. As a result, jobs / processors using larger line widths will have access to all data blocks 38 in all caches 130, rather than a limited number of data blocks 38, as discussed in connection with FIG. Can be. In cache 130, index portion 36B is located in main memory address 36 based on the selected line width. The width unit 32 includes a width register 42 that operates in the same manner as described above with respect to FIG. 4. The address unit 134 is compared with the tag 38A in the data block 38, and the position of the data block 38 and the logical AND gate 44 that generates the tag 139 stored as the tag 38A. A shift circuit 146 that generates a lookup 137 to find out.

Depending on the value of the width register 42, all I bits of the index portion 36B and the least significant E bits of the tag portion 36A are provided to the shift circuit 146. According to the width of the width register 42, the provided bits are shifted to the right by zero or more bits. For example, the combination of the index portion 36B bits and the least significant E bits of the tag portion 36A may be shifted by one bit to the right for each bit of the width register 42 having a zero value (masked). Once shifted, the remaining least significant I bits are used as lookup 137 to locate the data block 38. As a result, lookup 137 will always contain unmasked I bits, so all indexes for data block 38 are accessible. Any right shifted bit may be used subsequently as part of block offset portion 36C, as described above.

The least significant E bit of the tag portion 36A is also provided to the AND gate 44 to be masked using the width register 42. Next, the masked bits are combined with the remaining bits of tag portion 36A to generate tag 139. Tag 139 is compared to tag 38A and / or copied to tag 38A. This shifts to the right, causing the least significant bit of the tag portion 36A used in the lookup 137 to be zero before being used as part of the tag. As a result, when the main memory address 36 is provided, the bit is not used twice, i. E. Once as part of the lookup 137 and next as part of the tag 139.

It is understood that various alternatives are possible for the two embodiments. For example, address unit 134 and / or width unit 32 shown in FIG. 6 may include software and / or circuitry to switch operations between the various embodiments discussed. For example, the width unit 32 may include a register for selecting a word size. The operation of the address unit 134 can be changed based on this selection and the value of the width register 42. The selected word size may also be associated with each data block 38 in a manner similar to size 38E (ie, stored in each data block 38). By incorporating this functionality, tasks running on processors with different addressable word sizes can be selected for varying line widths. Furthermore, it is understood that masking the main memory address 36 bits is not required. For example, an address lookup operation can ignore unnecessary bits.

In this specification, a computer program, software program, program, or software means any representation of a set of instructions in any language, code, or notation, wherein the instructions are either directly or after one of the following, or It is intended to result in a system having an information processing capability that performs both specific functions: (a) conversion to another language, code, or notation, and / or (b) reproduction in other material forms. . Various aspects described above with respect to the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and it is obvious that many variations and modifications are possible. It is apparent to those skilled in the art that such modifications and variations are intended to be included within the scope of the invention as defined by the appended claims.

The present invention is useful for accessing a memory such as a cache within a processing system.

Claims (20)

In the cache (30, 130), Means (38, 40) for storing data; And Means (32) for selectively changing a line width for the cache Cache containing. The method of claim 1, Means (12, 26) for communicating with the cache (30, 130) using the line width Cache containing more. The method of claim 1, Means 18 for transferring data 38D from a plurality of data blocks 38 in the cache 30, 130 while performing a data operation. Cache containing more. The method of claim 1, wherein the line width, A cache selected based on at least one of a processor (12, 26), a task (13, 28), and a performance assessment. The method of claim 1, Means for associating the line width with a data block 38 Cache containing more. The method of claim 1, Means (34, 134) for masking a portion of main memory address 36 based on the selected line width Cache containing more. In the method of managing the memory to communicate using the line width, Selectively changing the line width; And Delivering data in a memory operation, the amount of data being delivered based on the selected line width Memory management method comprising a. The method of claim 7, wherein the line width is, A memory management method selected based on at least one of a processor (12, 26), a task (13, 28), and a performance assessment. The method of claim 7, wherein the data transfer step, Providing a main memory address (36) to the memory (30, 130); Generating a lookup (37, 137) based on the main memory address and the line width; And Transferring data (38D) from at least one data block (38) located within the memory using the main memory address and the lookup. The method of claim 7, wherein Associating the line width with the data Memory management method further comprising. 11. The memory device of claim 10, wherein the memory (30, 130) comprises a first data block (38) associated with a first line width, and a second data block associated with a second line width that is different from the first line width. Including memory management method. The method of claim 7, wherein Associating line widths with operations 13 and 28; When loading the job, selecting the line width; And When unloading the job, storing the line width Memory management method further comprising. The method of claim 7, wherein Varying line width for active operation Memory management method further comprising. In the processing system 10, A memory 14, 30, 130 comprising a plurality of data blocks 38; A processor (12, 26) in communication with the memory; And Width units 22, 32 that store the line widths selected by the processor. Wherein the amount of data transferred from the data block (38D) is based on the line width while a memory operation is performed. The method of claim 14, Main memory (20) Further comprising, the memory (14) comprising data copied from the main memory. The method of claim 14, Address units 24, 34 and 134 for generating lookups 37 and 137 for locating at least one data block 38 in the memory 14-the lookup is the line width and main memory address Based on index portion 36B of (36)- Processing system comprising more. The method of claim 16, wherein the address unit (24, 34, 134), And a tag (139) for matching a data block (38) with said main memory address (36), said tag based on said line width and said memory address. The method of claim 17, wherein the index portion 36B is Located within the main memory address (36) based on the line width, wherein the tag portion (36A) is masked based on the line width to generate the tag (139). The method of claim 14, Means for varying the line width of the active operation 13, 28 Processing system comprising more. The method of claim 14, Means for associating the line width with at least one of operations 13, 28 and processor 12, 26. Processing system comprising more.