KR20050086073A - Display pannel with noise reduction - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device having a power supply noise preventing means capable of preventing noise of the power supply voltage on a power supply voltage line of the display device.

In accordance with an aspect of the present invention, there is provided a noise preventing means including a capacitor connected to the power supply voltage line and the cathode voltage line. An insulating substrate including a cathode voltage line region; A semiconductor pattern; A gate insulating film formed on the insulating substrate including the semiconductor pattern; Gate metal; An interlayer insulating film having a first contact hole and a second contact hole exposing the gate; A first source / drain metal contacted with the semiconductor pattern through the first contact hole of the interlayer insulating film and formed on the interlayer insulating film of the power voltage line region; And a second source / drain metal formed on the interlayer insulating layer of the cathode voltage line region, wherein the capacitor includes a first capacitor formed by overlapping the gate metal and the semiconductor pattern, and the gate metal and the first source / drain metal. It is characterized in that the second capacitor formed by overlapping.

Description

Display pannel with noise reduction

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device for reducing noise of a power source capable of preventing noise in a power line of a display device.

In recent years, with the spread of portable information terminals (PDAs) including mobile phones and notebook personal computers, display devices such as liquid crystal display (LCD) and electro luminescence (EL) have been used as display devices with small power consumption. . Among such display means, in an organic EL display device or a liquid crystal display device using an organic EL element as a light emitting source, a plurality of pixels in a panel are arranged and drive-controlled so that each pixel is turned on or off to display a predetermined image.

In general, an organic light emitting display device supplies a power supply voltage and a cathode voltage to the panel as driving power of the pixel, and a DC-DC converter is used to supply the driving power. The DC-DC converter boosts or depressurizes a low voltage of 2.8 to 3.3V to + 5V to -6V and outputs it to the display panel.

1 is a block diagram illustrating a conventional organic light emitting display device.

The control unit 40 outputs an image control signal, the DC-DC converter 50 outputs a power supply voltage and a cathode voltage under the control of the control unit 40, and the connection means 40 is connected to the control unit 40. The control signal is transmitted to the scan driver 30 and the data driver 10, and the output voltage of the DC-DC converter 50 is transmitted to the power supply voltage line 21 and the cathode voltage line 22, respectively. In addition, the scan driver 30 outputs a selection signal, the data driver 10 outputs a data signal, and the display panel 20 includes a plurality of unit pixels 23 to display a predetermined image. The unit pixel 23 emits a predetermined color corresponding to the selection signal and the data signal output from the scan driver 30 and the data driver 10. The unit pixel 23 is connected to the power supply voltage line 21 and the cathode voltage line 22, respectively.

When the driving control signal is applied from the controller 40, the DC-DC converter 50 applies the power supply voltage and the cathode voltage to the power supply voltage line 21 and the cathode voltage line 22. In addition, the controller 40 applies the pixel data signal and the driving signal to the data driver 10 and the scan driver 30 through the connection means 40.

Therefore, the scan driver 30 outputs a selection signal to each unit pixel 23 of the display panel 20, and the data driver 10 transmits a data signal to each unit pixel 23, and to each unit pixel. The corresponding voltage is applied through the power supply voltage line 21 and the cathode voltage line 22. Therefore, since each unit pixel 23 of the display panel 20 emits light with an intensity corresponding to the data signal, the entire display panel 20 displays a predetermined image.

In such a conventional display device, the power supply voltage line and the cathode voltage line which transmit the power supply voltage and the cathode voltage to the display panel are very vulnerable to noise caused by voltage drop and other signals due to the large current flow. If such noise is inserted into the panel, even small noise directly affects the display quality of the panel, thereby degrading the image quality of the image displayed on the display panel.

Accordingly, the present invention, which is intended to solve the above problems, is to display the power source line and the cathode voltage line, the gate metal and the source / drain metal overlapping the display panel to form a noise prevention means by reducing the noise of the power source It is an object to provide a device.

According to an aspect of the present invention, a display panel includes a plurality of unit pixels for implementing a predetermined color, a power supply voltage line for transmitting a power supply voltage, and a cathode voltage line for delivering a cathode voltage. The display panel includes a capacitor connected to the power voltage line and the cathode voltage line to prevent noise of the power line.

Here, the noise preventing means includes an insulating substrate including a power supply voltage line region and a cathode voltage line region; A semiconductor pattern formed on the power supply voltage line region and the cathode voltage line region of the insulating substrate; A gate insulating film formed on the insulating substrate including the semiconductor pattern; A gate metal formed on the gate insulating film; An interlayer insulating film formed on the gate insulating film including the gate metal and having a first contact hole exposing the semiconductor pattern and a second contact hole exposing the gate; A first source / drain metal contacted with the semiconductor pattern through the first contact hole of the interlayer insulating film and formed on the interlayer insulating film of the power voltage line region; And a second source / drain metal contacted to the gate metal through the second contact hole of the interlayer insulating film and formed on the interlayer insulating film of the cathode voltage line region, wherein the capacitor is formed by overlapping the gate metal and the semiconductor pattern. The first capacitor is formed, and the second capacitor is formed by overlapping the gate metal and the first source / drain metal.

In addition, the noise preventing means includes an insulating substrate including a power supply voltage line region and a cathode voltage line region; A semiconductor pattern formed on the power supply voltage line region and the cathode voltage line region of the insulating substrate; A gate insulating film formed on the insulating substrate including the semiconductor pattern; A gate metal formed on the gate insulating film; An interlayer insulating film formed on the gate insulating film and having a first contact hole exposing the semiconductor pattern and a second contact hole exposing the gate metal; A first source / drain metal contacted with the semiconductor pattern through the first contact hole, contacted with the semiconductor pattern through the first contact hole of the interlayer insulating film, and formed on the interlayer insulating film of the power supply voltage line region; And a second source / drain metal contacted to the gate metal through the second contact hole and formed on the interlayer insulating layer of the cathode voltage line region, wherein the capacitor is formed by overlapping the gate metal and the semiconductor pattern. Characterized in that.

Here, the gate metal is formed in a range that does not overlap with the first source / drain metal.

In addition, the noise preventing means includes an insulating substrate including a power supply voltage line region and a cathode voltage line region; A semiconductor pattern formed on the power supply voltage line region and the cathode voltage line region of the insulating substrate; A gate insulating film formed on the insulating substrate including the semiconductor pattern; A first gate metal formed on the gate insulating film in the power supply voltage line region; A second gate metal formed on the gate insulating layer in the cathode voltage line region; A first contact hole formed on the gate insulating layer and exposing the first gate metal in the power supply voltage line region, a second contact hole exposing the semiconductor pattern in the power supply voltage line region and the second gate; An interlayer insulating film having a third contact hole exposing a metal; A first source / drain metal contacted with the first gate metal through the first contact hole, contacted with the semiconductor pattern through the second contact hole, and formed on the interlayer insulating film of the power voltage line region; And a second source / drain metal contacted with the gate metal through the third contact hole and formed on the interlayer insulating layer of the cathode voltage line region, wherein the capacitor is formed by overlapping the gate metal and the semiconductor pattern. It is characterized by.

The second gate metal may be formed in a range that does not overlap the first source / drain metal.

In addition, the first gate metal may be overlapped with the first source / drain metal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view illustrating an organic light emitting display device according to the present invention, and FIG. 3 is an equivalent circuit diagram of an organic light emitting display device according to an embodiment of the present invention.

2 and 3, the power supply voltage input terminal 171 (see FIG. 3) and the cathode voltage input terminal 172 (see FIG. 3) receive power from a DC-DC converter, and the upper power supply voltage line 110. And the lower power supply voltage line 120 transmits a power supply voltage input from the power supply voltage input terminal 171, and the pixel area 160 includes a plurality of unit pixels 161 to implement a predetermined image, and a scan driver 140 transmits the selection signal to the unit pixel 161 of the pixel region 160, the data driver 150 transmits the data signal to the pixel region 160, and the cathode voltage line 130 The cathode voltage input from the cathode voltage input terminal 172 is applied to the pixel region 160. The noise preventing means 190 is connected to the power supply voltage line 110 and the cathode voltage line 130 and included in the display panel. In this case, the noise preventing means 190 is preferably a capacitor.

When the power supply voltage ELVDD and the cathode voltage ELVSS are transmitted to the power supply voltage lines 110 and 120 and the cathode voltage line 130 through the power supply voltage input terminal 171 and the cathode voltage input terminal 172, the power supply voltage, respectively. And a cathode voltage is applied to the unit pixel 161.

In addition, the noise preventing means 190 connected to the power supply voltage lines 110 and 120 and the cathode voltage line 130 in a predetermined region where the power supply voltage lines 110 and 120 and the cathode voltage line 130 are formed. Is connected to the power supply voltage lines 110 and 120 and the cathode voltage line 130 to prevent noise of the power supply through each of the lines 110, 120 and 130.

In addition, the unit pixel 161 emits light of a predetermined color by transmitting a selection signal from the scan driver 140 and a data signal from the data driver 150.

4 is a cross-sectional view illustrating a power line of a display device according to a first exemplary embodiment of the present invention.

Referring to FIG. 4, a transparent or translucent insulating substrate 188 such as a glass substrate is provided, and the insulating substrate 188 is formed of the power supply voltage lines 110 and 120 and the cathode voltage line 130 in a subsequent process. It has an area | region which becomes.

A buffer layer 187 such as an oxide film is formed on the insulating substrate 188, and a conductive film such as a poly-Si layer is formed on the buffer layer 187 and then patterned to form a semiconductor pattern 186. ) Is formed at the same time as forming a semiconductor layer (not shown) of the thin film transistors constituting each unit pixel.

In addition, a gate insulating film 185 formed of a silicon oxide film SiO2 or a silicon nitride film SiNx is deposited on the buffer layer 187 including the semiconductor pattern 186, and a gate electrode material is deposited on the gate insulating film 185. And patterning the gate metal 184 to form a gate electrode (not shown) of the thin film transistor so as to overlap the semiconductor pattern 186. An interlayer insulating layer 183 formed of a silicon oxide layer SiO 2 or a silicon nitride layer SiNx is formed on the gate insulating layer 185 including the gate metal 184.

In addition, in order to form contact holes 189a and 189b on the interlayer insulating film 183, a photoresist is deposited on the interlayer insulating film 183, and an exposure process, a developing process, and an etching process are performed in sequence to form the interlayer insulating film ( First and second contact holes 189a and 189b exposing the semiconductor pattern 186 and the gate metal 184 are formed in 183. At this time, a contact hole (not shown) for exposing the semiconductor layer of the thin film transistor is also formed at the same time.

The semiconductor pattern 186 is formed through the first contact hole 189a by depositing and patterning a source / drain electrode material on the interlayer insulating layer 183 including the first and second contact holes 189a and 189b. A first source / drain metal 181 in contact with the second metal may be formed and a second source / drain metal 182 in contact with the gate metal 184 through the second contact hole 189b. Although not shown in the drawing, a source / drain electrode is formed to be connected to the semiconductor layer of the thin film transistor through a contact hole.

Therefore, the first source / drain metal 181 and the gate metal 184 overlap, and the gate metal is connected to the second source / drain metal 182 so that the first source / drain metal 181 and the second source / drain metal 181 overlap. The drain metal 182 is a first capacitor 191 serving as an electrode.

That is, a general capacitor includes a dielectric formed of a silicon oxide film (SiO 2) or a silicon nitride film (SiN x) between the positive electrode and the positive electrode. In the present invention, the first source / drain metal 181 and the gate metal 184 overlap each other. And the second source / drain metal 182 is connected through the second contact hole 189b so that the first and second source / drain metals 181 and 182 are connected to the electrode of the first capacitor 191. The interlayer insulating film 183 formed of the silicon oxide film or the silicon nitride film corresponds to a dielectric to form the first capacitor 191.

In addition, the semiconductor pattern 186 overlaps the gate metal 184, the semiconductor pattern 186 is connected to the first sword / drain metal 181, and the gate metal 184 is the second source / drain. As connected to the metal 182, a second capacitor 192 is formed in which the first source / drain metal 181 and the second source / drain metal 182 become electrodes.

That is, the second capacitor 192 has a gate insulating film formed of a silicon oxide film (SiO 2) or a silicon nitride film (SiN x), wherein the first source / drain metal 181 and the second source / drain metal 182 are electrodes. 185 corresponds to the dielectric.

Therefore, in the first exemplary embodiment of the present invention, the semiconductor pattern 186 and the gate metal 184, the first source / drain metal 181, and the gate metal 184 overlap each other to form first and second capacitors 191 and 192. By forming the noise prevention means 190 to prevent noise of the voltage applied to the power line (110, 120, 130).

5 is a cross-sectional view illustrating a power line of a display device according to a second exemplary embodiment of the present invention.

Referring to FIG. 5, an insulating substrate 188 including a region where power supply voltage lines 110 and 120 and a cathode voltage line 130 are formed, and a buffer layer 187 such as an oxide film on the insulating substrate 188 are formed. The semiconductor pattern 186 is formed of polysilicon ion-doped on the buffer layer 187.

In addition, a gate insulating film 185 formed of a silicon oxide film (SiO 2) or a silicon nitride film (SiN x) is deposited on the buffer layer 187 including the semiconductor pattern 186, and on the gate insulating film 185, the semiconductor pattern ( An interlayer insulating film 183 formed of a silicon oxide film (SiO 2) or a silicon nitride film (SiN x) on the gate metal 184 formed to overlap the 186 and the gate insulating film 185 including the gate metal 184. To form. First and second contact holes 189c and 189d may be formed on the interlayer insulating layer 183 to contact the semiconductor pattern 186 and the gate metal 184, respectively.

The first source / drain metal 181 contacts the semiconductor pattern 186 through the first contact hole 189c, and the gate metal 184 contacts the second contact hole 189d. A second source / drain metal 182 is formed.

Accordingly, the semiconductor pattern 186 and the gate metal 184 overlap each other, and the semiconductor pattern 186 has a first contact hole 189c in the first source / drain metal 181 of the power supply voltage lines 110 and 120. And the gate metal 184 is connected to the second source / drain metal 182 of the cathode voltage line 130 so that the gate metal 184 is connected between the semiconductor pattern 186 and the gate metal 184. A capacitor 193 having the second source / drain metal 181 and 182 as an electrode is formed to constitute the noise preventing means 190.

 In addition, in the second embodiment of the present invention, the gate 184 does not overlap with the first source / drain metal 181 to prevent a short between the source / drain metal 181 and the gate metal 184. It is preferable to form in a range.

In addition, even if a short occurs due to damage of the gate insulating layer 185, the semiconductor pattern 186 is formed of polysilicon (Poly-Si), and the gate metal 184 is formed of the first source / drain metal 181. In this case, the current flowing through the gate metal 184 does not flow directly to the first source / drain metal 181 but flows through the semiconductor pattern 186. However, since the semiconductor pattern 186 has a large resistance, the leakage current through the semiconductor pattern 186 is not large.

6 is a cross-sectional view of a third exemplary embodiment of a display device in which noise of a power source according to the present invention is reduced.

Referring to FIG. 6, as described in the above-described first and second embodiments, the insulating substrate 188, the buffer layer 187, and the semiconductor pattern 186 are formed, and the buffer layer (including the semiconductor pattern 186) is formed. A gate insulating film 185 is formed on 187. Further, a gate metal 184 is formed on the semiconductor pattern 186 by depositing and patterning a gate electrode material on the gate insulating layer 185. The semiconductor pattern 186 is formed of polysilicon.

The gate metal 184 may include a first gate metal 184a overlapping the first source / drain metal 181 in the power voltage line regions 110 and 120, and the gate metal 184 in the cathode voltage line region 130. The second gate metal 184b overlaps the second source / drain metal 182.

In addition, an interlayer insulating film 183 is formed on the gate insulating film 185 including the first and second gate metals 184a and 184b, and the interlayer insulating film 183 contacts the first gate metal 184a. And a first contact hole 189e, a second contact hole 189f contacting the semiconductor pattern 186, and a third contact hole 189g contacting the second gate metal 184b.

A source / drain electrode material is deposited on the interlayer insulating layer 183 including the first to third contact holes 189e, 189f, and 189g and then patterned to form the first contact hole 189e and the second contact hole ( A first source / drain metal 181 contacting the first gate metal 184a and the semiconductor pattern 186 through 189f, and the second gate metal 184b through the third contact hole 189g, respectively. And form a second source / drain metal 182 in contact with it. The first source / drain metal 181 is formed in the power supply voltage line regions 110 and 120, and the second source / drain metal 182 is formed in the cathode voltage line region 130.

In addition, a second of the semiconductor pattern 186 and the cathode voltage line region 130 connected through the first source / drain metal 181 and the second contact hole 189f of the power supply voltage line regions 110 and 120. Since the second gate metal 184b connected to the source / drain metal 182 overlaps to form a capacitor 194 to constitute the noise preventing means 190, the power voltage lines 110 and 120 and the cathode voltage line ( Noise in the voltage delivered through 130 is prevented.

In the third embodiment of the present invention as described above, as the first gate metal 184a and the second gate metal 184b are formed, the resistance is smaller than the power line including the gate metal composed of one voltage drop (IR Drop). Is less. In addition, since the second gate metal 184b is configured in a range not overlapping with the first source / drain metal 181 in the cathode voltage line region 130, a short may be generated when the interlayer insulating film 183 is damaged. Prevent (Short)

In addition, when a short occurs due to damage of the gate insulating layer 185, the semiconductor pattern 186 is formed of polysilicon as a resistance, so that an excessive leakage current due to a short flows much less than a short between metals. When the semiconductor pattern 186 is formed, the pattern may be divided into several independent parts, and when a short occurs due to damage to the gate insulating layer, only the short generation part may be cut off, so that only a portion of the capacitor may not be formed.

The detailed description of the invention has been described with reference to specific embodiments of the invention as examples, but the invention is not limited thereto, and one having ordinary skill in the art to which the invention pertains without departing from the concept of the invention. Modification or modification of the invention in various forms by the ruler is of course included in the concept of the present invention.

As described above, the present invention reduces the capacitance of the capacitor configured at the output terminal of the DC-DC converter by forming noise preventing means in the power supply voltage line and the cathode voltage line region, so that a small capacitor can be used. Since the incoming noise is directly removed from the inside of the panel, the image quality of the display device is improved.

1 is a block diagram showing a conventional display device;

2 is a plan view of a display device according to an exemplary embodiment of the present invention;

3 is an equivalent circuit diagram of a display device for reducing noise of a power supply according to an exemplary embodiment of the present invention;

4 is a cross-sectional view of a display device for reducing noise of a power supply according to a first embodiment of the present invention;

5 is a cross-sectional view of a display device for reducing noise of a power supply according to a second embodiment of the present invention;

6 is a cross-sectional view of a display device to reduce noise of a power supply according to a third exemplary embodiment of the present invention.

Explanation of symbols on main parts of drawing

110: power supply voltage line 140: cathode voltage line

181: first source / drain metal 182: second source / drain metal

183: interlayer insulating film 184: gate

185: gate insulating film 186: semiconductor pattern

187: buffer 188: insulating substrate

189 contact hole 191 capacitor

Claims (7)

A display panel comprising a plurality of unit pixels for implementing a predetermined color, a power supply voltage line for transmitting a power supply voltage, and a cathode voltage line for delivering a cathode voltage, wherein the display panel includes: And a noise preventing means having a capacitor connected to the power supply voltage line and the cathode voltage line to prevent noise of the power supply line. The method of claim 1, wherein the noise preventing means An insulating substrate including a power supply voltage line region and a cathode voltage line region; A semiconductor pattern formed on the power supply voltage line region and the cathode voltage line region of the insulating substrate; A gate insulating film formed on the insulating substrate including the semiconductor pattern;  A gate metal formed on the gate insulating film; An interlayer insulating film formed on the gate insulating film including the gate metal and having a first contact hole exposing the semiconductor pattern and a second contact hole exposing the gate; A first source / drain metal contacted with the semiconductor pattern through the first contact hole of the interlayer insulating film and formed on the interlayer insulating film of the power voltage line region; A second source / drain metal contacted to the gate metal through the second contact hole of the interlayer insulating film and formed on the interlayer insulating film of the cathode voltage line region; The capacitor may be a first capacitor formed by overlapping the gate metal and the semiconductor pattern, and a second capacitor formed by overlapping the gate metal and the first source / drain metal. . The method of claim 1, wherein the noise preventing means,  An insulating substrate including a power supply voltage line region and a cathode voltage line region; A semiconductor pattern formed on the power supply voltage line region and the cathode voltage line region of the insulating substrate; A gate insulating film formed on the insulating substrate including the semiconductor pattern; A gate metal formed on the gate insulating film; An interlayer insulating film formed on the gate insulating film and having a first contact hole exposing the semiconductor pattern and a second contact hole exposing the gate metal; A first source / drain metal contacted with the semiconductor pattern through the first contact hole, contacted with the semiconductor pattern through the first contact hole of the interlayer insulating film, and formed on the interlayer insulating film of the power supply voltage line region; A second source / drain metal contacted to the gate metal through the second contact hole and formed on the interlayer insulating film of the cathode voltage line region; And the capacitor is formed by overlapping the gate metal and the semiconductor pattern. The method of claim 3, wherein the gate metal The display device of claim 1, wherein the noise of the power supply is formed so as not to overlap with the first source / drain metal. The method of claim 1, wherein the noise preventing means, An insulating substrate including a power supply voltage line region and a cathode voltage line region; A semiconductor pattern formed on the power supply voltage line region and the cathode voltage line region of the insulating substrate; A gate insulating film formed on the insulating substrate including the semiconductor pattern; A first gate metal formed on the gate insulating film in the power supply voltage line region; A second gate metal formed on the gate insulating layer in the cathode voltage line region; A first contact hole formed on the gate insulating layer and exposing the first gate metal in the power supply voltage line region, a second contact hole exposing the semiconductor pattern in the power supply voltage line region and the second gate; An interlayer insulating film having a third contact hole exposing a metal; A first source / drain metal contacted with the first gate metal through the first contact hole, contacted with the semiconductor pattern through the second contact hole, and formed on the interlayer insulating film of the power voltage line region; A second source / drain metal contacted with the gate metal through the third contact hole and formed on the interlayer insulating layer of the cathode voltage line region; And the capacitor is formed by overlapping the gate metal and the semiconductor pattern. The method of claim 5, wherein the second gate metal And a noise of a power source, wherein the power source is formed in a range not overlapping with the first source / drain metal. The method of claim 5, wherein the first gate metal And a noise of a power supply, overlapping the first source / drain metal.