KR20050082454A - Layout structure of scalable two transistor memory cell - Google Patents

Abstract

The present invention relates to a layout structure of a STTM cell in which two shrinkable transistor memory (STTM) cells each including one sensing transistor and one program transistor are arranged in a matrix form, the ground line being connected to a source of the sensing transistor, By disposing bit lines connected to the drain of the sensing transistor in a vertical direction so that the drain lines of the sensing transistor of the STTM cell and the drain of the sensing transistor of the adjacent STTM cell are commonly connected, unnecessary space for isolating the drain terminals of the sensing transistors from each other is eliminated. A layout structure of two shrinkable transistor memory (STTM) cells that can be minimized to reduce cell array area and be highly integrated is disclosed.

Description

Layout structure of two shrinkable transistor memory (STMM) cells

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the layout of semiconductor devices and, more particularly, to the layout of two shrinkable transistor memory (STTM) cells.

Since DRAM devices are composed of one transistor and one capacitor, they can be highly integrated compared to memory devices such as SRAM devices. However, the DRAM device is difficult to maintain the data stored by the leakage current generated from the memory cell, and the refresh operation is performed to prevent the soft error, etc. caused by the leakage current, internal noise, and alpha particles incident from the outside. There is a disadvantage that this is necessary.

In contrast, devices such as a flash memory have an advantage of not requiring a refresh operation of the memory cell to maintain data stored in the memory cell. However, a flash memory device has a relatively long time for programming a memory cell, which increases the access time. In addition, a high voltage is required to program (write) or erase the memory cells of the flash memory device, and a high electric field applied to perform the erase and program operations reduces the film quality of the tunneling barrier layer made of an oxide film. It has the disadvantage of shortening the life.

Accordingly, there is a need for a semiconductor memory device capable of having advantages of the DRAM and flash memory devices, that is, long data retention, low power, high speed, high reliability, and high integration. A scalable two transistor memory cell (STTM) cell has been proposed. The STTM cell has an electrically isolated memory node, which is excellent in resistance to soft errors, and has a high signal-to-noise ratio (S / N ratio), resulting in high gain, nonvolatile, high speed, low power and It is characterized by high density. In addition, the STTM cell is an quantum tunneling device that operates at room temperature without deterioration by hot carriers, and thus, may be manufactured by using a technology of a conventional semiconductor manufacturing process.

FIG. 1 is a circuit diagram illustrating a configuration of two collapsible transistor memory (STTM) cells, which will be described below with reference to FIG. 1.

Referring to FIG. 1, a STTM cell includes a program (top) transistor 10, commonly known as a write transistor, and a sensing (bottom) transistor 20, known as a read or access transistor. The program transistor 10 is a MOS transistor including a vertical control gate having a multiple tunnel junction (MTJ) barrier layer between a source and a drain, and the source is a data line DL. The drain is commonly connected to the floating gate of the sensing transistor 20 and one end of the coupling capacitance 30. In addition, the sidewall gate is commonly connected to the control line (CL) or the other end of the parasitic transistor 30. The sensing transistor 20 is basically a MOS transistor including a floating gate having a function of a storage node of a memory cell. A source is connected to a ground line GND and a drain is connected to a bit line BL.

Referring to the operation of the STTM cell, first, during a write operation, a data voltage is applied to the data line DL and a write voltage, that is, a program voltage is applied to the control line CL, through the insulating layer of the MTJ barrier layer. The tunneling current flows to store data in the floating gate of the sensing transistor through the program transistor. The write operation of the STTM cell may use a lower level of voltage than that of a flash memory device. During a read operation, a read voltage is applied to the control line CL, and a voltage of a predetermined level is applied to the ground line GND to sense data flowing through the bit line BL to read data. In this case, when the threshold voltage of the sensing transistor 20 is higher than the read voltage, no current flows in the bit line BL, and when the threshold voltage of the sensing transistor 20 is lower than the read voltage, the bit line Current flows to BL. Thus, there is no need to refresh the STTM cell when the read voltage is lower than the write voltage.

FIG. 2 is a circuit diagram illustrating a layout structure of a cell array region including two collapsible transistor memory (STTM) cells according to the related art. With reference to Figure 2 looks at the center of the problem with the prior art.

Referring to FIG. 2, a layout structure of a cell array region including two shrinkable transistor memory (STTM) cells according to the related art is a bit line connected to a drain of a sensing transistor, a data line connected to a source of a program transistor, and the sensing transistor. Ground lines connected to the sources of are arranged side by side in the same direction. Accordingly, the sensing transistor is disposed in the same direction as the bit line and the data line so that the source of the sensing transistor is connected to the bit line and the drain is connected to the ground line.

As such, when the ground line connected to the source of the sensing transistor and the bit line connected to the drain of the sensing transistor are disposed adjacent to each other in the same direction, a spaced interval is required to isolate the drain terminals of the sensing transistor, thereby providing a cell array area. This increasing problem occurs. In particular, when the STTM cell is configured as a unit memory cell, the integration of the STTM device becomes more difficult considering the need for a data line in addition to the bit line and the control line (or word line).

Accordingly, it is an object of the present invention to provide a layout structure of two shrinkable transistor memory (STTM) cells consisting of one sensing transistor and one program transistor, which can solve the above-mentioned conventional problems.

Another object of the present invention is to arrange the ground line connected to the source of the sensing transistor and the bit line connected to the drain of the sensing transistor in a vertical direction so as to be common to the drain of the sensing transistor of the STTM cell adjacent to the drain of the sensing transistor of the STTM cell. By providing a connection, a layout structure of two collapsible transistor memory (STTM) cells arranged so that there is no space for isolating the drain terminals of the sensing transistors from each other is provided.

It is still another object of the present invention to significantly reduce the area of the STTM cell array by eliminating unnecessary space to isolate the drain terminals of the sensing transistors from each other, and to allow two more compactable elements to be formed by increasing the number of STTM cells in the same area. The present invention provides a layout structure of a transistor memory cell.

In order to achieve the above object, the layout structure of two shrinkable transistor memory (STTM) cells according to the present invention is a matrix of two shrinkable transistor memory (STTM) cells composed of one sensing transistor and one program transistor. A layout structure of an STTM cell arranged in a form, comprising: a control line connected to a control gate of the program transistor along a first direction of the STTM cell and commonly connected to a drain gate of the program transistor and a floating gate of the sensing transistor; A data line connected to a source of the program transistor along a second direction of a cell, spaced apart from the data line in the same direction, and a bit line connected to a drain of the sensing transistor and disposed in a vertical direction to the bit line; Spaced in the same direction as the control line Value is provided with a ground line connected to the source of the sense transistor.

In addition, the source / drain of the sensing transistor is disposed in the same direction as the data line, and the drain of the sensing transistor adjacent to the drain of the sensing transistor is arranged to be commonly connected to one control line, and the ground line is the STTM. The source transistor is arranged to be commonly connected to the source of the sensing transistor of the STTM cell adjacent to the source of the sensing transistor of the cell.

In order to solve the above technical problem, the layout structure of two collapsible transistor memory (STTM) cells according to the present invention includes a sensing transistor as a lower transistor and a program transistor as an upper transistor. And a layout structure of the STTM cells arranged in a matrix so as to have a second direction, wherein the STTM cells are arranged along the first direction and spaced apart in the same direction as control lines that provide a control voltage to the control gate of the program transistor. And ground lines connected to the source of the sensing transistor.

In addition, the source / drain of the sensing transistors is disposed in the same direction as the data lines, the source and the drain of the sensing transistors are alternately disposed, and the drain of the sensing transistor adjacent to the drain of the sensing transistor is one. It is arranged to be commonly connected to the control line.

Further, data lines connected to the source of the program transistor along the second direction of the STTM cell to provide data to the STTM cell, spaced apart from each other in the same direction as the data lines, and alternately disposed with the data line. And bit lines connected to drains of the sensing transistors.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The descriptions in the various embodiments are only shown and limited by way of example and without intention other than the intention to help those of ordinary skill in the art to more thoroughly understand the present invention, and thus the scope of the present invention. It should not be used as a limitation.

FIG. 3 is a circuit diagram showing a layout structure of a cell array region including two collapsible transistor memory (STTM) cells according to an embodiment of the present invention, each of four control lines, data lines, and bit lines, and two ground lines. This arranged circuit is shown. Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying FIG. 3.

As shown in FIG. 3, a layout structure of an STTM cell array in which STTM cells including one sensing transistor and one program transistor are arranged in a matrix form may be arranged along the first direction (X-axis direction) of the STTM cells. Control lines CL0, CL1, CL2, and CL3 connected to the control gates of the program transistor and commonly connected to the floating gate of the program transistor and the floating gate of the sensing transistor, and along the second direction (Y direction) of the STTM cell. Data lines DL0, DL1, DL2, and DL3 connected to the source of the program transistor, and bit lines BL0, BL1, BL2, and BL3 spaced apart in the same direction as the data line and connected to the drain of the sensing transistor; A vertical direction of the bit line and spaced apart from the control line to be connected to the source of the sensing transistor; Ground line GND is formed.

The ground line GND of the STTM cell array is spaced apart in parallel in the same direction as the control lines CL0, CL1, CL2, and CL3 and connected to the source of the program transistor. In addition, the control line CL is commonly connected to one end of the source and coupling capacitance of the sensing transistor, and one ground line GND is disposed between the first control line CL0 and the second control line CL1. The other ground line GND is disposed between the third control line CL2 and the fourth control line CL3.

In addition, the data lines DL0, DL1, DL2, and DL3 and the bit lines BL0, BL1, BL2, and BL3 of the STTM cell array are spaced apart in parallel in the same direction, and the data lines DL are arranged in the program. The bit line BL is connected to the drain of the sensing transistor. In addition, the data line and the bit line are disposed in a vertical direction with the control lines CL0, CL1, CL2, and CL3 and the ground line GND, and the data lines and the bit lines are alternately disposed.

Therefore, according to the exemplary embodiment of the present invention, the ground line is disposed in the vertical direction with the data line and the bit line, and is disposed to be commonly connected between the control line and the drain of the sensing transistor adjacent to the drain of the sensing transistor.

4 is a legend diagram of a layout limited to an embodiment of the present invention, in which a control line 210 and a data line 220 are shown in a layout diagram of two collapsible transistor memory (STTM) cells according to an embodiment of the present invention. Bit line 230 and ground line 240 are shown separately. In addition, the first contact 250 and the second contact 260 to which the lines are connected are shown separately.

5 is a plan view illustrating a layout structure of a cell array region including two collapsible transistor memory (STTM) cells according to the related art, and FIG. 6 is a collapsible two transistor memory STTM according to an embodiment of the present invention. A plan view showing a layout structure of a cell array region composed of cells.

5 and 6, a layout structure of a cell array region including two collapsible transistor memory (STTM) cells and a cell composed of two collapsible transistor memory (STTM) cells according to the related art according to an exemplary embodiment of the present invention. A comparison of the layout structure of the array area is as follows.

First, referring to FIG. 5, the bit line BL, the data line DL, and the ground line GND are spaced apart at regular intervals in the same direction, and the first data line 132 and the second data line 134 are disposed. The first ground line 142 is disposed therebetween. The second ground line 144 is disposed between the third data line 136 and the fourth data line 138. In addition, the control line CL is disposed in a direction perpendicular to the ground line GL, and contacts to which the bit line BL and the ground line GND are connected to the source / drain of the sensing transistor of the STTM cell ( 150 is formed. Here, the drains D1, D2, D3, and D4 of the sensing transistor of the STTM cell are connected to the respective bit lines 132, 134, 136, and 138, and the sources S1, S2, S3, and S4 are each ground line. The sensing transistor is formed in the same direction as the control line CL in order to be connected to the 142 and 144. Thus, space for drain terminals of the sensing transistors to be isolated on the same control line CL is required, thereby increasing the STTM cell array area.

As shown in FIG. 6, unlike the prior art, the ground lines GND are spaced at regular intervals in the same direction as the control lines 212, 214, 216, and 218, and the data lines 222, 224, and 226. 228 and the bit lines 232, 234, 236, and 238 are arranged in a vertical direction. In addition, the ground line 244 is disposed between the first control line 214 and the second control line 216 of the control line.

In addition, the sensing transistor is formed in the same direction as the data line DL so that the source and drain S1, D1, S2, D2, and S3 of the sensing transistor are disposed perpendicular to the control line CL. The sources and drains of are to be arranged alternately. In addition, the first contacts 250 may connect the sources S1, S2, S3 of the sensing transistor and the ground line GND, and the drains D1, D2, and the bit line BL of the sensing transistor. It is shown that the second contacts 260 are formed.

Accordingly, the ground line is disposed to be commonly connected to the source of the sensing transistor of the STTM cell and the source of the sensing transistor of the STTM cell adjacent to each other, and the drain of the sensing transistor adjacent to the drain of the sensing transistor is common to one control line. By being arranged to be connected, space for isolating the drain terminals of the sensing transistors from each other is unnecessary.

According to the related art, the ground line connected to the source of the sensing transistor and the bit line connected to the drain of the sensing transistor are arranged in parallel in the same direction, so that a predetermined interval is required to isolate the drain terminals of the sensing transistor.

However, as described above, according to the layout structure of two collapsible transistor memory (STTM) cells according to an embodiment of the present invention, a ground line connected to the source of the sensing transistor and a bit line connected to the drain of the sensing transistor are provided. By placing them vertically so that the drains of the sensing transistors of the STTM cells and the drains of the sensing transistors of the adjacent STTM cells are commonly connected, the unnecessary space for isolating the drain terminals of the sensing transistors can be minimized, thereby significantly reducing the area of the STTM cells array. In other words, it is possible to have more STTM cells formed in the same area to enable high integration.

The layout structure of two shrinkable transistor memory (STTM) cells according to an embodiment of the present invention is not limited to the above embodiment, and various designs and applications can be made without departing from the basic principles of the present invention. It will be apparent to those skilled in the art to which the invention pertains.

As described above, the present invention relates to a structure of an STTM cell in which two shrinkable transistor memory (STTM) cells composed of one sensing transistor and one program transistor are arranged in a matrix, and connected to a source of the sensing transistor. By separating the ground line and the bit line connected to the drain of the sensing transistor in the vertical direction so that the drain terminal of the sensing transistor of the STTM cell and the drain of the sensing transistor of the STTM cell adjacent to each other is isolated, the drain terminals of the sensing transistors are isolated from each other. Has the effect of minimizing unnecessary space.

In addition, the present invention significantly reduces the STTM cell array area in the layout structure of the STTM cell in which two shrinkable transistor memory (STTM) cells, each of which is composed of one sensing transistor and one program transistor, are arranged in a matrix form. More STTM cells can be formed in the same area, enabling high integration.

1 is a circuit diagram showing the configuration of two shrinkable transistor memory (STTM) cells

2 is a circuit diagram showing a layout structure of a cell array region composed of two shrinkable transistor memory (STTM) cells according to the prior art.

3 is a circuit diagram showing a layout structure of a cell array region composed of two collapsible transistor memory (STTM) cells according to an embodiment of the present invention.

Figure 4 is a legend diagram of the layout limited to the prior art and the embodiment of the present invention

5 is a plan view showing a layout structure of a cell array region consisting of two shrinkable transistor memory (STTM) cells according to the prior art;

6 is a plan view showing a layout structure of a cell array region composed of two collapsible transistor memory (STTM) cells in accordance with an embodiment of the present invention.

<Description of Reference Symbols for Main Parts of Drawings>

210: control line CL 220: data line DL

230: bit line BL 240: ground line GND

250: first contact 260: second contact

Claims (12)

In a layout structure of an STTM cell in which two collapsible transistor memory (STTM) cells consisting of one sensing transistor and one program transistor are arranged in a matrix form: A control line connected to a control gate of the program transistor along a first direction of an STTM cell and commonly connected to a drain of the program transistor and a floating gate of a sensing transistor; A data line connected to a source of the program transistor along a second direction of the STTM cell; A bit line spaced apart from the data line in the same direction and connected to a drain of the sensing transistor; And a ground line disposed perpendicular to the bit line and spaced apart in the same direction as the control line and connected to a source of the sensing transistor. 2. The method of claim 1, Wherein said first direction and said second direction are perpendicular to each other. The method of claim 1, And a source / drain of said sensing transistor arranged in the same direction as said data line. The method of claim 3, wherein And a drain of the sensing transistor adjacent to the drain of the sensing transistor is arranged to be commonly connected to one control line. The method of claim 3, wherein And a source and a drain of the sensing transistor are disposed alternately with each other. The method of claim 1, Wherein said ground line is arranged in common connection with a source of a sensing transistor of said STTM cell and a source of a sensing transistor of an adjacent STTM cell. The method of claim 1, And the data line and the bit line are alternately arranged with each other. The method of claim 1, And a coupling capacitance further coupled between the control line and the floating gate of the sensing transistor. In a layout structure of an STTM cell in which a sensing transistor is configured as a lower transistor and a program transistor is configured as an upper transistor, the STTM cells arranged in a matrix form have a first direction and a second direction: A ground line disposed along a first direction of the STTM cell, spaced apart in the same direction as control lines providing a control voltage to a control gate of the program transistor, and connected to a source of the sensing transistor; Layout structure of two shrinkable transistor memory (STTM) cells. The method of claim 9, And the source / drain of the sensing transistors are disposed in the same direction as the data lines, and the source and drain of the sensing transistors are alternately disposed with each other. The method of claim 10, And a drain of the sensing transistor adjacent to the drain of the sensing transistor is arranged to be commonly connected to one control line. The method of claim 9, Data lines connected to a source of the program transistor along a second direction of the STTM cell to provide data to the STTM cell; And bit lines spaced apart from each other in the same direction as the data lines and alternately arranged with the data lines, the bit lines being connected to the drain of the sensing transistor.