KR20050081721A - Apparatus using pll for scan testing at speed of semiconductor chip - Google Patents

Abstract

The present invention relates to a technology that enables a test using a high-speed clock signal in a system for testing a non-memory semiconductor chip using a scan structure, reduces the frequency of occurrence of a delay failure, and enables a fast delay failure test. . The present invention includes a PEL (PLL) (61A), (61B) for controlling the phase of the system clock signal (SYS_CLK) to output the operating speed clock signal (CKA), (CKB) of different phases and periods; A test clock signal generator 62 for synchronizing the scan movement clock signal SCK input from the outside with the operation speed clock signals CKA and CKB generated therein; A capture signal generation unit 63 for synchronizing the capture signal SE input from the outside with the scan movement clock signals SCKA and SCKB generated by the test clock signal generation unit 62; Test target circuit 64 for receiving the operation speed clock signals tCKA and tCKB output from the test clock signal generator 62 and the capture signals SEA and SEB output from the capture signal generator 63. Is achieved by

Description

APELATUS USING PLL FOR SCAN TESTING AT SPEED OF SEMICONDUCTOR CHIP}

The present invention relates to a technique for testing a non-memory semiconductor chip using a scan structure, and more particularly, to test using a high-speed clock signal, to reduce the frequency of occurrence of a delay failure, and to enable a fast delay failure test. The present invention relates to a scanning speed test apparatus for a semiconductor chip using PLEL.

The scan (SCAN) structure is the most widely used technique for the test of non-memory semiconductors and can detect defects in the semiconductor process by performing Automatic Test Pattern Generation (ATPG) for fixing failures. However, as semiconductor technology becomes smaller and the frequency of clock signals increases, the proportion of delay faults among semiconductor defects increases. Many recent experimental evidence indicates that shipping the final semiconductor without ignoring or testing delay failures can no longer guarantee the desired quality.

The delay faults are largely classified into transition faults and path delay faults. Delay failure detects a failure that causes chip malfunction due to accumulation of delay defects on a path, and the number of paths existing in a circuit is close to infinity, which limits its application to actual semiconductor tests. Therefore, the delay failure model mainly used in the industry is a transition failure.

Technical methods for detecting a transition failure can be classified into three types. The first is to use functional patterns. However, as the frequency of the clock signal increases, the amount of data for the operation speed test increases. Moreover, due to the cost of developing functional patterns, the difficulty of debugging the developed patterns, and the need for ultra-high cost test equipment, the operation speed test technique using the functional patterns is gradually moving away from the interest.

Second, there is a method using a logic built-in self test (BIST) that can test the circuit under test in-chip itself as shown in FIG. 1. A pattern can be generated at the operating speed of the semiconductor and the response can be analyzed to determine whether there is a failure in the circuit. In this way, using BIST enables high test quality, and the internal PLL enables the test to be performed regardless of the performance of the test equipment. However, in the case of using the BIST, many constraints such as multiple clock signals, mixed edge design, excessive power consumption, hierarchical structure, and design method must be overcome. Therefore, more manpower, time, and cost are required to implement BIST.

Finally, there is a scan-based speed test method, which is a design for testability technique that is widely used in the industry, and the industry is paying attention to the usefulness of the speed test technology based thereon.

The prior art for the scan-based speed test can be divided into two categories. FIG. 2 shows a method of a global delay test, and FIGS. 3 and 4 show a skewed load transition test and a launch-off-shift method. Basically, for the delay failure test, a transition is generated at the primary input or the scan flip-flop to capture the transition at the primary output or the flip-flop.

Therefore, the main technique for performing the operation speed test is a method of generating a pair of clocks for generation and capture of a transition. The global delay test method shown in FIG. 2 uses a pair of operating speed clock pulses in a normal mode of operation. The first pulse generates a transition and the second pulse captures the transition in the scan cell. This method allows for early skewing and late skewing within the generation and capture clock cycles. The main advantage of this technique is that the timing constraints of the capture signal scan (SE) are loose compared to the skew load transition test, making it easier to construct a scan chain.

However, Jacob Savir has shown that this approach is generally low in experiments in the broad-side delay test (IEEE Trans. On CAD, Vol. 13, No. 8, Aug, 1994, pp. 1057 SIM 1064). It has a failure detection rate and, in particular, has poor performance compared to the skew rod transition test. The global delay test utilizes the circuit's operating function of the transition so that the flip-flop for generating the transition has low controllability, resulting in low failure detection rate. In addition, the global delay test method requires the test equipment to be able to supply two clock signals having different frequencies to one clock pin when using external equipment.

In particular, most high-speed operation semiconductors currently on the market are equipped with a PLL (PLL) to convert a low frequency clock signal into an internal high frequency clock signal. Therefore, in order to enable an operating speed scan test, a global delay test must generate and capture a transition to the internal PLL clock. However, due to the performance of the test equipment, internal fast PLL clock signal frequencies do not allow vectors to be applied to the chip's input pins, nor are they capable of capturing values at the output. This has the disadvantage of obtaining a lower failure detection rate.

Global delay tests using internal PLLs are described in two studies, (1) Xijiang Lin et al., "Novel techniques for achieving high at speed transition fault test coverage for motorola's microprocessors based on PowerPC instruction set architecture," IEEE VLSI Test Symp., 2002, (2) Nandu Tendolkar et al., "High-frequency, at-speed scan testing," was applied to IEEE Design & Test of computers, Sep.-Oct. 2003, and did not solve the aforementioned disadvantages. In addition, the methods used in this study have a big disadvantage that the existing ATPG tool cannot be used as it is. In particular, only a circuit having only one operating speed clock signal is used and a method for processing multiple clock signals has not been developed yet.

Meanwhile, only methods using test equipment have been developed for the skew load transition test shown in FIGS. 3 and 4, and a method using a high speed clock signal generated inside a chip such as a PLL has not been developed yet. For scan-based tests, the scan shifting speed does not exceed the maximum speed that the device can support. Most semiconductor test equipment can only support low frequency scan movement speeds, so scan movements are typically performed at low speeds. Since the capture clock signal must be supplied at the operation speed for the operation speed test, a method of adjusting the skew of the clock signal is used as shown in FIGS. 3 and 4.

As shown in FIG. 3 and FIG. 4, the cycles divided into the scan movement, the transition, and the capture intervals all have the same frequency, but only the phase delay of the clock signal. Therefore, the test equipment generates a clock signal having a phase suitable for each cycle, and supplies a clock signal suitable for scan movement, transition generation, and capture cycles using a multiplexer (MUX) according to a section. Since the skew load transition test method does not need to consider the frequency of the clock during the ATPG process, the existing ATPG can be used as it is, except for the interclock domain, the multi-cycle path (MCP), Consideration should be given to a false path. This consideration must be taken into account for global delay testing as well.

The skew load transition test method using external equipment cannot use the clock signal generated inside the chip, so it is impossible to test the operation speed of the chip having high speed operation. Also, as mentioned earlier, global delay testing has several drawbacks. To solve this problem, it is necessary to develop a technology that can apply the skew load transition test method to a chip having an internally generated clock signal. In addition, since most chips have multiple clock structures, it is necessary to develop an operation speed test technique.

On the other hand, Figure 5 shows a test target circuit according to the prior art. The circuit under test is an example of a circuit using two PLLs 51A and 51B and one system clock signal SYS_CLK. In a typical low speed test circuit, the clock signal SCK is supplied to the test target circuit 53 through the multiplexers 52A and 52B by the test mode signal TM and used simultaneously as a scan shift clock signal and a capture clock signal. It became. In this example, the clock signal SCK is multiplexed with two normal operation clock signals CKA and CKB through one pin, but corresponding to each of the normal operation clock signals CKA and CKB. A test clock signal may be used.

Therefore, the first object of the present invention is to solve the disadvantage of the conventional skew rod transition test.

A second object of the present invention is to solve the shortcomings of a typical global load test.

A third object of the present invention is to enable scan-based speed test using conventional ATPG tools.

A fourth object of the present invention is to reduce instantaneous power consumption in scan based operating speed test.

A fifth object of the present invention is to enable an operation speed test in the form of a skew load transition test for a chip having a high speed internally generated clock.

According to a first aspect of the invention, a test clock signal generator for synchronizing a scan movement clock signal supplied from the outside and the capture clock signal generated therein; And a capture signal generation unit configured to output a capture signal input from the outside in synchronization with a scan movement clock signal generated by the test clock signal generation unit.

According to a second aspect of the present invention, timing for the skew load transition test is implemented using an internal PLL.

According to the third aspect of the present invention, the synchronization circuit generates a scan movement signal for each capture clock by synchronizing the scan movement clock signal with each capture clock signal.

According to the fourth aspect of the present invention, the capture signal generation unit can distinguish a capture section for each clock, and only one capture clock is generated in the capture section.

According to a fifth aspect of the invention, one external signal is used to distinguish between an operating speed test and a normal low speed test mode.

According to the sixth aspect of the present invention, an ATPG generated for each existing clock domain is generated for the entire circuit.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

FIG. 6 is a block diagram illustrating an exemplary embodiment of an apparatus for scanning a scan speed of a semiconductor chip using a PEL according to the present invention. As shown in FIG. PLL (PLL) 61A, 61B which outputs the operation speed clock signal CKA, CKB of a period; A test clock signal generator 62 for synchronizing the scan movement clock signal SCK input from the outside with the operation speed clock signals CKA and CKB generated therein; A capture signal generation unit 63 for synchronizing the capture signal SE input from the outside with the scan movement clock signals SCKA and SCKB generated by the test clock signal generation unit 62; Test target circuit 64 for receiving the operation speed clock signals tCKA and tCKB output from the test clock signal generator 62 and the capture signals SEA and SEB output from the capture signal generator 63. When described in detail with reference to FIGS. 2 to 10 attached to the operation of the present invention configured as described above as follows.

FIG. 6 is a block diagram of an apparatus for scanning a scan speed of a semiconductor chip using a PEL according to the present invention, and may be classified into a test clock signal generator 62 and a capture signal generator 63.

An embodiment of the test clock signal generator 62 is illustrated in FIG. 7. 7 shows only a circuit for one clock signal tCKA, and has the same structure for another clock signal. Here, if the value of (AC, TM) is (1, X), it is an operation speed test mode, if (0, 1) is a normal low speed test mode, and (0, 0) represents a normal operation mode. The main function of the circuit shown in FIG. 7 is to synchronize two clock signals that do not match the phase delay, that is, the scan shift clock signal SCK and the internally generated operating speed clock signal CKA. However, since the phase delay of the operation speed clock signal CKA is unknown from the outside of the chip, the synchronization between the scan shift clock signal SCK, which is an external clock signal, and the scan shift clock signal CKA, which is an internal clock signal, is achieved. Facilitate scan movement and capture. According to the sampling theory, the scan shift clock signal SCK, which is a slow clock signal, should be smaller than half of the frequency of the operation speed clock signal CKA, which is a sampling clock signal. However, in order to guarantee the operation accuracy, the sampling error should be eliminated by using the smaller than 1/4 maximum.

In addition, in order to ensure the correct operation of the circuit, the ratio of the section when the waveform of the scan shift clock signal SCK is 1 and the section when 0 is 40% to 60%. This is to prevent sampling of the same value during the sampling operation due to the phase delay between the two clock signals when the period of 1 or 0 of the scan movement clock signal SCK is smaller than the period of the operation speed clock signal CKA.

The operation speed clock signal tCKA generated in FIG. 7 is used as a test clock signal of a flip-flop using the clock signal in the operation speed test. In addition, SCKA is used as the scan shift clock signal and CKA is used as the capture clock signal. The flip-flop using the operating speed clock signal CKB in the normal operation mode uses tCKB generated in the same manner as in FIG. 7 as a test clock signal.

6 shows a block diagram only for a circuit having two normal operating clock signals. In another embodiment, the clock signals SCKA and tCKA may be generated as shown in FIG. 7 even for a circuit having a large number of clock signals. The capture signal SEA used as an input in FIG. 7 is a signal representing a capture section, which is a signal supplied to the SE terminal of the scan flip-flop. By generating the corresponding scan movement clock signal for each internal clock signal, each scan chain can perform scan movement without synchronizing with other clock signals, thereby greatly reducing the dynamic power loss due to synchronization. .

The capture signal SEA is generated by the capture signal generator 63, and an embodiment thereof is illustrated in FIG. 8. The capture signal SE input from the outside is synchronized with the scan movement clock signal SCKA generated by the test clock signal generator 62. The reason why the scan shift clock signal SCKA is used as the synchronization clock signal is as follows. In FIG. 7, the rising transition of the two clock signals may occur simultaneously during the synchronization of the operation speed clock signal CKA and the scan shift clock signal SCK. This is because the value of the scan movement clock signal SCKA may be delayed by the period of the operation speed clock signal CKA at this time. In this case, the capture signal SEA is synchronized with the operation speed clock signal SCKA so that the capture signal SEA is always generated in time delay than the scan movement clock signal SCKA. Otherwise, a problem occurs where the scan movement section and the capture section overlap.

As another embodiment of the test clock signal generator 62, an input clock signal of the PLL may be used instead of the scan movement clock signal SCK. Each PLL may also have a separate input clock signal.

In the normal operation mode as shown in FIG. 8, the capture signal SE is directly supplied to one input terminal of the multiplexer 82, and the capture signal SE is synchronized with the scan shift clock signal SCKA to allow the multiplexer ( It is supplied to the other input terminal of 82, and the capture signal SEA is generated by controlling the switching of the multiplexer 82 with the mode signal AC. In the same manner, another capture signal SEB is generated. As a result, the capture signal SE is divided into two capture signals SEA and SEB. Therefore, when the skew load transition test is used in the design stage, it is easy to make and use a capture signal (SE) terminal for each clock. This adds one signal inside the circuit, and the pin count of the chip remains unchanged. In addition, since the HFNCTS (High Fanout Net Clock Tree Synthesis) is performed on the capture signal SE generated for each clock in the placement and wiring stages, the phase delay and skew may be more accurately adjusted.

In another embodiment, when it is difficult to satisfy the time constraints of the capture signals SEA and SEB, a pipeline technique that passes through multiple stages of flip-flops is used. In this case, the SE signal must be generated in advance by multiplying the SCK period by the number of stages of the flip-flop.

As another embodiment, there may be a method of using the capture signal SE of a conventional test target circuit as it is. In FIG. 6, unlike the single capture signal SE divided into two capture signals SEA and SEB, only one capture signal SE is used. In this method, the test clock signal generator 62 and the capture signal generator 63 are configured as shown in FIGS. 7 and 8 for each clock signal, and then only one clock signal can be selected during the test operation. . In the case of two clock signals, an embodiment is shown in FIG.

FIG. 10 is a timing diagram of each part signal in FIG. 6. Even when a test clock signal exists for each normal operation, the same scan shift clock signal may be used for each test clock signal.

The ATPG process can be divided into two types. First, the capture signal is classified according to the clock signal of the circuit under test. This is a case in which one capture signal SE is divided into two capture signals SEA and SEB, as shown in FIG. 6, and when a scan-based operation speed test is performed, an unconstrained path, a multipath, and a heterologous clock signal. Liver zones cannot be tested at operating speed. Therefore, first, when performing ATPG, the flip-flop is masked at the boundary between the unconstrained path, the multi-cycle path, and the inter-clock signal region. ATPG is performed using a list of stuck failures not detected due to masking. The first of the test vectors generated by the two ATPGs is a test vector capable of detecting stuck and transition failures and is tested in the speed test mode. The second generated vector is intended to test for stuck failures in unconstrained paths, multi-cycle paths, and inter-clockwise intersecting zones. Through this process, it is possible to obtain a fixation failure detection rate as before, and to detect a fault in the clock signal region that occupies most of the circuit.

In another embodiment, in the ATPG method for the method shown in FIG. 9, a test vector should be generated for each clock signal region. Although the method described above only masks the unconstrained path, the multi-cycle path, and the inter-clock region, only one clock region is tested as mentioned above in order to use the method shown in FIG. 9.

Accordingly, the vector performing the ATPG as many as the clock signal and performing the test in the operation speed test mode and performing the ATPG for the undetected fixation failure performs the test in the low speed test mode. This method uses the clock signal of an existing external test equipment to perform the operation speed test (e.g. Jayashree, "Scan-based transition fault testing-implementation and low cost test challenged," IEEE Intl, Test Conf., 2002 , pp. 1120-1129). Conventional ATPG tools cannot recognize the circuit configuration presented in the present invention. Therefore, to solve this problem, set the low speed test mode and perform ATPG for the transition failure.

As described in detail above, the present invention implements a timing signal for skew load transition test using an internal PLL, and thus, the semiconductor chip may be tested using a high speed clock signal generated therein.

In addition, by synchronizing the scan movement clock signal to each capture clock signal to generate a scan movement signal for each capture clock signal, the capture signal generator distinguishes the capture interval for each clock signal, and generates only one capture clock signal in the capture interval. By doing so, it is possible to prevent the removal of the defective chip due to the delay failure.

In addition, since the high-speed test clock signal is used in the chip, high-speed delay failure test can be performed without purchasing expensive test equipment, thereby reducing test cost.

In addition, the present invention can be applied to a logic BIST technique and a test compression technique, and has an effect of solving a test power consumption problem, which is a problem in a high speed operation test.

1 is a block diagram of a logic BIST according to the prior art.

2 is a timing diagram of a clock signal for a global delay test.

3 is a timing diagram for a skew rod transition test.

4 is another timing diagram for a skew rod transition test.

5 is a block diagram of a test apparatus for a semiconductor chip according to the prior art.

Figure 6 is a block diagram of the operation speed scan test apparatus of the semiconductor chip using the PL.

FIG. 7 is a detailed block diagram of a test clock signal generator of FIG. 6. FIG.

FIG. 8 is a detailed block diagram of a capture signal generator in FIG. 6. FIG.

9 is a diagram illustrating an implementation in the case of using one capture signal.

(A)-(n) is a timing diagram of each part signal of FIG.

*** Description of the symbols for the main parts of the drawings ***

61A and 61B: PL 62: Test clock signal generator

63: capture signal generator 64: the circuit to be tested

Claims (4)

PEL (61A), (61B) for controlling the phase of the system clock signal to output the operating speed clock signal of different phases and periods; A test clock signal generator 62 for synchronizing the scan movement clock signal inputted from the outside with the operation speed clock signal generated therein; A capture signal generator 63 for synchronizing a capture signal input from the outside with a scan movement clock signal generated by the test clock signal generator 62; The semiconductor chip using PLEL comprising a test target circuit 64 which receives an operation speed clock signal output from the test clock signal generator 62 and a capture signal output from the capture signal generator 63. Speed scan test device. The PLL of claim 1, wherein the test clock signal generator 62 is configured to synchronize the capture signal with the operation speed clock signal so that the capture signal is always delayed in time than the scan movement clock signal. Scanning speed test device for semiconductor chips. 2. The apparatus of claim 1, wherein the capture signal generator (63) comprises: a multiplexer (81A) for outputting the captured signal in synchronization with the scan shift clock signal; According to the mode signal, the operation speed scan test of the semiconductor chip using the PEL, characterized in that it comprises a multiplexer 82 for selecting and outputting the capture signal or the capture signal supplied through the multiplexer 81A directly supplied. Device. The semiconductor chip of claim 1, wherein the test clock signal generator 62 and the capture signal generator 63 are configured to output a plurality of operating speed clock signals and a plurality of capture signals, respectively. Speed scan test device.