KR20050081228A - Apparatus and method for adapting for i2c bus - Google Patents

Abstract

The present invention relates to an I2C bus used in a network system, and by using an unused MDIO / MDC as an I2C bus in an unused MII management interface, MDIO / MDC, without using a separate I2C controller. An I2C bus matching device and method for enabling a bus are provided.

Description

I2C bus matching device and method {APPARATUS AND METHOD FOR ADAPTING FOR I2C BUS}

The present invention relates to a device using a MII interface between a PHY and a medium access control (MAC). The present invention relates to an I2C bus matching device and a method for using a MII (Media Independent Interface) management interface as an I2C bus.

1 is a diagram according to the prior art, illustrating a method of reading information through an I2C bus of a PMD transceiver module.

When initializing a system in the conventional network system as shown in FIG. 1, a network system user reads transceiver module information, that is, transceiver module information embedded in a physical medium dependent (PMD) 140 through an Ethernet device driver. . This transceiver module information is used by the host processor 100 to manage the network system.

Here, the I2C (Inter IC) bus is a transmission path used for serial communication. Using this I2C bus, the packet processor 110 can read transceiver module information stored in a storage means such as an EEPROM (Electrically Erasable Programmable Read Only Memory) built in the PMD 140. However, even if the host processor 100 does not or does not have an I2C controller, it may be used for other purposes. For example, since the A2 to A0 signals of the I2C device address selection signals of the PMD 140 are all set to "000", this may be a problem when they are tied to another general serial EEPROM 102 and one bus line. have. This is because each EEPROM cannot be distinguished because the address selection signals are all the same.

Therefore, when the main packet processing board and the PHY board are separated, the serial memory 102 connected to the I2C bus of the host processor 100 has board management information for storing board information, and the PMD 140 The serial memory in c) must be read by the packet processor 110 and delivered to the host process 100. However, since the packet processor 110 does not provide an I2C controller, a separate I2C controller 142 has to be added to the system. The addition of these separate I2C controllers involves problems such as increasing the size and cost of the system.

Therefore, there is a need for an apparatus and method capable of implementing an I2C bus without a separate I2C controller.

Accordingly, an object of the present invention is to provide an I2C bus matching device and method for providing an I2C bus without using a separate I2C controller.

The present invention does not use MII (Management Data I / O) and MDC (Management Data Clock), which are MII (Media Independent Interface) management interfaces, in a network system that provides a MII interface between a PHY and a MAC. The management interface provides matching between the I2C bus and the MII management interface serial bus.

Most MACs provide MIO management interface I / O, MDIO / MDC, as specified in IEEE 802.3 to read the status registers provided in the PHY. By the way, there are some MAC 120 including some of the PHY (130). In this case, MDIO / MDC is not used.

For example, GMAC in Gigabit Ethernet is optionally available to include the PCS layer that is part of the PHY. In this case, the MII interface between the PCS layer and the MAC layer is implemented in GMAC, so GMAC and SERDES (PMA layer). TBI interface is connected. In fact, if the MII interface is implemented in GMAC, the MDIO / MDC pins provided by the GMAC device will not be used. The SERDES device simply converts the 10 bits to serial to transfer to the transceiver module and vice versa. There is no MDIO / MDC interface because there is no internal PHY 130 associated register.

GBIC (GigaBit Interface Converter) having a serial memory that has its own module information in the PMD at the initialization of the network system as shown in FIG. Transceiver modules such as Small Form Factor Pluggable (SFP) are read by a packet processor or host processor via an I2C controller, and as described above, the MDIO / MDC I / O pins of the MAC are open and not used.

As such, the I2C bus may be implemented by using the MDIO / MDC which is not used in the system where the MDIO / MDC is not used.

The apparatus of the present invention for this purpose is a physical medium dependent (PMD) having a MAC requesting the transceiver information for management of the network system, an I2C bus interface serial memory for storing the transceiver information required by the Mac, and The transceiver information is read from the serial memory through an I2C bus and output to the MAC through a MII management interface, MDIO (Management Data I / O) / MDC (Management Data Clock), or from an MDIO / MDC signal input from the MAC. I2C matching including an MDIO-to-I2C bus converter which detects a start condition and an end condition of an I2C bus and converts it into address information for reading transceiver information from the PMD having an I2C bus format and outputs the same to the PMD. Device.

In addition, the method of the present invention for this purpose, a first step of receiving a signal to read the transceiver information stored in the PMD from the Mac through the MDIO / MDC, a second step of converting the signal into an I2C signal, and the conversion And a fourth process of outputting the received signal to the PMD through an I2C bus, and a fourth process of converting transceiver information input from the PMD into MDIO / MDC information and outputting the signal to the MAC.

Hereinafter, the present invention will be described with reference to the drawings. First, look at the characteristics of the MDIO / MDC to be used in the present invention.

2 is an MII management access timing diagram of IEEE802.3.

2A is an access timing diagram during a read operation between the packet processor and the I2C controller, and FIG. 2B is an access timing diagram during the write operation.

The MII management interface consists of MDIO and MDC. MDIO is a protocol that has a predetermined format including preamble, ST, and OP (operation) codes. According to the predetermined format, the MAC 120 accesses the PHY register through the MDIO, but the present invention intends to use the format as an I2C bus.

3 is an MII management access timing diagram between an I 2 C controller and a PMD.

4 is an address format transmitted over an I2C bus.

Information capable of representing an address format as shown in FIG. 4 must be transmitted via an I2C bus. Information represented through the format shown in FIG. 4 is information about a device to be read or written and a place to be read or written in the device.

FIG. 5 is a diagram illustrating three types of readings and an access method through the I2C bus. FIG. 5A is a diagram showing a current address diary, FIG. 5B is a random read, and FIG. 5C is a continuous read.

There are three types of data reading methods through the I2C bus, as shown in FIGS. 5A to 5C. In general, when reading the I2C serial memory in the PMD 140, 101000 1 (read) is always transmitted first. Here, 1010 is an ID of a device type indicating an I2C serial EEPROM, next "000" is a memory of A2 to A0, and a memory address in the PMD 140 is always "000" in accordance with GBIC regulations.

When the I2C master reads data to the slave device, it is always performed in the order of device address, memory address to be read, device address, and read data acquisition in random order. One of three ways is therefore determined.

Current Address Read of FIG. 5A shows the address information of the device and the information to be read from or written to the address. That is, data is read from the currently designated address position or data is written to the currently designated address position.

In the random read of FIG. 5B, the device address information and the information to be read or written are shown after a dummy composed of the device address and n word addresses. In other words, information is read or recorded with a dummy gap between them.

In the sequential read of FIG. 5C, information to be read or written after the device address information is continuously shown.

6 is a diagram illustrating a bus registration between an I2C bus and an MDIO according to the present invention.

The present invention reads the transceiver module information from the PMD 140 and the PMD 140 having the I2C bus interface serial memory (not shown) therein through the I2C as shown in FIG. O to the processor (packet processor / host processor) 600 via MDC and MDIO, or vice versa for the start and end conditions of the I2C bus coming from the processor 600 via MDIO and MDC via Mac 120 And a MDIO-to-I2C bus converter 610 which detects and changes this to the I2C bus format and sends address information and the like to read the transceiver module information to the PMD 140.

As illustrated in FIG. 6, the I2C bus and the MDIO serial bus may be matched through bus mapping through the MDIO-to-I2C bus converter 610.

Meanwhile, in the present invention, the direct connection with the MDIO-to-I2C bus converter 610 may help the understanding of the present invention by omitting reference to the Mac 120 or the Mac 120 rather than the processor 600. Where it is determined that the reference to the mac 120 has been omitted.

Referring to the operation of the present invention configured as described above are as follows.

FIG. 7 is a diagram according to the present invention, which illustrates an operation when writing an address value and a control value to be read to the I2C bus.

In Figure 7, S is Start, E is End (Stop), A is Ack, P is Preamble, T is Status. O indicates an OP code.

FIG. 7 shows the mapping between the MDIO and I2C buses performed by the MDIO-to-I2C bus converter 610 and MDIO-to-I2C bus converter 610 shown in FIG. 6. Referring to FIG. 7, the mapping operation from the MDIO to the I2C bus will be described. The MDIO I / F of the MDIO-to-I2C bus converter 610 may use the MDIO interface of the MAC 120 controlled by the processor 600. Removes preamble and ST of existing MDIO format from MDIO signal inputted through and interprets OP Code to distinguish Read / Write bit, and only 10-bit data content is S / P Reg. (Serial-to-parallel register) ) S / P Reg. (Serial-to-parallel register) converts the 10-bit input serial data into parallel data and outputs it to Buf Reg. (Buffer register). The Buf Reg. (Buffer register) follows the 2.5 MHz MDC clock.

The 10-bit data input to the buffer register is converted into SCL (Serial CLock) clock frequency 100KHz or 400KHz, read, converted into serial data in P / S Reg. (Parallel-to-serial register), In I2C I / F, a flag indicating the start condition and end condition is added to the I2C bus serial line. In the case of reading from the PMD 140, transmission is terminated when an Ack signal is received from the serial memory, and data stored in the Buf Reg. (Buffer register) is transmitted again when the Ack bit is not received.

In the opposite direction, when I2C bus data through the MDIO serial bus is input to the serial memory in the PMD 140, the data value is output from the serial memory. The I2C bus interface deletes the flag indicating the start condition and the end condition. After receiving all of the data, the Ack bit is sent to S / P Reg. And the acknowledgment bit is sent to the serial memory of the PMD 140. Once stored in the buffer register via S / P Reg. (Serial-to-parallel register), wait until the next MDIO cycle comes up in P / S Reg. Sent via MDIO That is, when the MDIO read format is received again by the processor 600 controlling the MDIO after a predetermined time, the MDIO I / F transmits 2.5MHz to the DIO serial line after one cycle of turn around.

Such a mapped format according to the present invention will be described with reference to FIG. 8.

8 is a diagram according to the present invention, illustrating the mapping between MDIO and I2C format.

Among the formats shown in FIG. 8, the format referred to as the conventional format above is the I2C bus format, and the format referred to as the format of the present invention below is the MDIO format. As shown in FIG. 8, the MDIO format uses read / write instead of the OP code of I2C. In addition, the MDIO format uses 10 bits for data and ACK, unlike the I2C format using 5 bits of PHY address and 5 bits of register address. The MDIO-to-I2C bus converter shown in FIGS. 6 and 7 performs a function of mapping an MDIO format and an I2C format having such a difference.

As shown in FIG. 8, when the present invention is applied, 10 bits of a conventional PHY and a Reg address are used as data and control bits for reading I2C, and an OP code is used as a Read / Write bit.

As described above, the present invention provides an I2C matching device and method that can implement an I2C bus without adding a separate I2C controller using an MII management interface not used in the system.

On the other hand, in the description of the present invention reference to and reference to specific examples of specific numerical values, such as the clock frequency described for the purpose of understanding the present invention, the present invention is not limited thereby. In addition, the specific systems mentioned in describing the present invention are not intended to limit the present invention.

By applying the present invention, the processor's I2C controller can be used for other purposes, so that the I2C bus can be implemented without adding a separate I2C controller in a system without redundant.

1 is a diagram according to the prior art, illustrating a method of reading information over an I2C bus of a PMD transceiver module.

Fig. 2 is an MII management access timing diagram of IEEE802.3, Fig. 2A is an access timing diagram during a read operation in a packet processor and I2C control period, and Fig. 2B is an access timing diagram during a write operation.

3 is an MII management access timing diagram between an I 2 C controller and a PMD.

4 is an address format transmitted over an I2C bus.

FIG. 5 is a diagram showing three types of I2C reads and an access method, FIG. 5A shows a current address diary, FIG. 5B shows a random read, and FIG. 5C shows a continuous read.

6 is a diagram of a bus registration between an I2C bus and an MDIO in accordance with the present invention;

FIG. 7 is a diagram in accordance with the present invention, illustrating an operation when writing an address value and a control value to be read into an I2C bus. FIG.

8 is a diagram according to the present invention, illustrating the mapping between MDIO and I2C format.

Claims (7)

MAC requesting transceiver information for management of network system, A Physical Medium Dependent (PMD) having an I2C bus interface serial memory for storing transceiver information required by the Mac, The transceiver information is read from the serial memory of the PMD through an I2C bus and outputted to the MAC through a Management Data I / O (MDIO) / Management Data Clock (MDIO), which is a MII (Media Independent Interface) management interface. MDIO-to-I2C which detects the start condition and the end condition of the I2C bus from the MDIO / MDC signal inputted from the device and converts the information into address information for reading transceiver information from the PMD having the I2C bus format and outputs the address information to the PMD. I2C matching device including a bus inverter. According to claim 1, wherein the MDIO-to-I2C bus converter, MDIO interface unit that removes preamble and start condition of existing MDIO format from MDIO signal input from Mac, interprets OP (Operation) code, and divides read / write bits to output 10 bits of data; A serial-to-parallel converter for receiving the 10-bit serial data from the MDIO interface unit and converting the serial data into parallel data; A buffer for receiving and storing the parallel data from the serial-to-parallel converter; A parallel-to-serial converter that reads parallel data stored in the buffer, converts the serial data into serial data, and outputs the serial data; And an I2C interface unit receiving the serial data from the parallel-to-serial converter and adding a flag indicating a start condition and an end condition and outputting the flag to the PMD through an I2C bus. The method of claim 2, And the serial data inputted to the serial-to-parallel converter and the serial data outputted from the parallel-to-parallel converter have different clock frequencies from each other. The method of claim 3, wherein And serial data input to the serial-to-parallel converter is data having an MDC clock frequency, and serial data output from the parallel-to-parallel converter are data having a serial clock clock (SCL) clock frequency. The I2C bus matching device of claim 2, wherein when the response to the signal transmitted to the PMD is not received, the I2C bus matching device retransmits the data stored in the buffer to the PMD. A first process of receiving a signal from a Mac to read the transceiver information stored in the PMD through MDIO / MDC; Converting the signal into an I2C signal; And a third process of outputting the converted signal to the PMD via an I2C bus. The method of claim 6, And converting the transceiver information input from the PMD into MDIO / MDC information and outputting the same to the MAC.