KR20050076166A - Level shifter with single input and liquid crystal display device employing the same - Google Patents

Abstract

Provided are a single input level shifter which performs a stable operation against a characteristic variation of a thin film transistor constituting a level shifter without increasing an area, and a thin film transistor liquid crystal display (TFT LCD) using the same. The single input level shifter of the liquid crystal display level shifts an externally applied digital logic signal to a gate driver or a data driver, and includes an intermediate voltage signal providing unit, an inverting unit, and a voltage signal comparing unit.

Description

Level shifter with single input and liquid crystal display device employing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single input level shifter and a thin film transistor liquid crystal display (TFT LCD) using the same. More specifically, a thin film constituting the level shifter without increasing the area is described. The present invention relates to a single input level shifter performing stable operation against variations in characteristics of a transistor and a thin film transistor liquid crystal display using the same.

In recent years, with the trend of miniaturization, weight reduction, and thinning of personal computers and televisions, display devices have also been required to be smaller, lighter, and thinner. In order to meet these demands, flat panel display devices such as liquid crystal displays (LCDs) are being developed instead of cathode ray tubes (CRTs).

A liquid crystal display device is a display device that obtains a desired image signal by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and adjusting the intensity of the electric field to adjust the amount of light transmitted through the substrate. Such a liquid crystal display device is a portable flat panel display device, and a thin film transistor liquid crystal display device (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

In general, a thin film transistor liquid crystal display device includes a plurality of gate lines that transmit scan signals, a plurality of data lines that transmit corresponding gray voltages according to an image data signal, and are insulated from and intersect the plurality of gate lines. A display unit including a plurality of pixels arranged in a matrix form having switching elements connected to a gate line and a data line in an area surrounded by the gate line, a gate driver providing a scan signal to the gate line, and a gray voltage to the data line And a level shifter configured to level shift the logic signal and to transfer the logic signal to the gate driver or the data driver.

Here, the level shifter receives a digital logic signal from an external timing controller and provides a voltage signal having a larger voltage than the digital logic signal to drive the gate driver or the data driver.

A level shifter of a conventional liquid crystal display device will be described with reference to FIG. 1.

When the input signal IN in the low state is transmitted to the level shifter of FIG. 1, the PMOS transistor MP5 is turned on to invert the input signal to the PMOS transistor MP2 and the NMOS transistor MN2. Since a high voltage signal of INB is applied, the PMOS transistor MP2 is turned off and the NMOS transistor MN2 is turned on so that the ground voltage is provided as the output signal OUT.

On the other hand, when the input signal in the high state is transmitted to the level shifter of FIG. 1, the NMOS transistor MN3 is turned on to invert the signal INB of the input signal to the PMOS transistor MP2 and the NMOS transistor MN2. Since the in-low voltage signal is applied, the PMOS transistor MP2 is turned on and the NMOS transistor MN2 is turned off so that the power supply voltage is provided as the output signal OUT. The level shifter thus provides a voltage signal that is larger than the voltage magnitude of the input signal by using the power supply voltage larger than the voltage level of the high state of the input signal.

The level shifter of FIG. 1 may be configured of a plurality of thin film transistors to perform stable level shifting operations only when the voltage level of the high state of the input signal is greater than or equal to a predetermined voltage level. The thin film transistors perform stable operation at voltages greater than a predetermined voltage level due to high threshold voltage, low field effect mobility (μ), or large subthreshold swing. Therefore, when the voltage level of the high state of the input signal is less than or equal to the predetermined voltage level, the NMOS transistor may not be sufficiently turned on so that the input signal may not be inverted. When the input signal is not inverted, the output signal OUT of the level shifter may remain in a high state or a low state, or the voltage level of the high state of the output signal OUT may be smaller than the power supply voltage. In addition, there is a problem that the level shifting operation is changed according to the threshold voltage, field effect mobility, or deviation of the subthreshold swing of the plurality of thin film transistors.

The level shifter of the liquid crystal display disclosed in U.S. Patent No. 6,404,230 applies the input signal and the inverted signal of the input signal separately to level shift the input signal, but the wiring for transmitting the input signal and the wiring for inverting the input signal. Since this is required separately, the area occupied by the level shifter increases, and the number of output terminals of the timing controller increases.

Although the level shifter of the liquid crystal display disclosed in Korean Patent Laid-Open Publication No. 2003-0051920 applies a separate input signal and a reference voltage to level shift the input signal, the wiring to which the reference voltage is transmitted is different from the wiring to which another voltage signal is transmitted. There is a problem that may cause a malfunction because the coupling (coupling) does not deliver a stable reference voltage.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a single input level shifter that performs a stable level shifting operation without increasing an area and performs a stable level shifting operation even with a characteristic variation of a thin film transistor constituting a level shifter. It is.

Another object of the present invention is to provide a liquid crystal display using the single input level shifter.

A single input level shifter according to the present invention for achieving the above technical problem is an intermediate voltage signal providing unit for providing an intermediate voltage signal between the magnitude of the power supply voltage and the voltage of the input signal, the intermediate voltage receiving the intermediate voltage signal An inverting unit providing an inverted signal of the signal and a voltage signal comparing unit comparing the voltage magnitude of the intermediate voltage signal with the voltage magnitude of the inverted signal of the intermediate voltage signal and providing the power supply voltage or the ground voltage according to a comparison result. do.

According to another aspect of the present invention, there is provided a liquid crystal display device including a plurality of gate lines transferring scan signals, a plurality of gate lines transferring corresponding gray voltages according to image data signals, and being insulated from and intersecting the plurality of gate lines. A display unit including a plurality of pixels arranged in a matrix form having a data line of and a switching element connected to the gate line and the data line in an area surrounded by the gate line and the data line, respectively; A gate driver providing the scan signal, a data driver providing the gray voltage to the data line, a timing controller providing a logic signal, and a single input level shifting the logic signal to the gate driver or the data driver Level shifter The single input level shifter may include an intermediate voltage signal providing unit providing an intermediate voltage signal between a power supply voltage magnitude and an input signal voltage magnitude, and receiving the intermediate voltage signal to provide an inverted signal of the intermediate voltage signal. And a voltage signal comparison unit comparing the voltage level of the butting unit and the voltage level of the inverted signal of the intermediate voltage signal to provide the power supply voltage or the ground voltage according to a comparison result.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments completely cover the scope of the invention to those skilled in the art to which the present invention pertains. It is provided to inform the disclosure that the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

2 is a block diagram of a liquid crystal display according to the present invention. A liquid crystal display according to the present invention will be described with reference to FIG. 2. The liquid crystal display according to the present invention includes a liquid crystal panel 100 and a timing controller 210.

The single input level shifter 110 and the display unit 120 are integrated in the liquid crystal panel 100. The gate driver 220 and the data driver 230 are mounted on the liquid crystal panel 100 in a chip on glass (COG) method. Of course, the present invention is not limited thereto, and the gate driver 220 or the data driver 230 may not be formed inside the liquid crystal panel 100, but may be equally applied to a liquid crystal display device mounted on a PCB, a flexible film, or the like. have.

The display unit 120 may include a plurality of gate lines that transmit scan signals, a plurality of data lines that transmit corresponding gray voltages according to image data signals, and are insulated from and cross the plurality of gate lines, and the gate lines and data lines. And a plurality of pixels arranged in a matrix form having switching elements connected to the gate line and the data line, respectively, in an area surrounded by the gate line.

The gate driver 220 provides the scan signal to the gate line, the data driver 230 provides the gray voltage to the data line, and the timing controller 210 provides a logic signal. The single input level shifter 110 level-shifts the logic signal to the gate driver 220 or the data driver 230. The logic signal includes all digital signals for driving the gate driver 220 or the data driver 230 including a clock signal and a start signal.

Next, the single input level shifter 110 of the liquid crystal display according to the exemplary embodiment of the present invention will be described in more detail with reference to FIG. 3. 3 is a circuit diagram of a single input level shifter 110 of a liquid crystal display according to an exemplary embodiment of the present invention. The single input level shifter 110 of the liquid crystal display according to the exemplary embodiment of the present invention includes an intermediate voltage signal providing unit 10, an inverting unit 20, and a voltage signal comparing unit 30.

The intermediate voltage signal providing unit 10 provides an intermediate voltage signal between the magnitude of the power supply voltage VDD and the voltage of the input signal IN, and the inverting unit 20 receives the intermediate voltage signal. The inverted signal of the intermediate voltage signal is provided, and the voltage signal comparator 30 compares the voltage magnitude of the intermediate voltage signal with the voltage magnitude of the inverted signal of the intermediate voltage signal and according to a comparison result, the power supply voltage VDD. Or provide a ground voltage (GND).

The intermediate voltage signal providing unit 10 transfers a predetermined current to the first current source 11 and the input signal IN which deliver a predetermined current to the output node N10 of the intermediate voltage signal. A second current source 12. The voltage magnitude of the intermediate voltage signal output to the output node N10 is determined by the ratio of the current delivered by the first current source 11 and the current delivered by the second current source.

That is, when the amount of current delivered by the second current source to the input signal IN is greater than the amount of current delivered by the first current source 11 to the output node N10, the output node ( Since the charge goes out to the input signal IN terminal more than the charge transferred to N10, the voltage level of the intermediate voltage signal output to the output node N10 is equal to the power supply voltage VDD and the input signal ( IN) becomes smaller than the middle of the difference in magnitude.

On the contrary, when the amount of current transmitted by the second current source 12 to the input signal IN is smaller than the amount of current delivered by the first current source 11 to the output node N10, the Since the charge exiting to the input signal IN is smaller than the charge transmitted to the output node N10, the voltage level of the intermediate voltage signal output to the output node N10 is equal to the power supply voltage VDD and the input signal ( IN is greater than the middle of the difference in the magnitude of the voltage.

The first current source 11 has a PMOS having a source connected to a power supply voltage VDD, a drain connected to an output node N10 of the intermediate voltage signal, and a gate connected to a ground voltage GND. It is preferable that it is a transistor MP11.

The ground voltage GND terminal is connected to the gate of the PMOS transistor MP11, the ground voltage GND is transferred to the gate of the PMOS transistor MP11, and the power supply voltage VDD is supplied to the source of the PMOS transistor MP11. Since the terminal is connected and the power supply voltage VDD is transmitted to the source of the PMOS transistor MP11, the PMOS transistor MP11 is always turned on. Therefore, the PMOS transistor MP11 may be used as a current source for transmitting a constant current to the output node N10 of the intermediate voltage signal. The amount of current provided by the PMOS transistor MP11 is equal to the ratio W / L of the width W and the length L of the PMOS transistor MP11 and the power supply voltage VDD and the output node. It can be adjusted by the voltage difference of N10).

The second current source 12 has a drain connected to an output node N10 of the intermediate voltage signal, a source connected to the input signal IN, and a gate connected to a power supply voltage VDD. It is preferable that it is a MOS transistor MN11.

A power supply voltage VDD terminal is connected to a gate of the NMOS transistor MN11, a power supply voltage VDD is transferred to a gate of the NMOS transistor MN11, and the output node N10 is applied to a drain of the NMOS transistor MN11. ) Is connected to transfer the voltage of the output node N10 to the drain of the NMOS transistor MN11, so that the NMOS transistor MN11 is always turned on. Therefore, the NMOS transistor MN11 may be used as a current supply source for transmitting a constant current to the input signal IN terminal. The amount of current provided by the NMOS transistor MN11 is a ratio W / L of the width W and the length L of the NMOS transistor MN11 and the voltage and the input of the output node N10. It can be adjusted by the voltage difference of the signal IN.

When the input signal IN is input as a low voltage signal, the voltage difference between the voltage of the output node N10 and the input signal IN is greater than when the input signal IN is input as a high voltage signal. Therefore, since a larger amount of current is provided to the input signal IN, the magnitude of the voltage of the output node N10 is larger than the case where the input signal IN is input as a high voltage signal.

Therefore, the intermediate voltage signal providing unit 10 provides a voltage signal including a predetermined DC voltage component while maintaining a difference between voltage levels of the high state and the low state of the input signal IN as the intermediate voltage signal. The voltage level in the high state of the intermediate voltage signal is smaller than the power supply voltage VDD, and the voltage level in the low state of the intermediate voltage signal is greater than the ground voltage GND. The size of the predetermined DC voltage component may be adjusted by the ratio of the width and length of the PMOS transistor MP11 and the ratio of the width and length of the NMOS transistor MN11.

The PMOS transistor MP11 and the NMOS transistor MN11 are preferably formed of low temperature polycrystalline silicon (LTPS). Low-temperature polysilicon is crystallized by irradiating the laser to amorphous silicon and has a very high field effect mobility compared to amorphous silicon, and is easily integrated and formed when the display unit 120 is formed inside the liquid crystal panel 100. This makes it possible to reduce production costs while reducing production costs.

When the intermediate voltage signal providing unit 10 is configured using two resistors, the voltage difference between the high state and the low state of the input signal IN is reduced by two resistance ratios, so that the intermediate voltage provided to the inverting unit 20 is provided. Not suitable as a signal

For example, when the voltage difference between the high state and the low state of the input signal IN is 3 V, when the intermediate voltage signal providing unit 10 is composed of two resistors having the same resistance, the power supply voltage VDD and the high state The half value of the voltage difference of the input signal IN is the intermediate voltage signal in the high state, and the half value of the voltage difference of the power supply voltage VDD and the input signal IN in the low state is the middle of the low state. As a result, the voltage difference between the high and low states of the intermediate voltage signal is reduced to 1.5V.

The intermediate voltage signal is transmitted to the inverting unit 20, and the inverting unit 20 provides an inversion signal of the intermediate voltage signal. As shown in FIG. 3, the inverting unit 20 includes a compensation MOS including a PMOS transistor MP21 and an NMOS transistor MN21 between a power supply voltage VDD terminal and a ground voltage GND terminal. ; CMOS) transistors are preferred.

When the intermediate voltage signal in the low state is transmitted to the inverting unit 20, the PMOS transistor MP21 is turned on so that the power supply voltage VDD is transferred to the output node N20 of the inverting unit. When the voltage signal is transmitted to the inverting unit 20, the NMOS transistor MN21 is turned on and the ground voltage GND is transmitted to the output node N20 of the inverting unit, thereby providing an inversion signal of the intermediate voltage signal. .

At this time, the voltage value of the intermediate voltage signal in the high state is larger than the voltage value of the input signal IN in the high state, so the threshold voltage or subthreshold swing of the NMOS transistor MN21 is high. The NMOS transistor MN21 can be sufficiently turned on even if this is high or the field effect mobility μ is low.

Therefore, even when the voltage value of the high state input signal IN decreases, the NMOS transistor MN21 can be sufficiently turned on, thereby providing the inversion of the intermediate voltage signal to the output node N20 of the inverting unit. In addition, even if there is a deviation in the threshold voltage, subthreshold swing, or field effect mobility of the NMOS transistor MN21, the NMOS transistor MN21 may be sufficiently turned on.

The voltage difference between the high state and the low state of the intermediate voltage signal is greater than the voltage difference between the high state and the low state of the input signal IN. However, when the intermediate voltage signal in the low state is input, the low voltage of the intermediate voltage signal is larger than that of the ground voltage GND, so the NMOS transistor MN21 is not surely turned off. The voltage of becomes smaller than the power supply voltage VDD.

The PMOS transistor MP21 and the NMOS transistor MN21 are preferably formed of low temperature polycrystalline silicon (LTPS). As described above, low-temperature polysilicon is crystallized by irradiating a laser to amorphous silicon, and has a very high field effect mobility compared to amorphous silicon, and is easy to integrate and form inside the liquid crystal panel 100. This makes it possible to reduce production costs while reducing production costs.

The inverted signal of the intermediate voltage signal and the intermediate voltage signal is transmitted to the voltage signal comparator 30 so that the voltage signal comparator 30 is an output signal OUT of the single input level shifter, which is a power supply voltage VDD or a ground voltage. Provide (GND). As illustrated in FIG. 3, the voltage signal comparison unit 30 includes a current mirror and two NMOS transistors MN31 and MN32.

The current mirror is connected between a power supply voltage VDD terminal and a common node N30 and between a PMOS transistor MP31 and a power supply voltage VDD terminal having a gate and a drain connected in common, and a node of an output signal OUT. And a PMOS transistor MP32 connected to the gate of the PMOS transistor MP31.

The NMOS transistor MN31 is connected between the common node N30 and the output node N10 of the intermediate voltage signal part, and the gate is connected to the output node N20 of the inverting part. The NMOS transistor MN32 is connected between the node of the output signal OUT and the output node N20 of the inverting unit, and the gate is connected to the output node N10 of the intermediate voltage signal.

The voltage signal comparison unit 30 may amplify the difference between the output signal of the inverting unit 20 applied to the gate of the NMOS transistor MN31 and the intermediate voltage signal applied to the gate of the NMOS transistor MN32 again. Since there is no need, it is possible to eliminate the NMOS transistor functioning as the current sink in the conventional differential amplifier. Therefore, although the conventional differential amplifier is composed of two PMOS transistors and three NMOS transistors, the voltage signal comparator 30 includes two PMOS transistors MP31 and MP32 and two NMOS transistors MN31, MN32). Therefore, the voltage signal comparison unit 30 can reduce the area efficiently.

When the input signal IN in the low state is applied to the input signal terminal, the intermediate voltage signal providing unit 10 provides the inverting unit 20 with the intermediate voltage signal in the low state. Provide an inversion signal of the intermediate voltage signal. Accordingly, since the inverted signal of the high voltage is transmitted to the gate of the NMOS transistor MN31 and the low voltage of the intermediate voltage signal is transmitted to the gate of the NMOS transistor MN32, only the NMOS transistor MN31 is turned on. . When the NMOS transistor MN31 is turned on, the voltage value of the common node N30 becomes low, and the PMOS transistor MP32 is turned on.

In particular, since the voltage of the high state of the inversion signal of the intermediate voltage signal larger than the voltage value of the high state of the intermediate voltage signal is transmitted to the gate of the NMOS transistor MN31, the voltage value of the common node N30 is set to the low state of the intermediate voltage signal. It is lowered to the voltage value of. Therefore, the PMOS transistor MP32 is reliably turned on to transmit the power supply voltage VDD to the node of the output signal OUT.

When the input signal IN of the high state is applied to the input signal terminal, the intermediate voltage signal providing unit 10 provides the high voltage of the intermediate voltage signal to the inverting unit 20. Provide an inversion signal of the intermediate voltage signal. Therefore, since the inverted signal of the low voltage of the intermediate voltage signal is transmitted to the gate of the NMOS transistor MN31 and the high voltage of the intermediate voltage signal is transmitted to the gate of the NMOS transistor MN32, only the NMOS transistor MN32 is turned on. . When the NMOS transistor MN32 is turned on, the voltage of the node of the output signal OUT is transferred to the low state of the inverted signal of the intermediate voltage signal. Therefore, the voltage at the node of the output signal OUT becomes the ground voltage GND.

As a result, the voltage signal comparison unit 30 provides the power supply voltage VDD as the output signal OUT when the input signal IN in the low state is applied, and outputs the output signal OUT when the input signal IN in the high state is applied. Provides the ground voltage (GND).

It is preferable that the plurality of PMOS transistors MP31 and MP32 and the plurality of NMOS transistors MN31 and MN32 are formed of low temperature polycrystalline silicon (LTPS). As described above, low-temperature polysilicon is crystallized by irradiating a laser to amorphous silicon, and has a very high field effect mobility compared to amorphous silicon, and is easy to integrate and form inside the liquid crystal panel 100. This makes it possible to reduce production costs while reducing production costs.

Since the single input level shifter 110 according to the present invention does not need a separate inverted signal of the input signal IN, a separate wire for transferring the inverted signal of the input signal IN is not required, and thus the level shifter 110 is required. ) Does not increase, and the number of output terminals of the timing controller 210 does not increase. In addition, since a separate reference voltage is not required, malfunctions that may be caused by the coupling of the wiring to which the reference voltage is transmitted with the wiring to transmit another voltage signal are not generated.

4A and 4B are waveform diagrams of the main part signals of the single input level shifter of FIG. 3, wherein the power supply voltage VDD is 12V, the ground voltage GND is 0V, and the input signals in are 3.3V and 0V. In the case of the pulse signal between the results of the simulation using the SPICE for the single input level shifter 110 of FIG.

When the input signal in is applied as shown in FIG. 4A, as shown in FIG. 4B, the intermediate voltage signal providing unit 10 is an intermediate voltage signal N10, which is 4.5 V in a form not inverted with the input signal in. And a pulse signal between 8 V and the inverting unit 20 provides a pulse signal between 0.5 V and 8 V in an inverted form with the input signal in as the inverted signal signal N20 of the intermediate voltage signal. In addition, it can be seen that the voltage signal comparator 30 provides a pulse signal between 0.5 V and 11.5 V in an inverted form from the input signal in as the output signal out.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the present invention made as described above, it is possible to perform a stable level shifting operation without increasing the area, and stable level shifting operation even with respect to a characteristic (eg, threshold voltage) variation of the thin film transistor constituting the level shifter. It is possible to provide a single input level shifter for performing the above and a liquid crystal display using the same.

1 is a circuit diagram of a level shifter of a conventional liquid crystal display.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a circuit diagram of a single input level shifter of the liquid crystal display according to the exemplary embodiment of the present invention.

4A and 4B are waveform diagrams of main part signals of the single input level shifter of FIG.

(Explanation of symbols for the main parts of the drawing)

10: medium voltage signal providing unit

20: inverting part

30: voltage signal comparator

100: liquid crystal panel

110: level shifter

120: display unit

210: timing controller

220: gate driver

230: data driver

Claims (13)

An intermediate voltage signal providing unit providing an intermediate voltage signal between the power supply voltage magnitude and the voltage magnitude of the input signal; An inverting unit receiving the intermediate voltage signal and providing an inverted signal of the intermediate voltage signal; And And a voltage signal comparator for comparing the voltage magnitude of the intermediate voltage signal with the voltage magnitude of the inverted signal of the intermediate voltage signal to provide the power supply voltage or the ground voltage according to a comparison result. In claim 1, The intermediate voltage signal providing unit includes a first current source for transmitting a predetermined current to an output node of the intermediate voltage signal and a second current source for transmitting a predetermined current to an input signal terminal. The voltage magnitude of the intermediate voltage signal is adjusted by the ratio of the current delivered by the first current source and the current delivered by the second current source. In claim 2, And the first current source is a PMOS transistor having a source connected to a power supply voltage terminal, a drain connected to an output node of the intermediate voltage signal, and a gate connected to a ground voltage terminal. In claim 2, And the second current source is an NMOS transistor having a drain connected to an output node of the intermediate voltage signal, a source connected to the input signal terminal, and a gate connected to the power supply voltage terminal. . The method of claim 3 or 4, And said PMOS transistor or said NMOS transistor is formed of polysilicon. In claim 1, The voltage signal comparison unit includes a first PMOS transistor having a gate and a drain connected in common, a second PMOS transistor having a gate connected to a gate of the first PMOS transistor, a drain of the first PMOS transistor, and the A gate connected between an output node of an intermediate voltage signal part and a gate connected between an output node of the first NMOS transistor and the second PMOS transistor connected to an output node of the inverting part and an output node of the inverting part; Is coupled to an output node of the intermediate voltage signal. A plurality of gate lines transferring scan signals, a plurality of data lines transferring corresponding gray voltages according to an image data signal, and insulated from and intersecting the plurality of gate lines, and regions surrounded by the gate lines and the data lines, respectively. A display unit including a plurality of pixels arranged in a matrix form having a gate line and a switching element connected to the data line; A gate driver providing the scan signal to the gate line; A data driver providing the gray voltage to the data line; A timing controller for providing a logic signal; And And a single input level shifter for level shifting the logic signal and transferring the logic signal to the gate driver or the data driver. The single input level shifter may include an intermediate voltage signal providing unit providing an intermediate voltage signal between a power supply voltage magnitude and an input signal voltage magnitude, an inverting unit receiving the intermediate voltage signal and providing an inverted signal of the intermediate voltage signal; And a voltage signal comparator for comparing the voltage magnitude of the intermediate voltage signal with the voltage magnitude of the inverted signal of the intermediate voltage signal to provide the power voltage or the ground voltage according to a comparison result. In claim 7, And the display unit and the single input level shifter are integrally formed in a panel of the liquid crystal display. In claim 7, The intermediate voltage signal providing unit includes a first current source for transmitting a predetermined current to an output node of the intermediate voltage signal and a second current source for transmitting a predetermined current to an input signal terminal. The voltage level of the intermediate voltage signal is controlled by the ratio of the current delivered by the first current source and the current delivered by the second current source. In claim 9, And the first current source is a PMOS transistor having a source connected to a power supply voltage terminal, a drain connected to an output node of the intermediate voltage signal, and a gate connected to a ground voltage terminal. In claim 9, And the second current source is an NMOS transistor having a drain connected to an output node of the intermediate voltage signal, a source connected to the input signal terminal, and a gate connected to the power supply voltage terminal. The method according to any one of claims 10 or 11, The PMOS transistor or the NMOS transistor is formed of polysilicon. In claim 7, The voltage signal comparison unit includes a first PMOS transistor having a gate and a drain connected in common, a second PMOS transistor having a gate connected to a gate of the first PMOS transistor, a drain of the first PMOS transistor, and the A gate connected between an output node of an intermediate voltage signal part and a gate connected between an output node of the first NMOS transistor and the second PMOS transistor connected to an output node of the inverting part and an output node of the inverting part; Is connected to an output node of the intermediate voltage signal.