KR20050075866A - Plasma display panel - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly to a plasma display panel designed to reduce jitter in an address period.

The plasma display panel is driven by a single scan driving method in which the scan pulses applied to the plurality of scan electrodes formed on the display area of the upper substrate are different from each other in the plurality of scan electrodes. A plasma display panel including a discharge gas including Xe), wherein the plurality of sustain electrodes formed in parallel with the plurality of scan electrodes formed on the upper substrate, the upper dielectric layer formed to cover the plurality of scan electrodes and the sustain electrodes And a top plate having a protective film formed to cover the upper dielectric layer; A lower substrate having a lower substrate facing the upper substrate, an address electrode formed on the lower substrate, a lower dielectric layer formed to cover the address electrode, a partition formed on the lower dielectric layer, and a phosphor layer formed on the lower dielectric layer and the partition wall; The protective film includes magnesium oxide (MgO) as a main component and 20 ppm to 500 ppm of silicon (Si) is added.

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a protective film of a plasma display panel and a method of manufacturing the same, and a plasma display panel having the same to reduce jitter in an address period.

Plasma Display Panel (hereinafter referred to as "PDP") is helium (He) + xenon (Xe), neon (Ne) + xenon (Xe), helium (He) + xenon (Xe) + neon (Ne) The image is displayed by exciting the phosphor by using ultraviolet rays generated when an inert mixed gas such as the above is discharged. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP includes a sustain electrode pair including a scan electrode (Y) and a sustain electrode (Z) formed on the upper substrate 1, and a lower portion perpendicular to the sustain electrode pair. An address electrode X formed on the substrate 2 is provided.

Each of the scan electrode Y and the sustain electrode Z is composed of a transparent electrode and a metal bus electrode formed thereon. An upper dielectric layer 6 and an MgO passivation layer 7 are stacked on the upper substrate 1 on which the scan electrode Y and the sustain electrode Z are formed. The MgO protective film 7 serves to protect the dielectric layer 6 and the electrodes Y and Z from sputtering of particles generated by the discharge, and to increase the emission efficiency of secondary electrons.

The lower dielectric layer 4 is formed on the lower substrate 2 on which the address electrode X is formed to cover the address electrode X. FIG. A partition 3 is formed vertically on the lower dielectric layer 4. Phosphors 5 are formed on the surfaces of the lower dielectric layers 4 and the partition walls 3.

The upper substrate 1 and the lower substrate 2 are bonded by a seal (not shown). An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space provided between the upper substrate 1, the lower substrate 2, and the partition wall 3.

The PDP adopts a method in which time-division driving is performed by dividing one frame into several subfields having different number of emission times, and addressing and display are separated (ADS). Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. The reset period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling ramp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 and 4 illustrate driving waveforms of the PDP shown in FIG. 1.

Referring to Fig. 3, the PDP is driven by dividing into a reset period, an address period and a sustain period.

In the reset period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. Following the setup discharge, a falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is simultaneously applied to the scan electrodes Y. Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The sustain electrode Z is supplied with a positive DC voltage Zdc during the set down period and the address period. The DC voltage Zdc causes a setdown discharge between the sustain electrode Z and the scan electrode Y in the setdown period, and a large discharge occurs between the scan electrode Y and the sustain electrode Z in the address period. The voltage difference between the sustain electrode Z and the scan electrode Y or between the sustain electrode Z and the address electrode X is set.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, square waves ers1 and ers2 having a small pulse width and ramp waveforms ers3 having a small voltage level are supplied to the sustain electrode Z as an erase signal for erasing charge in the cell. When the erase signals ers1, ers2, and ers3 are supplied into the cell, erase discharge occurs and the wall charges generated and sustained by the sustain discharge are erased.

The driving waveforms shown in FIG. 4 are square waves (rst1, rst2, and rst3) in which the initialization waveforms supplied in the reset period are alternately supplied to the scan electrode Y and the sustain electrode Z, compared to the driving waveforms shown in FIG. And rise ramp waveform (Ramp-up). The signals supplied to the electrodes X, Y, and Z during the address period and the sustain period are substantially the same as those shown in FIG.

In such a PDP, high definition, high brightness, high contrast ratio, low contour noise, and the like are required to realize high quality image quality. In addition, in order to realize high quality image quality in the PDP, an appropriate address period must be secured in the ADS driving method. As the PDP develops to high definition / high resolution, the number of lines to be scanned increases, so that the address period becomes longer and the sustain period becomes difficult. For example, there are 480 scan lines, 3μs scan time per line, single scan method that scans sequentially from the first scan line to the last scan line at once In the case of driving divided into three subfields, an address period required in one frame takes 480 x 3 mu s 8 = 13 ms or more. Therefore, the time that can be allocated to the sustain period within one frame is absolutely short of 16.67ms-13ms. In order to allocate more of the insufficient sustain period as described above, the scan time should be reduced, but the address period is difficult to reduce because the width of the scan pulse is increased in consideration of jitter during address discharge. Jitter is a discharge delay time generated during address discharge, which is slightly different in every subfield, and has a certain range during driving. Since the scan pulse contains these jitter values, the pulse width becomes longer. Therefore, the larger the jitter value, the longer the address period becomes, so that it is difficult to realize high quality image quality.

The jitter value tends to increase as the PDP temperature or ambient temperature decreases. For this reason, since the address discharge is unstable at a low temperature, the cell can not be selected, that is, miss writing occurs and black noise appears in the display image.

On the other hand, Japanese Patent Application Laid-Open No. 2001-135238 increases the xenon (Xe) content to 5% or more in the discharge gas enclosed in the PDP, so that the driving voltage is higher than that of the conventional low density Xe panel, but the luminance is high. We have proposed a PDP that can further increase. However, in the high density Xe panel, as the Xe content increases, the jitter value of the address period increases. Therefore, it is difficult to implement a high density Xe panel due to the jitter value of the address period.

The factor which has the greatest influence on the jitter value of the address period is the secondary electron emission characteristic of the protective film 7. As the secondary electron emission efficiency of the passivation layer 7 is higher, jitter is reduced and the pulse width of the scan pulse is reduced by the reduced jitter, so that the address period can be shortened.

Accordingly, it is an object of the present invention to provide a PDP that reduces the jitter value of an address period.

In order to achieve the above object, the PDP according to the present invention is driven by a single scan driving method in which a scan pulse applied to a plurality of scan electrodes formed on the display area of the upper substrate is applied at each of the plurality of scan electrodes, A PDP containing 5% or more of xenon (Xe) in a discharge space, comprising: a plurality of sustain electrodes, the plurality of scan electrodes and the sustain electrodes formed in parallel with the plurality of scan electrodes formed on the upper substrate; An upper plate having an upper dielectric layer formed to cover the upper dielectric layer and a protective film formed to cover the upper dielectric layer; A lower substrate having a lower substrate facing the upper substrate, an address electrode formed on the lower substrate, a lower dielectric layer formed to cover the address electrode, a partition formed on the lower dielectric layer, and a phosphor layer formed on the lower dielectric layer and the partition wall; Equipped.

The protective film contains magnesium oxide (MgO) as a main component and 20 ppm to 500 ppm of silicon (Si) is added.

The silicon (Si) is added in an amount of approximately 20 ppm to 300 ppm.

The protective film includes 50 ppm or less calcium (Ca), 50 ppm or less iron (Fe), 250 ppm or less aluminum (Al), 5 ppm or less nickel (Ni), 5 ppm or less sodium (Na), or 5 ppm or less potassium (K). This is further added.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 and 6.

Referring to FIG. 5, the protective film of the PDP according to the embodiment of the present invention contains magnesium oxide (MgO) as a main component and contains a small amount of silicon (Si) as a concentration set within a range in which jitter is minimized. In Fig. 5, the vertical axis represents jitter μs of the address period, and the horizontal axis represents content wt.ppm of silicon (Si).

The PDP according to the present invention is driven by a single scan method in which the number of driving circuits is not increased and the panel is not dividedly driven using the protective film added with silicon.

The protective film according to the present invention is formed on the upper surface of the PDP by vacuum deposition such as chemical vapor deposition (CVD), E-beam, ion-plating, sputtering, or the like.

When forming the protective film according to the present invention using a vacuum deposition method, there may be a variety of methods for adding a small amount of silicon (Si). By adding a small amount of silicon (Si) to the raw materials (source matrial, target, etc.) used for vacuum deposition, a protective film may be deposited using a single source, and conventional magnesium oxide (MgO ) And silicon (Si) may be used as a source at the same time to add silicon (Si) to the protective film. At this time, the content of silicon (Si) can be adjusted by adjusting the power (power) applied to the silicon source (Si source). Here, the source material is produced by refining seawater or magnesium ore having magnesium oxide (MgO) of 99.5 wt% or more, wherein calcium (Ca) of 300 ppm or less, iron (Fe) of 50 ppm or less, aluminum (Al) of 250 ppm or less 5 ppm or less nickel (Ni), 5 ppm or less sodium (Na), 5 ppm or less potassium (K) may be included as impurities, and 5000 ppm or less silicon (Si) is added as shown in Table 1 below. In other words, the source material contains a small amount of silicon (Si) to improve the secondary electron emission characteristics of the protective film as shown in Table 1 below.

MgO 99.5wt%-99.99999wt% Si 5000 ppm or less

The MgO protective film is deposited on the upper substrate of the PDP on which the sustain electrode pairs Y and Z and the dielectric layer are formed using the protective film deposition method. The protective film formed on the upper substrate of the PDP by the deposition process and a small amount of silicon (Si) is added to improve the secondary electron emission characteristics of magnesium oxide (MgO) and the protective film close to 100 wt% as shown in Table 2 below. A small amount of silicon (Si) is contained in 500 ppm or less.

MgO 99.5wt%-99.99999wt% Si 500 ppm or less

Further, the protective film formed on the PDP has 50 ppm or less of calcium (Ca), 50 ppm or less of iron (Fe), 250 ppm or less of aluminum (Al), 5 ppm or less of nickel (Ni), 5 ppm or less of sodium (Na), or 5 ppm or less. Potassium (K) may be included.

In Tables 1 and 2, the decrease in the content of silicon (Si) in the source material and the protective film actually formed on the PDP is due to the adjustment of the process parameters during the deposition process. For example, when the pressure in the deposition apparatus is increased or the distance between the substrate and the source material of the PDP is increased, the silicon content of the protective film formed on the substrate of the PDP is reduced than the silicon content in the source material.

Silicon (Si) is added to magnesium oxide (MgO) in a small amount to compensate for the secondary electron emission efficiency of the protective film in which oxygen (O) falls by oxygen vacancy defects and impurities in the crystal of magnesium oxide (MgO). . In other words, when the protective film is formed by vacuum deposition, crystal defects that are inevitably involved in the process and impurities introduced from the source material, that is, calcium (Ca), iron (Fe), aluminum (Al), and nickel (Ni). ), Sodium (Na), potassium (K) and the like act as a factor deteriorating the electron emission characteristics. Silicon (Si) cancels the jitter of the address period by canceling the secondary electron emission characteristic deteriorated due to crystal defects and impurities.

As the silicon (Si) is added, the jitter value of the address period is reduced as shown in FIG. 5, and when the content of silicon (Si) becomes larger than a predetermined value, the jitter tends to increase. Therefore, silicon (Si) is preferably added to the protective film in a content within a range in which jitter is minimized. To this end, silicon (Si) may vary depending on the content of other impurities and deposition conditions, but is added in an amount of about 20 ppm to about 300 ppm in the protective film as an optimum content.

The jitter characteristic shown in FIG. 5 was obtained by applying a driving waveform to the PDP and measuring an optical waveform generated when addressing in one cell. The measurement pattern used in this experiment was a low gradation line pattern to minimize the priming effect.

According to the results of dozens of experiments each time changing the type of discharge gas encapsulated in the PDP, the secondary electron emission characteristics of the protective film containing silicon (Si) were improved regardless of the type of discharge gas.

FIG. 6 shows an experimental result of jitter characteristics of a protective film added with silicon (Si) in a PDP in which a high-density Xe discharge gas containing 5% or more of xenon (Xe) is filled.

As can be seen from Fig. 6, when the protective film of the PDP in which the high-density Xe discharge gas is encapsulated, magnesium oxide (MgO) is added as the main component and silicon (Si) is added at 300 ppm or less, the jitter of the address period is approximately 0.6 µs. Within a very small level.

Therefore, when the protective film according to the present invention is applied to the high-density Xe panel, high brightness and high speed driving are possible, as well as high resolution can be realized and external temperature response can be increased.

As described above, the PDP according to the present invention reduces the jitter of the address period by adding silicon to the protective film to improve the secondary electron emission characteristic of the protective film. As a result, according to the PDP according to the present invention, since address discharge of the PDP occurs stably in a short time, the address operation is stable and the efficiency is increased even in a low temperature environment. Furthermore, according to the PDP according to the present invention, as the address period is reduced, the sustain period is sufficiently secured, and the number of subfields can be increased to reduce the noise, so that high quality image quality can be realized in the PDP.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform for driving a conventional PDP.

4 is a waveform diagram showing another drive waveform for driving a conventional PDP.

5 is a characteristic diagram illustrating a change in jitter value according to the content of silicon (Si) in the protective film of the plasma display panel according to the embodiment of the present invention.

FIG. 6 is a characteristic diagram illustrating a change in jitter value according to contents of xenon (Xe) and silicon (Si) in a protective film of a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1: upper substrate 2: lower substrate

3: bulkhead 4,6: dielectric layer

5: phosphor 7: protective film

X: address electrode Y: scan electrode

Z: sustain electrode

Claims (3)

An application point of the scan pulse applied to the plurality of scan electrodes formed on the display area of the upper substrate is driven by a different single scan driving method on each of the plurality of scan electrodes, and includes 5% or more of xenon (Xe) in the discharge space. In a plasma display panel in which discharge gas is sealed, An upper plate having a plurality of sustain electrodes formed parallel to the plurality of scan electrodes formed on the upper substrate, an upper dielectric layer formed to cover the plurality of scan electrodes and the sustain electrodes, and a protective film formed to cover the upper dielectric layers; A lower substrate having a lower substrate facing the upper substrate, an address electrode formed on the lower substrate, a lower dielectric layer formed to cover the address electrode, a partition formed on the lower dielectric layer, and a phosphor layer formed on the lower dielectric layer and the partition wall; Equipped, The protective film is a plasma display panel comprising magnesium oxide (MgO) as a main component and silicon (Si) 20ppm ~ 500ppm added. The method of claim 1, And the silicon (Si) is added in an amount of approximately 20 ppm to 300 ppm. The method of claim 1, The protective film includes 50 ppm or less calcium (Ca), 50 ppm or less iron (Fe), 250 ppm or less aluminum (Al), 5 ppm or less nickel (Ni), 5 ppm or less sodium (Na), or 5 ppm or less potassium (K). The plasma display panel further comprises.