KR20050073902A - Semiconductor memory module and method of testing operating margin thereof, and semiconductor memory apparatus - Google Patents

Abstract

The present invention discloses a semiconductor memory module, a test method thereof, and a semiconductor memory device. The semiconductor memory module of the present invention includes a circuit board having a plurality of external input / output terminals, an interface circuit provided on the circuit board, a plurality of semiconductor memory chips, and a nonvolatile memory chip. The interface circuit interfaces the signal transmission between the plurality of external input terminals and the internal circuit. The plurality of semiconductor memory chips are connected to an interface circuit and input an external address signal having the mode setting information to decode the input mode setting information to generate a mode setting control signal. In the test mode, the mode setting control signal is provided to the test operation circuit unit. The nonvolatile memory chip stores the initial value to provide initial values of the semiconductor memory chips to the outside through the interface circuit during initial system boot. Therefore, in the present invention, various tests can be performed by mode setting the chips in the memory module, thereby improving test efficiency in the test process.

Description

Semiconductor Memory Module and Method of Testing Operating Margin, and Semiconductor Memory Apparatus

The present invention relates to a semiconductor memory module, a test method, and a semiconductor memory device capable of operating margin testing, and more particularly, to a semiconductor memory module and a test method capable of testing an operation margin by allowing a mode setting to be programmed during a test operation. ,

In order to improve the performance of the central processing unit of the computer system and to process a large amount of data at high speed, large-capacity main memories of high speed operation are used. In particular, as a main memory of a personal computer system, a memory module including a double data rate (DDR) or rambus DRAM chips as one package is commercially provided.

The memory module configures a plurality of unit memory chips on a circuit board and mounts the configured module to a motherboard to connect to the system.

The computer system requires that initialization information for initializing the memory module is stored in the memory module in order to speed up the system booting operation.

In order for a computer system to boot properly, it must be able to recognize the configuration of the memory modules. Parallel Presence Detect (PPD) is a general method of using registers to connect necessary information. It is mainly used in SIMM (Single-In-Line Memory Module) type modules and Serial Presence Detect (SPD). -Serial Configuration Recognition Device) is a method used by a module of a dual-in-line memory module (DIMM) type and uses EEPROM to store information about the module.

The test range of such a memory module is limited according to the configuration of the unit memory chip. Typically, synchronous DRAMs have a mode register inside the chip and are configured to set to test mode. In other words, the setting in the unit chip is given only the mode setting in which the chip is simply set to the test mode or the normal mode.

However, in the case of configuring such unit chips as modules, data input / output operation margins among the plurality of chips may be different from each other, and there may be a difference in minute operation parameter differences depending on a mounting environment or a module. Therefore, after module mounting, these parameters had to be measured to find the most appropriate margin for the entire module and to set each memory chip inside the module. That is, since it is not possible to know which margin is most suitable at the time of producing the first module, a test sample module having various operating margins was manufactured and then tested in a mounted state to find an optimal margin.

However, since each individual memory chip does not have a function for testing an operating margin by changing parameter values in a test mode, a separate test module has to be prepared and tested for each change value, which is expensive.

This process adds time and cost, increasing module production costs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory module and a test method thereof capable of testing an optimal operating margin among a plurality of memory chips in order to solve the problems of the prior art.

Another object of the present invention is to provide a semiconductor memory device capable of programming a plurality of operation margin tests.

In order to achieve the above object, the memory module of the present invention includes a circuit board having a plurality of external input / output terminals, an interface circuit provided on the circuit board, a plurality of semiconductor memory chips, and a recognition unit.

The interface unit interfaces a signal transmission between the memory chips and the input / output terminal. The interface section includes a timing register. Each of the semiconductor memory chips is connected to an interface circuit and inputs an external address signal having mode setting information to decode the input mode setting information to generate a mode setting control signal. In the test mode, the mode setting control signal is provided to the test operation circuit unit. Here, the semiconductor memory chips may be composed of DDR SDRAM or Rambus DRAM, respectively. The recognition unit stores the initial value in order to provide the initial values of the semiconductor memory chips to the outside through the interface circuit during initial system booting. Here, the recognition unit is composed of a serial input / output EEPROM.

The test method of the present invention for achieving the object of the present invention comprises the following steps.

a) mounting a test memory module to the memory test equipment;

b) reading initial value information from the mounted test memory module;

c) initializing the test memory module in response to the read initial value information;

d) providing test mode setting information to the initialized test memory module;

e) setting a plurality of memory chips mounted inside the memory module to a corresponding test mode in response to provided test mode setting information;

f) testing the memory module in the set test mode; And

g) detecting the mode setting information of the optimum operation by repeating steps d to f while changing the test mode setting information provided to the memory module.

In the present invention, the test memory module further includes programming a plurality of memory chips mounted in the test mode by electric fusing.

In order to achieve the above object, the semiconductor memory device of the present invention includes a mode register for inputting and storing an external address signal having mode setting information, and a mode setting connected to the mode register and decoding the mode setting information stored in the mode register. A mode setting decoder for generating a control signal, and a fuse circuit unit which is fused to provide the mode setting control signal to the normal operation circuit unit in the normal mode and to provide the mode setting control signal to the test operation circuit unit in the test mode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This embodiment is described in sufficient detail to enable those skilled in the art to practice the invention.

1 shows a configuration diagram of a semiconductor memory module according to the present invention.

In FIG. 1, the memory module 100 of the present invention is provided by installing an interface unit 120, a plurality of SDRAMs 130, and a recognition unit 140 on a circuit board 110. Specific examples are disclosed in the data manual of the DDR SDRAM Registered Module published by the applicant in August 2003. The circuit board 110 is provided with 184 pin input / output terminals 112 for inputting and outputting data, data strobe signals, address signals, timing signals, power signals, and the like.

The interface unit 120 is composed of an address and a timing register. Input the bank address BA0 ~ BA1, address signals A0 ~ A12, timing signals CS0 ~ CS1, RAS, CAS, CKE0, CKE1, WE, etc., so that the internal chip selection signal, internal bank address signal, internal address signal, internal timing signal, etc. Occurs.

The SDRAM 130 may be configured as 512M, 1G, 2G, etc. according to the memory capacity.

The recognition unit 140 is configured as an EEPROM and inputs and outputs serial data in response to the serial clock signal.

FIG. 2 is a circuit block diagram of the internal memory chip of FIG. 1. 2, the SDRAM 130 according to the present invention includes an address register 202, a timing register 204, a mode register 206, a mode setting circuit 207, a row decoder 208, A column decoder 210, a memory cell array 212, a data input buffer and a data input register 214, a data output buffer 216, a data strobe output buffer 218, a DLL 220, and the like.

The address register 202 inputs and buffers a bank address signal and an address signal ADD to provide a row address, a column address, a mode set address, and the like in response to a timing control signal.

The timing register 204 inputs and buffers external timing control signals such as CKE, CS, RAS, CAS, and WE to generate internal timing control signals.

The mode register 206 latches a mode set address in response to a timing control signal, eg, a mode set command, to store mode set information.

The mode setting circuit 207 includes a mode setting decoder MRD, a first fuse circuit FS1, a second fuse circuit FS2, a normal operation circuit NC, and a test operation circuit TC.

Referring to FIG. 3, the mode setting decoder MRD decodes the MRS command MRSCMD signal and the mode setting address bits Ai and Aj through the gates of G1 to G4 to output four mode setting control signals MRS1 to MRS4. Output each of them.

In the first fuse circuit FS1 and the second fuse circuit FS2, the output is converted from a state of '0' or '1' to a state of '1' or '0' by cutting a fuse through a transient current. It consists of a fuse circuit.

In a normal memory chip, all of FS2 is turned off and all of FS1 are turned on so that the MRS1 to MRS4 signals are applied to the normal operation circuit. Therefore, in the normal operation, the mode setting control signals MRS1 to MRS4 are generated when the address bits Ai and Aj are changed externally, and the normal operation circuit is programmed by the corresponding mode setting.

In the test memory chip, all of FS1 is turned off and FS2 is all turned on. Therefore, during the test operation, the mode setting control signals MRS1 to MRS4 are generated when the address bit Ai and Aj values are changed externally, and the test operation circuit is programmed by the corresponding mode setting.

4 shows an example of a mode register setting code table according to the present invention.

That is, four test modes can be set by the address bits Ai and Aj. As shown in the drawing, the access time (tAC) value of the DRAM can be programmed to be set while changing the operating margin little by little, such as + 100ps, + 200ps, -100ps, -200ps, and the like.

5 is a flowchart for describing a test operation of the semiconductor memory module of FIG. 1.

First, the test memory module (TMM) is mounted on the module test equipment (S10). Here, the test memory module TMM refers to a memory module including the above-described test mode programmable memory chips, and refers to a module in which internal chips are fused in a test mode.

The SPD read command is transmitted to the memory module mounted in the test equipment, and the initial value information of the mounted memory module is interpreted by receiving the SPD code value read from the recognition unit of the module (S12).

The TMM is initialized according to the analyzed initial value information (S14).

Subsequently, mode set address information is provided to the initialized TMM, and an MRS command is issued to set the mode in the first test mode (S16).

Subsequently, the memory module is tested according to the given test pattern, and the test result is analyzed (S18).

If the optimal operating margin is not determined by the test result analysis, the mode change is performed (S20), and the steps S16 and S18 are repeated.

When the optimum operating margin is detected by the test, the test result is stored (S22).

For example, in this manner, the optimum access time can be set while changing the access time of the memory chip from the initial value to four steps from + 200ps to -200ps.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

As described above, the present invention can be tested while changing the operation margin little by little in the test of the memory module so that one test memory module can be used to easily detect the optimum operating margin. Therefore, since all four conventional test memory modules can be tested by one test module, test costs can be reduced and test work efficiency can be improved.

1 is a block diagram of a semiconductor memory module according to the present invention.

FIG. 2 is a circuit block diagram of the internal memory chip of FIG. 1. FIG.

FIG. 3 is a diagram illustrating one mode setting circuit of the semiconductor memory chip of FIG. 2. FIG.

4 is a diagram showing an example of a mode register setting code table according to the present invention;

5 is a flowchart for describing a test operation of the semiconductor memory module of FIG. 1.

* Brief description of the main parts of the drawing *

100: memory module 110: circuit board

120: interface unit 130: memory chip, SDRAM

140: recognition unit, EEPROM 206: mode register

207: mode setting circuit MRD: mode setting decoder

FS1, FS2: Fusing circuit part NC: Normal operation circuit part

TC: test operation circuit

Claims (4)

A mode register for inputting and storing an external address signal having mode setting information; A mode setting decoder connected to the mode register, the mode setting decoder generating a mode setting control signal by decoding mode setting information stored in the mode register; And a fuse circuit unit which is fused to provide the mode setting control signal to the normal operation circuit unit in the normal mode and to provide the mode setting control signal to the test operation circuit unit in the test mode. A circuit board having a plurality of external input / output terminals; An interface circuit provided on the circuit board and configured to interface signal transmission between the plurality of external input terminals and an internal circuit; A mode setting control signal is generated on the circuit board, connected to the interface circuit, and decoded input mode setting information by inputting an external address signal having mode setting information, and in the normal mode, the mode setting control signal. A plurality of semiconductor memory chips which provide a normal operation circuit to the normal operation circuit, and provide the mode setting control signal to a test operation circuit in the test mode; And And a recognizing unit installed on the circuit board and storing the initial values in order to provide initial values of the semiconductor memory chips to the outside through the interface circuit when the system is initially booted. a) mounting a test memory module to the memory test equipment; b) reading initial value information from the mounted test memory module; c) initializing the test memory module in response to the read initial value information; d) providing test mode setting information to the initialized test memory module; e) setting a plurality of memory chips mounted inside the memory module to a corresponding test mode in response to provided test mode setting information; f) testing the memory module in the set test mode; g) detecting the mode setting information of the optimum operation by repeating the steps d to f while changing the test mode setting information provided to the memory module. The method of claim 3, wherein the test memory module further comprises programming a plurality of memory chips mounted therein in a test mode by fusing.