KR20050073044A - Chemical mechanical polishing method - Google Patents
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- KR20050073044A KR20050073044A KR1020040001225A KR20040001225A KR20050073044A KR 20050073044 A KR20050073044 A KR 20050073044A KR 1020040001225 A KR1020040001225 A KR 1020040001225A KR 20040001225 A KR20040001225 A KR 20040001225A KR 20050073044 A KR20050073044 A KR 20050073044A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005498 polishing Methods 0.000 title claims abstract description 33
- 239000000126 substance Substances 0.000 title claims abstract description 14
- 239000002245 particle Substances 0.000 claims abstract description 56
- 239000002002 slurry Substances 0.000 claims abstract description 34
- 238000006243 chemical reaction Methods 0.000 claims abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 230000002776 aggregation Effects 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 238000005054 agglomeration Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000007517 polishing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
본 발명은 화학적기계연마(Chemical Mechanical Polishing) 방법을 개시한다. 개시된 본 발명의 화학적기계연마 방법은, 표면 단차가 발생된 연마 대상층을 슬러리에 의한 화학 반응과 연마패드에 의한 기계적 가공을 통해 평탄화시키는 화학적기계연마 방법에 있어서, 상기 슬러리로서, 연마율을 높이면서 연마 균일성이 증가되도록 서로 다른 크기의 연마 입자를 갖는 적어도 둘 이상의 슬러리를 사용하는 것을 특징으로 한다. 본 발명에 따르면, 한 가지 종류의 슬러리 입자를 사용하여 CMP 공정을 진행하는 종래 공정과 달리, 입자 크기가 다른 두 가지 이상의 슬러리 입자를 사용하여 CMP를 진행함으로써 단차제거능력의 향상 및 빠른 연마 속도를 얻을 수 있으며, 스크래치 등의 결함 발생을 방지할 수 있다.The present invention discloses a chemical mechanical polishing method. In the chemical mechanical polishing method of the present invention, in the chemical mechanical polishing method of flattening the polishing target layer having the surface step generated by chemical reaction with a slurry and mechanical processing with a polishing pad, the slurry is used as the polishing rate while increasing the polishing rate. It is characterized by using at least two slurries having abrasive particles of different sizes to increase polishing uniformity. According to the present invention, unlike the conventional process in which the CMP process is performed using one kind of slurry particles, the CMP is progressed using two or more slurry particles having different particle sizes, thereby improving the step removal ability and increasing the polishing speed. It can obtain and it can prevent the generation of defects, such as a scratch.
Description
본 발명은 화학적기계연마(Chemical Mechanical Polishing) 방법에 관한 것으로, 특히 화학적기계연마 공정시 슬러리간 응집(Agglomeration) 및 스크래치(Scratch)의 발생을 방지할 수 있는 화학적기계연마 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical mechanical polishing method, and more particularly, to a chemical mechanical polishing method capable of preventing agglomeration and scratches between slurries in a chemical mechanical polishing process.
반도체 소자의 집적도가 증가함에 따라, 리소그라피 공정의 요구 조건에 부합하기 위해서 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP) 공정을 이용한 층간절연막의 평탄화가 필수적으로 되었다. As the degree of integration of semiconductor devices increases, planarization of an interlayer insulating film using a chemical mechanical polishing (CMP) process is essential to meet the requirements of the lithography process.
이러한 CMP 공정은 슬러리(slurry)에 의한 화학 반응과 연마패드(polishing pad)에 의한 기계적 가공이 동시에 수행되는 평탄화 공정으로서, 표면 평탄화를 위해 기존에 이용되어져 왔던 리플로우(reflow) 공정 또는 에치-백(etch-back) 공정 등과 비교해서 글로벌 평탄화를 얻을 수 있고, 또한, 저온에서 수행될 수 있다는 잇점을 갖는다.The CMP process is a planarization process in which a chemical reaction by a slurry and a mechanical processing by a polishing pad are simultaneously performed. A reflow process or etch-back that has been used for planarization of a surface is performed. Compared with an etch-back process and the like, global planarization can be obtained and also has the advantage that it can be performed at low temperatures.
또한, 상기 CMP 공정은 평탄화 공정으로 제안된 것이지만, 최근에 들어서는, 얕은 접합 소자분리(shallow trench isolation) 공정은 물론 콘택 플러그 형성을 위한 폴리실리콘막의 식각 및 금속배선의 형성을 위한 금속막의 식각 공정에 필수적으로 이용되고 있으며, 그 이용 분야가 점차 확대되고 있는 추세이다. In addition, although the CMP process has been proposed as a planarization process, in recent years, a shallow trench isolation process, as well as an etching process of a polysilicon film for forming a contact plug and an etching process of a metal film for forming a metal wiring, are described. Essentially, it is being used, and its field of use is gradually expanding.
한편, 이와 같은 CMP 공정은 일반적으로 한 종류의 슬러리를 사용하여 연마 대상층을 원하는 두께까지 연마하며, 여기서, 상기 슬러리로는 작은 입자 크기의 슬러리 및 큰 입자 크기의 슬러리 중에서 어느 하나가 사용된다. On the other hand, such a CMP process generally uses one kind of slurry to polish the layer to be polished to a desired thickness, wherein any one of a small particle size slurry and a large particle size slurry is used as the slurry.
그러나, 한 종류의 슬러리만을 사용하는 종래의 CMP 공정은, 실리카 또는 세리아 등의 단일 입자만을 사용하기 때문에 입자간 크기가 비슷하여 CMP에 가장 중요한 연마율과 균일성(Uniformity)을 향상시키는데 한계가 있었다.However, in the conventional CMP process using only one type of slurry, since only single particles such as silica or ceria are used, there is a limit in improving the polishing rate and uniformity which is the most important for CMP due to the similar size between particles. .
즉, 도 1 내지 도 2에 도시된 바와 같이, 큰 입자(2)를 갖는 슬러리는 웨이퍼(1)와 입자의 접촉점이 작아 연마율이 낮고, 작은 입자(3)를 갖는 슬러리는 웨이퍼(1)와 입자의 접촉접이 많지만 입자가 웨이퍼 표면에 들어가는 깊이가 낮아 연마율이 떨어지는 문제점을 가지고 있다.That is, as shown in FIGS. 1 and 2, the slurry having the large particles 2 has a low polishing rate due to the small contact point between the wafer 1 and the particles, and the slurry having the small particles 3 has the wafer 1. Although there is a lot of contact contact between the particles and particles, the depth of entry of the particles into the wafer surface has a problem of decreasing the polishing rate.
또한, 특정 pH 이외의 영역에서는 입자간 제타포텐셜(Zetapotential)이 -30∼30mV이하이기 때문에 강한 응집현상이 발생하였다. 이는 CMP 공정 후 스크래치를 발생시키는 주 원인이 되고 있다.In addition, in the region other than the specific pH, since the particle zetapotential is -30 to 30 mV or less, strong aggregation occurs. This is a major cause of scratching after the CMP process.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, CMP 공정시 슬러리간 응집 및 스크래치의 발생을 방지할 수 있는 화학적기계연마 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a chemical mechanical polishing method capable of preventing the occurrence of agglomeration and scratches between slurries during the CMP process, to solve the above problems.
상기와 같은 목적을 달성하기 위하여, 본 발명은 표면 단차가 발생된 연마 대상층을 슬러리에 의한 화학 반응과 연마패드에 의한 기계적 가공을 통해 평탄화시키는 화학적기계연마 방법에 있어서, 상기 슬러리로서, 연마율을 높이면서 연마 균일성이 증가되도록 서로 다른 크기의 연마 입자를 갖는 적어도 둘 이상의 슬러리를 사용하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a chemical mechanical polishing method for flattening the polishing target layer having the surface step generated by chemical reaction with a slurry and mechanical processing with a polishing pad. It is characterized by using at least two slurries having abrasive particles of different sizes to increase polishing uniformity while increasing.
여기에서, 상기 슬러리는 입자 크기가 다른 두 가지의 큰 입자 및 작은 입자를 포함하며, 상기 큰 입자와 작은 입자는 각각 50∼1000nm, 50nm이하의 크기를 갖는 것을 특징으로 한다.Here, the slurry includes two large particles and small particles having different particle sizes, and the large particles and the small particles are characterized by having a size of 50 to 1000 nm and 50 nm or less, respectively.
상기 입자 크기가 다른 두 가지 이상의 슬러리는 동일한 pH에서 30mV 이상의 제타포텐셜값을 갖는 것을 특징으로 한다. Two or more slurries having different particle sizes are characterized by having a zeta potential value of 30 mV or more at the same pH.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 5는 본 발명의 실시예에 따른 CMP 공정을 설명하기 위한 도면들로서, 이를 설명하면 다음과 같다. 여기서, 도면부호 11은 반도체 기판, 12는 금속배선, 13은 층간절연막, 14는 큰 입자, 15는 작은 입자를 각각 나타낸다. 3 to 5 are diagrams for explaining a CMP process according to an embodiment of the present invention. Reference numeral 11 denotes a semiconductor substrate, 12 metal wiring, 13 an interlayer insulating film, 14 large particles, and 15 small particles.
본 발명의 실시예에 따른 CMP 방법은 소정의 하지층에 의해 야기된 층간절연막 표면의 단차를 제거함에 있어서, 연마 공정을 진행할 때에 입자 크기가 다른 두 가지 이상의 슬러리를 사용하여 수행한다.The CMP method according to the embodiment of the present invention is performed by using two or more slurries having different particle sizes during the polishing process in removing the step difference of the interlayer insulating film surface caused by the predetermined underlayer.
자세하게, 도 3에 도시된 바와 같이, 본 발명의 CMP 방법은 금속배선(12)에 의해 표면 단차가 발생된 층간절연막(13)을 연마함에 있어서, 먼저, 입자 크기가 다른 두 가지 이상의 슬러리를 사용하여 연마를 수행한다. 여기에서, 슬러리의 조합은 입자 크기와 제타포텐셜에 의해 설정된다. 이때, 입자 크기는 큰 입자와 작은 입자를 혼합하여 사용하며, 큰 입자는 50∼100nm, 작은 입자는 50nm 이하로 사용한다.In detail, as shown in FIG. 3, in the CMP method of the present invention, in polishing the interlayer insulating film 13 in which the surface step is generated by the metal wiring 12, first, two or more slurries having different particle sizes are used. To perform polishing. Here, the combination of the slurry is set by the particle size and the zeta potential. At this time, the particle size is used by mixing the large particles and small particles, the large particles are used in 50 ~ 100nm, small particles 50nm or less.
도 4에 도시된 바와 같이, 입자 크기가 다른 두 가지 이상의 슬러리 즉, 큰 입자(14)와 작은 입자(15)를 혼합하여 CMP 공정을 진행하면, 큰 입자(14)는 웨이퍼와 접촉점이 작아 하중을 적게 받게 되고, 작은 입자(15)는 큰 입자(14)에 비해 층간절연막(13)의 표면에 고르게 분포되어 웨이퍼와 접촉점이 많아지기 때문에 단차제거능력이 우수하고, 스크래치의 유발없이 균일한 연마를 이룰 수 있게 된다. As shown in FIG. 4, when the CMP process is performed by mixing two or more slurries having different particle sizes, that is, the large particles 14 and the small particles 15, the large particles 14 have a small contact point with the wafer. The small particles 15 are more evenly distributed on the surface of the interlayer insulating film 13 than the larger particles 14, so that the contact points with the wafer are increased, so that the step removal ability is excellent and uniform polishing without causing scratches. Can be achieved.
도 5에 도시된 바와 같이, CMP 공정을 진행할 때에 pH를 조절하여 제타포텐셜값이 30mV이상 또는 -30mV이하가 되는 pH 영역에서만 슬러리를 사용한다. 여기에서, 제타포텐셜값이 -30∼30mV 영역에서 선택되는 입자들은 서로 뭉치는 효과를 발생한다. 따라서, 30mV이상 또는 -30mV이하의 입자 선택이 가능한 영역(A, B)에서 입자 크기가 다른 두 가지 이상의 슬러리를 선택하게 되면, 제타포텐셜값을 선택하는 범위가 넓어지고, 입자가 뭉치는 현상을 방지할 수 있다.As shown in FIG. 5, when the CMP process is performed, the slurry is used only in a pH range where the zeta potential value is 30 mV or more or -30 mV or less. Here, particles having a zeta potential value selected from a range of -30 to 30 mV generate agglomeration effect. Therefore, when two or more slurries having different particle sizes are selected in the regions A and B where particles can be selected to be 30 mV or more and -30 mV or less, the range for selecting the zeta potential value becomes wider, and particles are aggregated. You can prevent it.
상기와 같이, 본 발명은 한 가지 종류의 슬러리 입자를 사용하여 CMP 공정을 진행하는 종래 공정과 달리, 입자 크기가 다른 두 가지 이상의 슬러리 입자를 사용하여 CMP를 진행함으로써 단차제거능력의 향상 및 빠른 연마 속도를 얻을 수 있으며, 응집 및 스크래치 등의 결함 발생을 방지할 수 있다.As described above, the present invention is different from the conventional process of proceeding the CMP process using one kind of slurry particles, by using the two or more slurry particles having a different particle size to improve the step removal ability and rapid polishing The speed can be obtained and defects such as agglomeration and scratch can be prevented.
이상, 본 발명을 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.
이상에서와 같이, 본 발명은 입자 크기가 다른 두 가지 이상의 슬러리 입자를 사용하여 CMP를 진행함으로써 단차제거능력을 향상시키고, 응집 및 스크래치 등의 결함 발생을 방지함으로 인해 CMP 공정의 특성을 향상시킬 수 있다. As described above, the present invention can improve the step removal ability by proceeding CMP using two or more slurry particles having different particle sizes, and can improve the characteristics of the CMP process by preventing the occurrence of defects such as agglomeration and scratches. have.
도 1 내지 도2는 종래 기술에 의한 화학적기계연마 공정의 문제점을 설명하기 위한 도면.1 to 2 is a view for explaining the problem of the chemical mechanical polishing process according to the prior art.
도 3은 본 발명의 실시예에 따른 화학적기계연마 공정을 설명하기 위한 단면도.3 is a cross-sectional view for explaining a chemical mechanical polishing process according to an embodiment of the present invention.
도 4는 슬러리 입자 크기에 따른 연마 특성을 설명하기 위한 도면.4 is a view for explaining the polishing characteristics according to the slurry particle size.
도 5는 pH에 따른 제타포텐셜값의 특성을 보여주는 도면.5 is a view showing the characteristics of the zeta potential value according to the pH.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 반도체 기판 12 : 금속배선11 semiconductor substrate 12 metal wiring
13 : 층간절연막 14 : 큰 입자13 interlayer insulating film 14 large particles
15 : 작은 입자15: small particles
Claims (4)
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| KR1020040001225A KR20050073044A (en) | 2004-01-08 | 2004-01-08 | Chemical mechanical polishing method |
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| KR1020040001225A KR20050073044A (en) | 2004-01-08 | 2004-01-08 | Chemical mechanical polishing method |
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| KR20050073044A true KR20050073044A (en) | 2005-07-13 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015148295A1 (en) * | 2014-03-24 | 2015-10-01 | Cabot Microelectronics Corporation | Mixed abrasive tungsten cmp composition |
| KR20160050648A (en) * | 2014-10-30 | 2016-05-11 | 주식회사 케이씨텍 | Polishing slurry composition |
| KR20170011517A (en) * | 2015-07-23 | 2017-02-02 | 주식회사 케이씨텍 | Polishing slurry composition |
| US10077381B2 (en) | 2015-07-20 | 2018-09-18 | Kctech Co., Ltd. | Polishing slurry composition |
-
2004
- 2004-01-08 KR KR1020040001225A patent/KR20050073044A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015148295A1 (en) * | 2014-03-24 | 2015-10-01 | Cabot Microelectronics Corporation | Mixed abrasive tungsten cmp composition |
| US9303190B2 (en) | 2014-03-24 | 2016-04-05 | Cabot Microelectronics Corporation | Mixed abrasive tungsten CMP composition |
| CN106415796A (en) * | 2014-03-24 | 2017-02-15 | 嘉柏微电子材料股份公司 | Mixed abrasive tungsten CMP composition |
| KR20160050648A (en) * | 2014-10-30 | 2016-05-11 | 주식회사 케이씨텍 | Polishing slurry composition |
| US10077381B2 (en) | 2015-07-20 | 2018-09-18 | Kctech Co., Ltd. | Polishing slurry composition |
| KR20170011517A (en) * | 2015-07-23 | 2017-02-02 | 주식회사 케이씨텍 | Polishing slurry composition |
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