KR20050070528A - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR20050070528A KR20050070528A KR1020030100168A KR20030100168A KR20050070528A KR 20050070528 A KR20050070528 A KR 20050070528A KR 1020030100168 A KR1020030100168 A KR 1020030100168A KR 20030100168 A KR20030100168 A KR 20030100168A KR 20050070528 A KR20050070528 A KR 20050070528A
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- 239000002184 metal Substances 0.000 title claims abstract description 111
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 230000009977 dual effect Effects 0.000 claims abstract description 30
- 238000009713 electroplating Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000000126 substance Substances 0.000 claims description 25
- 238000007517 polishing process Methods 0.000 claims description 24
- 238000005260 corrosion Methods 0.000 claims description 19
- 230000007797 corrosion Effects 0.000 claims description 19
- 239000003112 inhibitor Substances 0.000 claims description 19
- 239000007800 oxidant agent Substances 0.000 claims description 17
- 239000002002 slurry Substances 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 15
- 238000005498 polishing Methods 0.000 claims description 13
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 9
- BJEPYKJPYRNKOW-UHFFFAOYSA-N malic acid Chemical compound OC(=O)C(O)CC(O)=O BJEPYKJPYRNKOW-UHFFFAOYSA-N 0.000 claims description 6
- 239000012964 benzotriazole Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000003755 preservative agent Substances 0.000 claims description 4
- 230000002335 preservative effect Effects 0.000 claims description 4
- BJEPYKJPYRNKOW-REOHCLBHSA-N (S)-malic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O BJEPYKJPYRNKOW-REOHCLBHSA-N 0.000 claims description 3
- 235000011090 malic acid Nutrition 0.000 claims description 3
- 239000001630 malic acid Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 6
- 239000010410 layer Substances 0.000 description 66
- 239000011229 interlayer Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- -1 and H 2 O 2 Substances 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000035622 drinking Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 듀얼 다마신 패턴이 형성된 절연막의 전체 표면에 장벽 금속층보다 저항이 낮은 금속층과 장벽 금속층을 순차적으로 형성하고 듀얼 다마신 패턴 내부에 금속 시드층을 형성한 후, 전기 도금법으로 듀얼 다마신 패턴 내부에 금속 배선을 형성함으로써, 장벽 금속층의 비저항값이 높다하더라도 장벽 금속층 하부에 형성된 낮은 비저항값의 금속층을 통해 반도체 기판의 전체 영역에 전류 밀도를 고르게 분포시켜 금속 배선의 두께를 정확하고 균일하게 조절할 수 있다. The present invention relates to a method for forming a metal wiring of a semiconductor device, the metal layer having a lower resistance than the barrier metal layer and the barrier metal layer are sequentially formed on the entire surface of the insulating film on which the dual damascene pattern is formed, and the metal seed layer is formed inside the dual damascene pattern. After forming, the metal wiring is formed inside the dual damascene pattern by electroplating, so that the current density is evenly distributed over the entire area of the semiconductor substrate through the low resistivity metal layer formed under the barrier metal layer even if the resistivity value of the barrier metal layer is high. The thickness of the metal wiring can be adjusted accurately and uniformly.
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 전기 도금법을 이용한 반도체 소자의 금속배선 형성방법에 관한 것이다. The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device using an electroplating method.
RF IC에서 Si CMOS 테크널러지를 구현하기 위한 필수적인 소자가 인덕터(Inductor)이다. 그러나, 스탠다드 로직(Standard logic) 공정으로는 RF IC에서 요구되는 Q(Quality Factor; 충실도)를 얻을 수 없으며, 높은 Q값을 확보하기 위해서는 두껍고 균일한 메탈 라인을 형성하면서 기생저항 성분을 줄여야 한다. An inductor is an essential device for implementing Si CMOS technology in RF ICs. However, the standard logic process cannot obtain the Q (Quality Factor) required by the RF IC, and in order to secure high Q values, parasitic resistance components must be reduced while forming thick and uniform metal lines.
현재, 반도체 제조 기술에서 배선용으로 사용되는 물질 중 Cu의 경우 타 금속에 비해 낮은 저항을 갖고 있어 인덕터 소자 구현에 많이 사용되는 추세이다. 그러나, 일반적인 반도체 제조 기술로는 수 um 이상의 두께를 갖는 메탈 라인을 균일한 두께로 구현하기가 불가능하다. 그 이유는 수 um 이상 깊이로 절연막을 식각하거나, 수 um 이상의 금속을 제거하는 공정상의 어려움이 있기 때문이다. Currently, Cu, which is used for wiring in semiconductor manufacturing technology, has a lower resistance than other metals, and thus is used in inductor devices. However, it is impossible to realize a metal line having a thickness of several um or more with a uniform thickness using a general semiconductor manufacturing technique. This is because there is a difficulty in etching the insulating film to a depth of several um or more or removing a metal of several um or more.
이러한 문제를 해결하기 위하여 종래에는 포지티브 PR에 빛을 조사하는 시간으로 PR이 현상(Development)되는 깊이를 조절함으로써, 최종적으로 인덕터를 형성하기 위하여 형성되는 메탈 라인의 두께를 조절한다. 이때, 일반적인 CMP 방법으로는 수 um 이상의 Cu를 제거하는데 어려움이 있으므로, PR 상부에 장벽 금속층과 1000Å 내지 2000Å의 Cu 시드층을 형성하고 CMP로 구리 시드층을 PR의 트렌치에만 잔류시킨 후 전기 도금법으로 트렌치에만 Cu를 형성한다. 이때, 장벽 금속층은 일만적으로 Ta 또는 TaN의 단일층이나 이들의 적층 구조로 형성된다. In order to solve this problem, conventionally, by adjusting the depth at which PR is developed at the time of irradiating light on the positive PR, the thickness of the metal line formed to finally form the inductor is controlled. At this time, since it is difficult to remove Cu over several um by the general CMP method, a barrier metal layer and a Cu seed layer of 1000 kPa to 2000 kPa are formed on the PR, and the copper seed layer is left only in the trenches of PR with electroplating after CMP. Cu is formed only in the trench. At this time, the barrier metal layer is formed in a single layer of Ta or TaN or a laminated structure thereof.
그러나, 이러한 방법을 이용할 경우, 장벽 금속층의 높은 저항으로 인하여 전기도금 공정 시 웨이퍼의 가장자리(Edge)에서는 Cu가 두껍게 도금되고 중앙 부위에서는 얇게 도금되는 문제점이 발생된다. However, when using this method, the high resistance of the barrier metal layer causes a problem that Cu is thickly plated at the edge of the wafer and thinly plated at the center portion during the electroplating process.
이에 대하여, 본 발명이 제시하는 반도체 소자의 금속 배선 형성 방법은 듀얼 다마신 패턴이 형성된 절연막의 전체 표면에 장벽 금속층보다 저항이 낮은 금속층과 장벽 금속층을 순차적으로 형성하고 듀얼 다마신 패턴 내부에 금속 시드층을 형성한 후, 전기 도금법으로 듀얼 다마신 패턴 내부에 금속 배선을 형성함으로써, 장벽 금속층의 비저항값이 높다하더라도 장벽 금속층 하부에 형성된 낮은 비저항값의 금속층을 통해 반도체 기판의 전체 영역에 전류 밀도를 고르게 분포시켜 금속 배선의 두께를 정확하고 균일하게 조절할 수 있다. In contrast, in the method of forming a metal wiring of a semiconductor device according to the present invention, a metal layer having a lower resistance than a barrier metal layer and a barrier metal layer are sequentially formed on the entire surface of the insulating film on which the dual damascene pattern is formed, and the metal seed is formed inside the dual damascene pattern. After the layer is formed, a metal wiring is formed inside the dual damascene pattern by electroplating, so that the current density is applied to the entire region of the semiconductor substrate through the low resistivity metal layer formed under the barrier metal layer even if the resistivity value of the barrier metal layer is high. By evenly distributing, the thickness of metal wires can be adjusted accurately and uniformly.
본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법은 반도체 기판 상에 절연막을 형성하는 단계와, 절연막에 듀얼 다마신 패턴을 형성하는 단계와, 듀얼 다마신 패턴을 포함한 전체 구조 상에 전기 도금 시 전류 전달을 위한 금속층을 형성하는 단계와, 금속층 상에 장벽 금속층을 형성하는 단계와, 듀얼 다마신 패턴 내부에 금속 시드층을 형성하는 단계와, 전기 도금법으로 듀얼 다마신 패턴 내부에 금속 배선을 형성하는 단계, 및 절연막 상부의 전도성 물질을 제거하는 단계를 포함한다. According to an embodiment of the present invention, a method of forming a metal wiring of a semiconductor device includes forming an insulating film on a semiconductor substrate, forming a dual damascene pattern on the insulating film, and electroplating the entire structure including the dual damascene pattern. Forming a metal layer for transferring electric current, forming a barrier metal layer on the metal layer, forming a metal seed layer inside the dual damascene pattern, and metal wiring inside the dual damascene pattern by electroplating. Forming and removing the conductive material over the insulating film.
상기에서, 절연막은 감광막으로 형성할 수 있다. In the above, the insulating film may be formed as a photosensitive film.
금속층의 비저항값이 장벽 금속층의 비저항값보다 작으며, 금속층은 구리로 이루어지는 것이 바람직하다. It is preferable that the specific resistance value of a metal layer is smaller than the specific resistance value of a barrier metal layer, and a metal layer consists of copper.
한편, 금속 시드층은 듀얼 다마신 패턴을 포함한 전체 구조상에 형성된 후 화학적 기계적 연마 공정에 의해 듀얼 다마신 패턴의 내부에만 잔류될 수 있다. Meanwhile, the metal seed layer may be formed on the entire structure including the dual damascene pattern and then remain only inside the dual damascene pattern by a chemical mechanical polishing process.
화학적 기계적 연마 공정 시 연마제가 0wt% 내지 5wt% 포함된 슬러리가 공급된다. 슬러리에는 DL_말산, 메탄올, 벤조트리아졸 또는 사과산이 포함될 수 있다. In the chemical mechanical polishing process, a slurry containing 0 wt% to 5 wt% of an abrasive is supplied. The slurry may include DL malic acid, methanol, benzotriazole or malic acid.
한편, 화학적 기계적 연마 공정의 연마율을 산화제 또는 부식방지제로 조절할 수 있다. On the other hand, the polishing rate of the chemical mechanical polishing process can be adjusted with an oxidizing agent or a corrosion inhibitor.
부식 방지제를 사용하여 연마율을 조절하는 화학적 기계적 연마 공정은, 부식방지제를 10초 내지 3분 동안 패드에 공급하여 금속 시드층의 표면과 접촉시키는 단계와, 화학적 기계적 연마 공정을 실시하는 중간에 슬러리의 공급을 중단하고, 부식방지제를 10초 내지 3분 동안 공급하는 단계, 및 화학적 기계적 연마 공정을 완료한 후, 부식방지제를 10초 내지 3분 동안 공급하는 단계를 포함한다. 이때, 부식 방지제는 BTA가 될 수 있으며, 부식방지제의 농도는 0.01wt% 내지 1wt%로 설정할 수 있다. A chemical mechanical polishing process that uses a corrosion inhibitor to control the polishing rate includes supplying a corrosion inhibitor to the pad for 10 seconds to 3 minutes to contact the surface of the metal seed layer, and a slurry in between the chemical mechanical polishing process. Supplying the preservative for 10 seconds to 3 minutes, and supplying the preservative for 10 seconds to 3 minutes after completing the chemical mechanical polishing process. At this time, the corrosion inhibitor may be BTA, the concentration of the corrosion inhibitor may be set to 0.01wt% to 1wt%.
산화제를 사용하여 연마율을 조절하는 화학적 기계적 연마 공정에서, 슬러리와 혼합되는 산화제의 혼합비가 1wt% 내지 50wt%이다. 이때, 산화제는 H2O2, Fe(NO3)3, KIO2, H5IO6가 될 수 있다.In a chemical mechanical polishing process in which the oxidizing agent is used to adjust the polishing rate, the mixing ratio of the oxidizing agent mixed with the slurry is 1 wt% to 50 wt%. At this time, the oxidizing agent may be H 2 O 2 , Fe (NO 3 ) 3 , KIO 2 , H 5 IO 6 .
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.
한편, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다. 또한 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되었다. 도면 상에서 동일 부호는 동일한 요소를 지칭한다.On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.1A through 1E are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소(도시되지 않음)가 형성된 반도체 기판(101)이 제공된다. 예를 들면, 반도체 기판(101)에는 트랜지스터나 메모리 셀(도시되지 않음)이 형성될 수 있다. 이어서, 반도체 기판(101) 상에 층간 절연막(102)을 형성한 후, 듀얼 다마신 공정으로 층간 절연막(102)에 비아홀(103a)과 트렌치(103b)로 이루어진 듀얼 다마신 패턴(103)을 형성한다. 여기서, 층간 절연막(102)은 감광막으로 형성할 수 있다.Referring to FIG. 1A, referring to FIG. 1A, a semiconductor substrate 101 is provided on which various elements (not shown) are formed for forming a semiconductor device. For example, a transistor or a memory cell (not shown) may be formed in the semiconductor substrate 101. Subsequently, after the interlayer insulating film 102 is formed on the semiconductor substrate 101, the dual damascene pattern 103 including the via holes 103a and the trench 103b is formed in the interlayer insulating film 102 by a dual damascene process. do. Here, the interlayer insulating film 102 may be formed of a photosensitive film.
도 1b를 참조하면, 듀얼 다마신 패턴(103)을 포함한 전체 구조 상에 금속층(104)과 장벽 금속층(105)을 순차적으로 형성한다. 여기서, 장벽 금속층(105)은 Ta막 또는 Ta/TaN막으로 형성할 수 있으며, 50Å 내지 1000Å의 두께로 형성할 수 있다. 한편, 금속층(104)은 장벽 금속층(105)보다 낮은 비저항값을 갖는 금속 물질을 100Å 내지 5000Å의 두께만큼 증착하여 형성할 수 있으며, 구리로 형성하는 것이 바람직하다. Referring to FIG. 1B, the metal layer 104 and the barrier metal layer 105 are sequentially formed on the entire structure including the dual damascene pattern 103. Here, the barrier metal layer 105 may be formed of a Ta film or a Ta / TaN film, and may be formed to have a thickness of 50 μs to 1000 μs. On the other hand, the metal layer 104 may be formed by depositing a metal material having a specific resistance lower than the barrier metal layer 105 by a thickness of 100 kPa to 5000 kPa, preferably formed of copper.
도 1c를 참조하면, 듀얼 다마신 패턴(103)의 측벽 및 저면에 금속 시드층(106)을 형성한다. 금속 시드층(103)은 구리로 형성하는 것이 바람직하다. 한편, 듀얼 다마신 패턴(103)을 포함한 전체 구조 상에 금속 시드층을 형성한 후 화학적 기계적 연마 공정으로 층간 절연막(102) 상의 금속 시드층을 제거하는 방법으로 금속 시드층(103)을 듀얼 다마신 패턴(103)의 측벽 및 저면에만 형성할 수 있다. Referring to FIG. 1C, the metal seed layer 106 is formed on sidewalls and bottom surfaces of the dual damascene pattern 103. The metal seed layer 103 is preferably formed of copper. Meanwhile, the metal seed layer 103 is formed by forming a metal seed layer on the entire structure including the dual damascene pattern 103 and then removing the metal seed layer on the interlayer insulating layer 102 by a chemical mechanical polishing process. It may be formed only on the side walls and the bottom surface of the drinking pattern 103.
이때, 화학적 기계적 공정 시 연마제가 없는 슬러리(Abrasive free slurry)나 연마제(Abrasive)가 5wt% 이하로 함유된 슬러리를 사용하여 금속 시드층을 제거할 수 있다. 한편, 슬러리에는 DL_말산(DL_malicacid), 메탄올(Methanol), 벤조트리아졸(Benzotriazole) 또는 사과산이 포함될 수 있다. In this case, the metal seed layer may be removed by using an abrasive free slurry or an slurry containing 5 wt% or less of the abrasive during chemical and mechanical processes. Meanwhile, the slurry may include DL_malic acid, methanol, benzotriazole, or malic acid.
그리고, 산화제나 부식방지제를 사용하여 금속 시드층(106)의 연마율을 조절할 수 있다. In addition, the polishing rate of the metal seed layer 106 may be adjusted using an oxidizing agent or a corrosion inhibitor.
예를 들어, 금속 시드층(106)이 구리로 이루어진 경우, 구리 산화제(예를 들면, H2O2) 또는 구리 부식방지제(예를 들면, BenzoTriaZole; BTA)로 금속 시드층(106)의 연마율을 조절할 수 있다. 좀 더 구체적으로 설명하면 다음과 같다.For example, when the metal seed layer 106 is made of copper, polishing the metal seed layer 106 with a copper oxidant (eg H 2 O 2 ) or a copper preservative (eg BenzoTriaZole; BTA) You can adjust the rate. More specifically, it is as follows.
먼저, 부식 방지제로 연마율을 조절하는 경우에는, 화학적 기계적 연마 공정을 실시하기 전에 부식방지제로 농도가 0.01wt% 내지 1wt%인 BTA를 10초 내지 3분 동안 패드에 공급하여 금속 시드층(106)의 표면과 접촉시킨다. 이어서, 듀얼 다마신 패턴(103)의 내부에 형성된 금속 시드층(106)을 보호하기 위하여 화학적 기계적 연마 공정을 실시하는 과정에서 슬러리의 공급을 중단하고 부식방지제를 공급한다. 이때, 5psi 이하의 압력과 플래이튼의 회전 속도가 600rpm 이하인 상태에서 부식방지제를 공급하며, 부식방지제로 농도가 0.01wt% 내지 1wt%인 BTA를 10초 내지 3분 동안 공급할 수 있다. 다시, 슬러리를 공급하면서 화학적 기계적 연마 공정을 실시한다. 화학적 기계적 연마 공정이 완료된 후에는 다시 부식방지제로 농도가 0.01wt% 내지 1wt%인 BTA를 10초 내지 3분 동안 공급한다. First, in the case of adjusting the polishing rate with a corrosion inhibitor, before performing the chemical mechanical polishing process, BTA having a concentration of 0.01 wt% to 1 wt% as a corrosion inhibitor is supplied to the pad for 10 seconds to 3 minutes to provide a metal seed layer 106. ) In contact with the surface. Subsequently, in order to protect the metal seed layer 106 formed in the dual damascene pattern 103, the supply of the slurry is stopped and the corrosion inhibitor is supplied during the chemical mechanical polishing process. At this time, the pressure of 5psi or less and the rotational speed of the platen is 600rpm or less in the state of supplying a corrosion inhibitor, BTA with a concentration of 0.01wt% to 1wt% can be supplied for 10 seconds to 3 minutes. Again, a chemical mechanical polishing process is performed while feeding the slurry. After completion of the chemical mechanical polishing process, BTA with a concentration of 0.01 wt% to 1 wt% is supplied again as a corrosion inhibitor for 10 seconds to 3 minutes.
한편, 산화제로 연마율을 조절하는 경우에는, 슬러리와 혼합되는 산화제의 혼합비를 1wt% 내지 50wt%로 조절하며, 이 범위 내에서도 20wt% 내지 40wt%로 조절하는 것이 바람직하다. 이때, 산화제로 H2O2를 사용할 수 있다. 슬러리와 산화제를 혼합한 상태에서 화학적 기계적 연마 공정을 실시하다가, 듀얼 다마신 패턴(103)이 형성된 영역 이외의 영역(도시되지 않음)에서 금속 시드층이 제거되어 장벽 금속층이 노출될때 화학적 기계적 연마 공정을 종료한다. 이렇게, 장벽 금속층이 노출되는 시점을 연마 종료 시점으로 하는 경우, 장벽 금속층과 금속(예를 들면, 구리)의 연마비가 1:1 내지 1:5000이 되도록 슬러리와 산화제의 혼합비를 조절하는 것이 바람직하다.On the other hand, when adjusting the polishing rate with the oxidizing agent, it is preferable to adjust the mixing ratio of the oxidizing agent mixed with the slurry to 1wt% to 50wt%, even within this range to 20wt% to 40wt%. At this time, H 2 O 2 may be used as the oxidizing agent. The chemical mechanical polishing process is performed in a state in which the slurry and the oxidant are mixed, and then the chemical mechanical polishing process is removed when the barrier metal layer is exposed by removing the metal seed layer in a region other than the region where the dual damascene pattern 103 is formed (not shown). To exit. Thus, when the time point at which the barrier metal layer is exposed is the end point of polishing, it is preferable to adjust the mixing ratio of the slurry and the oxidant so that the polishing ratio of the barrier metal layer and the metal (for example, copper) is 1: 1 to 1: 5000. .
한편, 장벽 금속층과 금속의 연마비를 조절하기 위하여 산화제와 부식 방지제를 사용할 수 있다. 이때, 부식 방지제로는 BTA를 사용할 수 있으며, 산화제로는 H2O2, Fe(NO3)3, KIO2, H5IO6를 사용할 수 있다.On the other hand, an oxidizing agent and a corrosion inhibitor may be used to control the polishing ratio of the barrier metal layer and the metal. In this case, BTA may be used as a corrosion inhibitor, and H 2 O 2 , Fe (NO 3 ) 3 , KIO 2 , or H 5 IO 6 may be used as the oxidizing agent.
도 1d를 참조하면, 전기 도금법으로 듀얼 다마신 패턴(103) 내부를 금속 물질로 매립하여 금속 배선(107)을 형성한다. 이때, 금속 배선(107)은 구리로 형성하는 것이 바람직하다. Referring to FIG. 1D, the inside of the dual damascene pattern 103 is embedded with a metal material by an electroplating method to form a metal wiring 107. At this time, the metal wiring 107 is preferably formed of copper.
전기 도금법을 실시하기 위해서는 장벽 금속층(105)에 소정의 전압을 인가해야 하는데, 장벽 금속층(105)의 비저항값이 높기 때문에 종래에는 반도체 기판(101)의 전체 영역에서 부분별로 전류 밀도가 달라져 전기 도금이 균일하게 이루어지지 않았다. 하지만, 장벽 금속층(105)보다 낮은 비저항값을 갖는 금속층(104)이 장벽 금속층(105)의 하부에 형성되어 있기 때문에, 대부분이 전류가 금속층(104)을 통해 고른 밀도로 반도체 기판(101)의 전체 영역에 전달되어 전기 도금이 균일하게 이루어진다. 따라서, 장벽 금속층(105)의 높은 저항이나 반도체 기판(101)의 영역에 상관없이 전류 밀도를 고르게 분포시킬 수 있어 금속 배선(107)의 두께를 정확하고 균일하게 조절할 수 있다. In order to perform the electroplating method, a predetermined voltage must be applied to the barrier metal layer 105. However, since the resistivity value of the barrier metal layer 105 is high, the current density of the entire region of the semiconductor substrate 101 is different, so that electroplating is performed. This was not done uniformly. However, since the metal layer 104 having a lower resistivity than the barrier metal layer 105 is formed under the barrier metal layer 105, most of the currents of the semiconductor substrate 101 have a uniform density through the metal layer 104. It is transmitted to the whole area and the electroplating is made uniform. Therefore, the current density can be evenly distributed regardless of the high resistance of the barrier metal layer 105 or the region of the semiconductor substrate 101, so that the thickness of the metal wiring 107 can be adjusted accurately and uniformly.
한편, 전기 도금법을 실시하기 전에, 장벽 금속층(105)의 표면에는 산화막(예를 들면, 자연 산화막; 도시되지 않음)이 형성되어 있을 수 있으나, 장벽 금속층(105)에 전압을 인가하면, 산화막이 파고되면서 전류가 공급되기 때문에 산화막으로 인하여 문제가 발생되지는 않는다. On the other hand, before the electroplating method, an oxide film (for example, a natural oxide film; not shown) may be formed on the surface of the barrier metal layer 105. However, when a voltage is applied to the barrier metal layer 105, the oxide film may be formed. Since the current is supplied while digging, the problem does not occur due to the oxide film.
도 1e를 참조하면, 층간 절연막(102) 상부의 전도성 물질들(예를 들면, 장벽 금속층, 금속층 등등)을 제거한다. 전도성 물질들은 화학적 기계적 연마 공정으로 제거할 수 있다.Referring to FIG. 1E, conductive materials (eg, barrier metal layer, metal layer, etc.) on the interlayer insulating layer 102 are removed. Conductive materials can be removed by a chemical mechanical polishing process.
상술한 바와 같이, 본 발명은 듀얼 다마신 패턴이 형성된 절연막의 전체 표면에 장벽 금속층보다 저항이 낮은 금속층과 장벽 금속층을 순차적으로 형성하고 듀얼 다마신 패턴 내부에 금속 시드층을 형성한 후, 전기 도금법으로 듀얼 다마신 패턴 내부에 금속 배선을 형성함으로써, 장벽 금속층의 비저항값이 높다하더라도 장벽 금속층 하부에 형성된 낮은 비저항값의 금속층을 통해 반도체 기판의 전체 영역에 전류 밀도를 고르게 분포시켜 금속 배선의 두께를 정확하고 균일하게 조절할 수 있다. As described above, the present invention sequentially forms a metal layer having a lower resistance than the barrier metal layer and the barrier metal layer on the entire surface of the insulating film on which the dual damascene pattern is formed, and forming a metal seed layer inside the dual damascene pattern, followed by an electroplating method. By forming the metal wiring inside the dual damascene pattern, even if the resistivity of the barrier metal layer is high, the current density is evenly distributed over the entire area of the semiconductor substrate through the low resistivity metal layer formed under the barrier metal layer, thereby reducing the thickness of the metal wiring. It can be adjusted accurately and uniformly.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.1A through 1E are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 반도체 기판 102 : 층간 절연막101 semiconductor substrate 102 interlayer insulating film
103a : 비아홀 103b : 트렌치103a: via hole 103b: trench
103 : 듀얼 다마신 패턴 104 : 금속층103: dual damascene pattern 104: metal layer
105 : 장벽 금속층 106 : 금속 시드층105: barrier metal layer 106: metal seed layer
107 : 금속 배선107: metal wiring
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030100168A KR20050070528A (en) | 2003-12-30 | 2003-12-30 | Method of forming a metal wiring in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20050070528A (en) |
-
2003
- 2003-12-30 KR KR1020030100168A patent/KR20050070528A/en not_active Application Discontinuation
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